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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Local BIST for arrays
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// Pass array inputs through, or generate locally for test/manual access.
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// May want status_valid, ctl_valid sigs.
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// Want separate cmds for enter/exit functional?
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// ctl:
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// 00000000 - functional mode
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// 800000aa - read adr aa
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// 900000aa - write adr aa (next 3 cycs are data)
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// F00000tt - run bist test tt
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//
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// status:
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//
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//
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`timescale 1 ns / 1 ns
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module ra_bist (
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clk,
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reset,
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ctl,
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status,
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rd0_enb_in,
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rd0_adr_in,
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rd1_enb_in,
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rd1_adr_in,
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wr0_enb_in,
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wr0_adr_in,
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wr0_dat_in,
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rd0_enb_out,
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rd0_adr_out,
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rd0_dat,
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rd1_enb_out,
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rd1_adr_out,
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rd1_dat,
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wr0_enb_out,
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wr0_adr_out,
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wr0_dat_out
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);
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parameter GENMODE = 0; // 0=NoDelay, 1=Delay
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input clk;
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input reset;
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input [31:0] ctl;
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input rd0_enb_in;
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input [5:0] rd0_adr_in;
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input rd1_enb_in;
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input [5:0] rd1_adr_in;
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input wr0_enb_in;
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input [5:0] wr0_adr_in;
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input [71:0] wr0_dat_in;
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output [31:0] status;
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output rd0_enb_out;
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output [5:0] rd0_adr_out;
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input [71:0] rd0_dat;
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output rd1_enb_out;
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output [5:0] rd1_adr_out;
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input [71:0] rd1_dat;
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output wr0_enb_out;
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output [5:0] wr0_adr_out;
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output [71:0] wr0_dat_out;
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reg [5:0] seq_q;
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wire [5:0] seq_d;
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wire active;
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wire bist_rd0_enb;
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wire [5:0] bist_rd0_adr;
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wire bist_rd1_enb;
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wire [5:0] bist_rd1_adr;
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wire bist_wr0_enb;
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wire [5:0] bist_wr0_adr;
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wire [71:0] bist_wr0_dat;
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// ff
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always @ (posedge clk) begin
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if (reset)
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seq_q <= 6'h3F;
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else
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seq_q <= seq_d;
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end
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// do something
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assign seq_d = seq_q;
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assign active = seq_q != 6'h3F;
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assign status = 0;
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// outputs
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assign rd0_enb_out = (active) ? bist_rd0_enb : rd0_enb_in;
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assign rd0_adr_out = (active) ? bist_rd0_adr : rd0_adr_in;
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assign rd1_enb_out = (active) ? bist_rd1_enb : rd1_enb_in;
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assign rd1_adr_out = (active) ? bist_rd1_adr : rd1_adr_in;
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assign wr0_enb_out = (active) ? bist_wr0_enb : wr0_enb_in;
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assign wr0_adr_out = (active) ? bist_wr0_adr : wr0_adr_in;
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assign wr0_dat_out = (active) ? bist_wr0_dat : wr0_dat_in;
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//assign rd0_dat = (active) ? haven't done anything here yet
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endmodule
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