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588 lines
25 KiB
Plaintext
588 lines
25 KiB
Plaintext
v {xschem version=3.0.0 file_version=1.2}
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K {type=subcircuit
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format="@name @pinlist @symname"
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template="name=x1"
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}
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T {@symname} -90 -6 0 0 0.3 0.3 {}
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T {@name} 135 -1292 0 0 0.2 0.2 {}
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L 4 -130 -1280 130 -1280 {}
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L 4 -130 1280 130 1280 {}
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L 4 -130 -1280 -130 1280 {}
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L 4 130 -1280 130 1280 {}
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B 5 -152.5 -1272.5 -147.5 -1267.5 {name=WBLb_16 sig_type=std_logic dir=in }
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L 4 -150 -1270 -130 -1270 {}
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T {WBLb_16} -125 -1274 0 0 0.2 0.2 {}
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B 5 -152.5 -1252.5 -147.5 -1247.5 {name=WBL_25 sig_type=std_logic dir=in }
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L 4 -150 -1250 -130 -1250 {}
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T {WBL_25} -125 -1254 0 0 0.2 0.2 {}
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B 5 -152.5 -1232.5 -147.5 -1227.5 {name=WBLb_29 sig_type=std_logic dir=in }
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L 4 -150 -1230 -130 -1230 {}
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T {WBLb_29} -125 -1234 0 0 0.2 0.2 {}
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B 5 -152.5 -1212.5 -147.5 -1207.5 {name=WBL_30 sig_type=std_logic dir=in }
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L 4 -150 -1210 -130 -1210 {}
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T {WBL_30} -125 -1214 0 0 0.2 0.2 {}
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B 5 -152.5 -1192.5 -147.5 -1187.5 {name=WBLb_30 sig_type=std_logic dir=in }
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L 4 -150 -1190 -130 -1190 {}
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T {WBLb_30} -125 -1194 0 0 0.2 0.2 {}
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B 5 -152.5 -1172.5 -147.5 -1167.5 {name=WBL_31 sig_type=std_logic dir=in }
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L 4 -150 -1170 -130 -1170 {}
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T {WBL_31} -125 -1174 0 0 0.2 0.2 {}
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B 5 -152.5 -1152.5 -147.5 -1147.5 {name=WBLb_25 sig_type=std_logic dir=in }
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L 4 -150 -1150 -130 -1150 {}
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T {WBLb_25} -125 -1154 0 0 0.2 0.2 {}
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B 5 -152.5 -1132.5 -147.5 -1127.5 {name=WBL_28 sig_type=std_logic dir=in }
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L 4 -150 -1130 -130 -1130 {}
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T {WBL_28} -125 -1134 0 0 0.2 0.2 {}
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B 5 -152.5 -1112.5 -147.5 -1107.5 {name=WBLb_28 sig_type=std_logic dir=in }
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L 4 -150 -1110 -130 -1110 {}
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T {WBLb_28} -125 -1114 0 0 0.2 0.2 {}
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B 5 -152.5 -1092.5 -147.5 -1087.5 {name=WBL_29 sig_type=std_logic dir=in }
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L 4 -150 -1090 -130 -1090 {}
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T {WBL_29} -125 -1094 0 0 0.2 0.2 {}
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B 5 -152.5 -1072.5 -147.5 -1067.5 {name=WBLb_26 sig_type=std_logic dir=in }
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L 4 -150 -1070 -130 -1070 {}
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T {WBLb_26} -125 -1074 0 0 0.2 0.2 {}
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B 5 -152.5 -1052.5 -147.5 -1047.5 {name=WBLb_27 sig_type=std_logic dir=in }
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L 4 -150 -1050 -130 -1050 {}
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T {WBLb_27} -125 -1054 0 0 0.2 0.2 {}
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B 5 -152.5 -1032.5 -147.5 -1027.5 {name=WBL_26 sig_type=std_logic dir=in }
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L 4 -150 -1030 -130 -1030 {}
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T {WBL_26} -125 -1034 0 0 0.2 0.2 {}
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B 5 -152.5 -1012.5 -147.5 -1007.5 {name=WBL_27 sig_type=std_logic dir=in }
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L 4 -150 -1010 -130 -1010 {}
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T {WBL_27} -125 -1014 0 0 0.2 0.2 {}
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B 5 -152.5 -992.5 -147.5 -987.5 {name=WBL_17 sig_type=std_logic dir=in }
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L 4 -150 -990 -130 -990 {}
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T {WBL_17} -125 -994 0 0 0.2 0.2 {}
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B 5 -152.5 -972.5 -147.5 -967.5 {name=WBLb_21 sig_type=std_logic dir=in }
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L 4 -150 -970 -130 -970 {}
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T {WBLb_21} -125 -974 0 0 0.2 0.2 {}
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B 5 -152.5 -952.5 -147.5 -947.5 {name=WBL_24 sig_type=std_logic dir=in }
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L 4 -150 -950 -130 -950 {}
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T {WBL_24} -125 -954 0 0 0.2 0.2 {}
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B 5 -152.5 -932.5 -147.5 -927.5 {name=WBLb_24 sig_type=std_logic dir=in }
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L 4 -150 -930 -130 -930 {}
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T {WBLb_24} -125 -934 0 0 0.2 0.2 {}
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B 5 -152.5 -912.5 -147.5 -907.5 {name=WBL_22 sig_type=std_logic dir=in }
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L 4 -150 -910 -130 -910 {}
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T {WBL_22} -125 -914 0 0 0.2 0.2 {}
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B 5 -152.5 -892.5 -147.5 -887.5 {name=WBLb_23 sig_type=std_logic dir=in }
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L 4 -150 -890 -130 -890 {}
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T {WBLb_23} -125 -894 0 0 0.2 0.2 {}
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B 5 -152.5 -872.5 -147.5 -867.5 {name=WBLb_22 sig_type=std_logic dir=in }
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L 4 -150 -870 -130 -870 {}
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T {WBLb_22} -125 -874 0 0 0.2 0.2 {}
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B 5 -152.5 -852.5 -147.5 -847.5 {name=WBL_23 sig_type=std_logic dir=in }
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L 4 -150 -850 -130 -850 {}
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T {WBL_23} -125 -854 0 0 0.2 0.2 {}
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B 5 -152.5 -832.5 -147.5 -827.5 {name=WBLb_17 sig_type=std_logic dir=in }
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L 4 -150 -830 -130 -830 {}
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T {WBLb_17} -125 -834 0 0 0.2 0.2 {}
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B 5 -152.5 -812.5 -147.5 -807.5 {name=WBL_20 sig_type=std_logic dir=in }
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L 4 -150 -810 -130 -810 {}
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T {WBL_20} -125 -814 0 0 0.2 0.2 {}
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B 5 -152.5 -792.5 -147.5 -787.5 {name=WBLb_20 sig_type=std_logic dir=in }
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L 4 -150 -790 -130 -790 {}
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T {WBLb_20} -125 -794 0 0 0.2 0.2 {}
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B 5 -152.5 -772.5 -147.5 -767.5 {name=WBL_21 sig_type=std_logic dir=in }
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L 4 -150 -770 -130 -770 {}
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T {WBL_21} -125 -774 0 0 0.2 0.2 {}
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B 5 -152.5 -752.5 -147.5 -747.5 {name=WBL_18 sig_type=std_logic dir=in }
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L 4 -150 -750 -130 -750 {}
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T {WBL_18} -125 -754 0 0 0.2 0.2 {}
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B 5 -152.5 -732.5 -147.5 -727.5 {name=WBLb_19 sig_type=std_logic dir=in }
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L 4 -150 -730 -130 -730 {}
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T {WBLb_19} -125 -734 0 0 0.2 0.2 {}
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B 5 -152.5 -712.5 -147.5 -707.5 {name=WBLb_18 sig_type=std_logic dir=in }
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L 4 -150 -710 -130 -710 {}
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T {WBLb_18} -125 -714 0 0 0.2 0.2 {}
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B 5 -152.5 -692.5 -147.5 -687.5 {name=WBL_19 sig_type=std_logic dir=in }
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L 4 -150 -690 -130 -690 {}
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T {WBL_19} -125 -694 0 0 0.2 0.2 {}
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B 5 -152.5 -672.5 -147.5 -667.5 {name=WBLb_0 sig_type=std_logic dir=in }
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L 4 -150 -670 -130 -670 {}
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T {WBLb_0} -125 -674 0 0 0.2 0.2 {}
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B 5 -152.5 -652.5 -147.5 -647.5 {name=WBL_9 sig_type=std_logic dir=in }
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L 4 -150 -650 -130 -650 {}
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T {WBL_9} -125 -654 0 0 0.2 0.2 {}
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B 5 -152.5 -632.5 -147.5 -627.5 {name=WBLb_13 sig_type=std_logic dir=in }
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L 4 -150 -630 -130 -630 {}
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T {WBLb_13} -125 -634 0 0 0.2 0.2 {}
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B 5 -152.5 -612.5 -147.5 -607.5 {name=WBL_16 sig_type=std_logic dir=in }
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L 4 -150 -610 -130 -610 {}
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T {WBL_16} -125 -614 0 0 0.2 0.2 {}
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B 5 -152.5 -592.5 -147.5 -587.5 {name=WBL_14 sig_type=std_logic dir=in }
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L 4 -150 -590 -130 -590 {}
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T {WBL_14} -125 -594 0 0 0.2 0.2 {}
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B 5 -152.5 -572.5 -147.5 -567.5 {name=WBLb_15 sig_type=std_logic dir=in }
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L 4 -150 -570 -130 -570 {}
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T {WBLb_15} -125 -574 0 0 0.2 0.2 {}
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B 5 -152.5 -552.5 -147.5 -547.5 {name=WBLb_14 sig_type=std_logic dir=in }
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L 4 -150 -550 -130 -550 {}
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T {WBLb_14} -125 -554 0 0 0.2 0.2 {}
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B 5 -152.5 -532.5 -147.5 -527.5 {name=WBL_15 sig_type=std_logic dir=in }
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L 4 -150 -530 -130 -530 {}
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T {WBL_15} -125 -534 0 0 0.2 0.2 {}
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B 5 -152.5 -512.5 -147.5 -507.5 {name=WBLb_9 sig_type=std_logic dir=in }
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L 4 -150 -510 -130 -510 {}
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T {WBLb_9} -125 -514 0 0 0.2 0.2 {}
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B 5 -152.5 -492.5 -147.5 -487.5 {name=WBL_12 sig_type=std_logic dir=in }
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L 4 -150 -490 -130 -490 {}
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T {WBL_12} -125 -494 0 0 0.2 0.2 {}
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B 5 -152.5 -472.5 -147.5 -467.5 {name=WBLb_12 sig_type=std_logic dir=in }
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L 4 -150 -470 -130 -470 {}
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T {WBLb_12} -125 -474 0 0 0.2 0.2 {}
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B 5 -152.5 -452.5 -147.5 -447.5 {name=WBL_13 sig_type=std_logic dir=in }
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L 4 -150 -450 -130 -450 {}
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T {WBL_13} -125 -454 0 0 0.2 0.2 {}
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B 5 -152.5 -432.5 -147.5 -427.5 {name=WBL_10 sig_type=std_logic dir=in }
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L 4 -150 -430 -130 -430 {}
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T {WBL_10} -125 -434 0 0 0.2 0.2 {}
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B 5 -152.5 -412.5 -147.5 -407.5 {name=WBLb_11 sig_type=std_logic dir=in }
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L 4 -150 -410 -130 -410 {}
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T {WBLb_11} -125 -414 0 0 0.2 0.2 {}
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B 5 -152.5 -392.5 -147.5 -387.5 {name=WBLb_10 sig_type=std_logic dir=in }
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L 4 -150 -390 -130 -390 {}
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T {WBLb_10} -125 -394 0 0 0.2 0.2 {}
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B 5 -152.5 -372.5 -147.5 -367.5 {name=WBL_11 sig_type=std_logic dir=in }
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L 4 -150 -370 -130 -370 {}
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T {WBL_11} -125 -374 0 0 0.2 0.2 {}
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B 5 -152.5 -352.5 -147.5 -347.5 {name=WBL_1 sig_type=std_logic dir=in }
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L 4 -150 -350 -130 -350 {}
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T {WBL_1} -125 -354 0 0 0.2 0.2 {}
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B 5 -152.5 -332.5 -147.5 -327.5 {name=WBLb_5 sig_type=std_logic dir=in }
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L 4 -150 -330 -130 -330 {}
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T {WBLb_5} -125 -334 0 0 0.2 0.2 {}
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B 5 -152.5 -312.5 -147.5 -307.5 {name=WBL_8 sig_type=std_logic dir=in }
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L 4 -150 -310 -130 -310 {}
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T {WBL_8} -125 -314 0 0 0.2 0.2 {}
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B 5 -152.5 -292.5 -147.5 -287.5 {name=WBLb_8 sig_type=std_logic dir=in }
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L 4 -150 -290 -130 -290 {}
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T {WBLb_8} -125 -294 0 0 0.2 0.2 {}
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B 5 -152.5 -272.5 -147.5 -267.5 {name=WBL_6 sig_type=std_logic dir=in }
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L 4 -150 -270 -130 -270 {}
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T {WBL_6} -125 -274 0 0 0.2 0.2 {}
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B 5 -152.5 -252.5 -147.5 -247.5 {name=WBLb_7 sig_type=std_logic dir=in }
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L 4 -150 -250 -130 -250 {}
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T {WBLb_7} -125 -254 0 0 0.2 0.2 {}
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B 5 -152.5 -232.5 -147.5 -227.5 {name=WBLb_6 sig_type=std_logic dir=in }
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L 4 -150 -230 -130 -230 {}
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T {WBLb_6} -125 -234 0 0 0.2 0.2 {}
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B 5 -152.5 -212.5 -147.5 -207.5 {name=WBL_7 sig_type=std_logic dir=in }
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L 4 -150 -210 -130 -210 {}
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T {WBL_7} -125 -214 0 0 0.2 0.2 {}
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B 5 -152.5 -192.5 -147.5 -187.5 {name=WBLb_1 sig_type=std_logic dir=in }
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L 4 -150 -190 -130 -190 {}
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T {WBLb_1} -125 -194 0 0 0.2 0.2 {}
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B 5 -152.5 -172.5 -147.5 -167.5 {name=WBL_4 sig_type=std_logic dir=in }
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L 4 -150 -170 -130 -170 {}
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T {WBL_4} -125 -174 0 0 0.2 0.2 {}
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B 5 -152.5 -152.5 -147.5 -147.5 {name=WBLb_4 sig_type=std_logic dir=in }
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L 4 -150 -150 -130 -150 {}
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T {WBLb_4} -125 -154 0 0 0.2 0.2 {}
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B 5 -152.5 -132.5 -147.5 -127.5 {name=WBL_5 sig_type=std_logic dir=in }
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L 4 -150 -130 -130 -130 {}
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T {WBL_5} -125 -134 0 0 0.2 0.2 {}
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B 5 -152.5 -112.5 -147.5 -107.5 {name=WBL_2 sig_type=std_logic dir=in }
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L 4 -150 -110 -130 -110 {}
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T {WBL_2} -125 -114 0 0 0.2 0.2 {}
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B 5 -152.5 -92.5 -147.5 -87.5 {name=WBLb_3 sig_type=std_logic dir=in }
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L 4 -150 -90 -130 -90 {}
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T {WBLb_3} -125 -94 0 0 0.2 0.2 {}
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B 5 -152.5 -72.5 -147.5 -67.5 {name=WBLb_2 sig_type=std_logic dir=in }
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L 4 -150 -70 -130 -70 {}
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T {WBLb_2} -125 -74 0 0 0.2 0.2 {}
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B 5 -152.5 -52.5 -147.5 -47.5 {name=WBL_3 sig_type=std_logic dir=in }
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L 4 -150 -50 -130 -50 {}
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T {WBL_3} -125 -54 0 0 0.2 0.2 {}
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B 5 -152.5 -32.5 -147.5 -27.5 {name=WBLb_31 sig_type=std_logic dir=in }
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L 4 -150 -30 -130 -30 {}
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T {WBLb_31} -125 -34 0 0 0.2 0.2 {}
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B 5 -152.5 -12.5 -147.5 -7.5 {name=WBL_0 sig_type=std_logic dir=in }
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L 4 -150 -10 -130 -10 {}
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T {WBL_0} -125 -14 0 0 0.2 0.2 {}
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B 5 -152.5 7.5 -147.5 12.5 {name=WWL_0 sig_type=std_logic dir=in }
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L 4 -150 10 -130 10 {}
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T {WWL_0} -125 6 0 0 0.2 0.2 {}
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B 5 -152.5 27.5 -147.5 32.5 {name=RWL_0 sig_type=std_logic dir=in }
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L 4 -150 30 -130 30 {}
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T {RWL_0} -125 26 0 0 0.2 0.2 {}
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B 5 -152.5 47.5 -147.5 52.5 {name=WWL_1 sig_type=std_logic dir=in }
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L 4 -150 50 -130 50 {}
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T {WWL_1} -125 46 0 0 0.2 0.2 {}
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B 5 -152.5 67.5 -147.5 72.5 {name=RWL_1 sig_type=std_logic dir=in }
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L 4 -150 70 -130 70 {}
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T {RWL_1} -125 66 0 0 0.2 0.2 {}
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B 5 -152.5 87.5 -147.5 92.5 {name=WWL_2 sig_type=std_logic dir=in }
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L 4 -150 90 -130 90 {}
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T {WWL_2} -125 86 0 0 0.2 0.2 {}
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B 5 -152.5 107.5 -147.5 112.5 {name=RWL_2 sig_type=std_logic dir=in }
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L 4 -150 110 -130 110 {}
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T {RWL_2} -125 106 0 0 0.2 0.2 {}
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B 5 -152.5 127.5 -147.5 132.5 {name=WWL_3 sig_type=std_logic dir=in }
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L 4 -150 130 -130 130 {}
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T {WWL_3} -125 126 0 0 0.2 0.2 {}
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B 5 -152.5 147.5 -147.5 152.5 {name=RWL_3 sig_type=std_logic dir=in }
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L 4 -150 150 -130 150 {}
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T {RWL_3} -125 146 0 0 0.2 0.2 {}
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B 5 -152.5 167.5 -147.5 172.5 {name=WWL_4 sig_type=std_logic dir=in }
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L 4 -150 170 -130 170 {}
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T {WWL_4} -125 166 0 0 0.2 0.2 {}
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B 5 -152.5 187.5 -147.5 192.5 {name=RWL_4 sig_type=std_logic dir=in }
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L 4 -150 190 -130 190 {}
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T {RWL_4} -125 186 0 0 0.2 0.2 {}
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B 5 -152.5 207.5 -147.5 212.5 {name=WWL_5 sig_type=std_logic dir=in }
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L 4 -150 210 -130 210 {}
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T {WWL_5} -125 206 0 0 0.2 0.2 {}
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B 5 -152.5 227.5 -147.5 232.5 {name=RWL_5 sig_type=std_logic dir=in }
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L 4 -150 230 -130 230 {}
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T {RWL_5} -125 226 0 0 0.2 0.2 {}
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B 5 -152.5 247.5 -147.5 252.5 {name=WWL_6 sig_type=std_logic dir=in }
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L 4 -150 250 -130 250 {}
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T {WWL_6} -125 246 0 0 0.2 0.2 {}
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B 5 -152.5 267.5 -147.5 272.5 {name=RWL_6 sig_type=std_logic dir=in }
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L 4 -150 270 -130 270 {}
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T {RWL_6} -125 266 0 0 0.2 0.2 {}
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B 5 -152.5 287.5 -147.5 292.5 {name=WWL_7 sig_type=std_logic dir=in }
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L 4 -150 290 -130 290 {}
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T {WWL_7} -125 286 0 0 0.2 0.2 {}
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B 5 -152.5 307.5 -147.5 312.5 {name=RWL_7 sig_type=std_logic dir=in }
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L 4 -150 310 -130 310 {}
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T {RWL_7} -125 306 0 0 0.2 0.2 {}
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B 5 -152.5 327.5 -147.5 332.5 {name=WWL_8 sig_type=std_logic dir=in }
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L 4 -150 330 -130 330 {}
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T {WWL_8} -125 326 0 0 0.2 0.2 {}
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B 5 -152.5 347.5 -147.5 352.5 {name=RWL_8 sig_type=std_logic dir=in }
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L 4 -150 350 -130 350 {}
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T {RWL_8} -125 346 0 0 0.2 0.2 {}
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B 5 -152.5 367.5 -147.5 372.5 {name=WWL_9 sig_type=std_logic dir=in }
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L 4 -150 370 -130 370 {}
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T {WWL_9} -125 366 0 0 0.2 0.2 {}
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B 5 -152.5 387.5 -147.5 392.5 {name=RWL_9 sig_type=std_logic dir=in }
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L 4 -150 390 -130 390 {}
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T {RWL_9} -125 386 0 0 0.2 0.2 {}
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B 5 -152.5 407.5 -147.5 412.5 {name=WWL_10 sig_type=std_logic dir=in }
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L 4 -150 410 -130 410 {}
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T {WWL_10} -125 406 0 0 0.2 0.2 {}
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B 5 -152.5 427.5 -147.5 432.5 {name=RWL_10 sig_type=std_logic dir=in }
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L 4 -150 430 -130 430 {}
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T {RWL_10} -125 426 0 0 0.2 0.2 {}
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B 5 -152.5 447.5 -147.5 452.5 {name=WWL_11 sig_type=std_logic dir=in }
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L 4 -150 450 -130 450 {}
|
|
T {WWL_11} -125 446 0 0 0.2 0.2 {}
|
|
B 5 -152.5 467.5 -147.5 472.5 {name=RWL_11 sig_type=std_logic dir=in }
|
|
L 4 -150 470 -130 470 {}
|
|
T {RWL_11} -125 466 0 0 0.2 0.2 {}
|
|
B 5 -152.5 487.5 -147.5 492.5 {name=WWL_12 sig_type=std_logic dir=in }
|
|
L 4 -150 490 -130 490 {}
|
|
T {WWL_12} -125 486 0 0 0.2 0.2 {}
|
|
B 5 -152.5 507.5 -147.5 512.5 {name=RWL_12 sig_type=std_logic dir=in }
|
|
L 4 -150 510 -130 510 {}
|
|
T {RWL_12} -125 506 0 0 0.2 0.2 {}
|
|
B 5 -152.5 527.5 -147.5 532.5 {name=WWL_13 sig_type=std_logic dir=in }
|
|
L 4 -150 530 -130 530 {}
|
|
T {WWL_13} -125 526 0 0 0.2 0.2 {}
|
|
B 5 -152.5 547.5 -147.5 552.5 {name=RWL_13 sig_type=std_logic dir=in }
|
|
L 4 -150 550 -130 550 {}
|
|
T {RWL_13} -125 546 0 0 0.2 0.2 {}
|
|
B 5 -152.5 567.5 -147.5 572.5 {name=WWL_14 sig_type=std_logic dir=in }
|
|
L 4 -150 570 -130 570 {}
|
|
T {WWL_14} -125 566 0 0 0.2 0.2 {}
|
|
B 5 -152.5 587.5 -147.5 592.5 {name=RWL_14 sig_type=std_logic dir=in }
|
|
L 4 -150 590 -130 590 {}
|
|
T {RWL_14} -125 586 0 0 0.2 0.2 {}
|
|
B 5 -152.5 607.5 -147.5 612.5 {name=WWL_15 sig_type=std_logic dir=in }
|
|
L 4 -150 610 -130 610 {}
|
|
T {WWL_15} -125 606 0 0 0.2 0.2 {}
|
|
B 5 -152.5 627.5 -147.5 632.5 {name=RWL_15 sig_type=std_logic dir=in }
|
|
L 4 -150 630 -130 630 {}
|
|
T {RWL_15} -125 626 0 0 0.2 0.2 {}
|
|
B 5 -152.5 647.5 -147.5 652.5 {name=WWL_16 sig_type=std_logic dir=in }
|
|
L 4 -150 650 -130 650 {}
|
|
T {WWL_16} -125 646 0 0 0.2 0.2 {}
|
|
B 5 -152.5 667.5 -147.5 672.5 {name=RWL_16 sig_type=std_logic dir=in }
|
|
L 4 -150 670 -130 670 {}
|
|
T {RWL_16} -125 666 0 0 0.2 0.2 {}
|
|
B 5 -152.5 687.5 -147.5 692.5 {name=WWL_17 sig_type=std_logic dir=in }
|
|
L 4 -150 690 -130 690 {}
|
|
T {WWL_17} -125 686 0 0 0.2 0.2 {}
|
|
B 5 -152.5 707.5 -147.5 712.5 {name=RWL_17 sig_type=std_logic dir=in }
|
|
L 4 -150 710 -130 710 {}
|
|
T {RWL_17} -125 706 0 0 0.2 0.2 {}
|
|
B 5 -152.5 727.5 -147.5 732.5 {name=WWL_18 sig_type=std_logic dir=in }
|
|
L 4 -150 730 -130 730 {}
|
|
T {WWL_18} -125 726 0 0 0.2 0.2 {}
|
|
B 5 -152.5 747.5 -147.5 752.5 {name=RWL_18 sig_type=std_logic dir=in }
|
|
L 4 -150 750 -130 750 {}
|
|
T {RWL_18} -125 746 0 0 0.2 0.2 {}
|
|
B 5 -152.5 767.5 -147.5 772.5 {name=WWL_19 sig_type=std_logic dir=in }
|
|
L 4 -150 770 -130 770 {}
|
|
T {WWL_19} -125 766 0 0 0.2 0.2 {}
|
|
B 5 -152.5 787.5 -147.5 792.5 {name=RWL_19 sig_type=std_logic dir=in }
|
|
L 4 -150 790 -130 790 {}
|
|
T {RWL_19} -125 786 0 0 0.2 0.2 {}
|
|
B 5 -152.5 807.5 -147.5 812.5 {name=WWL_20 sig_type=std_logic dir=in }
|
|
L 4 -150 810 -130 810 {}
|
|
T {WWL_20} -125 806 0 0 0.2 0.2 {}
|
|
B 5 -152.5 827.5 -147.5 832.5 {name=RWL_20 sig_type=std_logic dir=in }
|
|
L 4 -150 830 -130 830 {}
|
|
T {RWL_20} -125 826 0 0 0.2 0.2 {}
|
|
B 5 -152.5 847.5 -147.5 852.5 {name=WWL_21 sig_type=std_logic dir=in }
|
|
L 4 -150 850 -130 850 {}
|
|
T {WWL_21} -125 846 0 0 0.2 0.2 {}
|
|
B 5 -152.5 867.5 -147.5 872.5 {name=RWL_21 sig_type=std_logic dir=in }
|
|
L 4 -150 870 -130 870 {}
|
|
T {RWL_21} -125 866 0 0 0.2 0.2 {}
|
|
B 5 -152.5 887.5 -147.5 892.5 {name=WWL_22 sig_type=std_logic dir=in }
|
|
L 4 -150 890 -130 890 {}
|
|
T {WWL_22} -125 886 0 0 0.2 0.2 {}
|
|
B 5 -152.5 907.5 -147.5 912.5 {name=RWL_22 sig_type=std_logic dir=in }
|
|
L 4 -150 910 -130 910 {}
|
|
T {RWL_22} -125 906 0 0 0.2 0.2 {}
|
|
B 5 -152.5 927.5 -147.5 932.5 {name=WWL_23 sig_type=std_logic dir=in }
|
|
L 4 -150 930 -130 930 {}
|
|
T {WWL_23} -125 926 0 0 0.2 0.2 {}
|
|
B 5 -152.5 947.5 -147.5 952.5 {name=RWL_23 sig_type=std_logic dir=in }
|
|
L 4 -150 950 -130 950 {}
|
|
T {RWL_23} -125 946 0 0 0.2 0.2 {}
|
|
B 5 -152.5 967.5 -147.5 972.5 {name=WWL_24 sig_type=std_logic dir=in }
|
|
L 4 -150 970 -130 970 {}
|
|
T {WWL_24} -125 966 0 0 0.2 0.2 {}
|
|
B 5 -152.5 987.5 -147.5 992.5 {name=RWL_24 sig_type=std_logic dir=in }
|
|
L 4 -150 990 -130 990 {}
|
|
T {RWL_24} -125 986 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1007.5 -147.5 1012.5 {name=WWL_25 sig_type=std_logic dir=in }
|
|
L 4 -150 1010 -130 1010 {}
|
|
T {WWL_25} -125 1006 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1027.5 -147.5 1032.5 {name=RWL_25 sig_type=std_logic dir=in }
|
|
L 4 -150 1030 -130 1030 {}
|
|
T {RWL_25} -125 1026 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1047.5 -147.5 1052.5 {name=WWL_26 sig_type=std_logic dir=in }
|
|
L 4 -150 1050 -130 1050 {}
|
|
T {WWL_26} -125 1046 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1067.5 -147.5 1072.5 {name=RWL_26 sig_type=std_logic dir=in }
|
|
L 4 -150 1070 -130 1070 {}
|
|
T {RWL_26} -125 1066 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1087.5 -147.5 1092.5 {name=WWL_27 sig_type=std_logic dir=in }
|
|
L 4 -150 1090 -130 1090 {}
|
|
T {WWL_27} -125 1086 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1107.5 -147.5 1112.5 {name=RWL_27 sig_type=std_logic dir=in }
|
|
L 4 -150 1110 -130 1110 {}
|
|
T {RWL_27} -125 1106 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1127.5 -147.5 1132.5 {name=WWL_28 sig_type=std_logic dir=in }
|
|
L 4 -150 1130 -130 1130 {}
|
|
T {WWL_28} -125 1126 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1147.5 -147.5 1152.5 {name=RWL_28 sig_type=std_logic dir=in }
|
|
L 4 -150 1150 -130 1150 {}
|
|
T {RWL_28} -125 1146 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1167.5 -147.5 1172.5 {name=WWL_29 sig_type=std_logic dir=in }
|
|
L 4 -150 1170 -130 1170 {}
|
|
T {WWL_29} -125 1166 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1187.5 -147.5 1192.5 {name=RWL_29 sig_type=std_logic dir=in }
|
|
L 4 -150 1190 -130 1190 {}
|
|
T {RWL_29} -125 1186 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1207.5 -147.5 1212.5 {name=WWL_30 sig_type=std_logic dir=in }
|
|
L 4 -150 1210 -130 1210 {}
|
|
T {WWL_30} -125 1206 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1227.5 -147.5 1232.5 {name=RWL_30 sig_type=std_logic dir=in }
|
|
L 4 -150 1230 -130 1230 {}
|
|
T {RWL_30} -125 1226 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1247.5 -147.5 1252.5 {name=WWL_31 sig_type=std_logic dir=in }
|
|
L 4 -150 1250 -130 1250 {}
|
|
T {WWL_31} -125 1246 0 0 0.2 0.2 {}
|
|
B 5 -152.5 1267.5 -147.5 1272.5 {name=RWL_31 sig_type=std_logic dir=in }
|
|
L 4 -150 1270 -130 1270 {}
|
|
T {RWL_31} -125 1266 0 0 0.2 0.2 {}
|
|
B 5 147.5 -1272.5 152.5 -1267.5 {name=RBL0_31 sig_type=std_logic dir=out }
|
|
L 4 130 -1270 150 -1270 {}
|
|
T {RBL0_31} 125 -1274 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1252.5 152.5 -1247.5 {name=RBL1_30 sig_type=std_logic dir=out }
|
|
L 4 130 -1250 150 -1250 {}
|
|
T {RBL1_30} 125 -1254 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1232.5 152.5 -1227.5 {name=RBL0_30 sig_type=std_logic dir=out }
|
|
L 4 130 -1230 150 -1230 {}
|
|
T {RBL0_30} 125 -1234 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1212.5 152.5 -1207.5 {name=RBL1_29 sig_type=std_logic dir=out }
|
|
L 4 130 -1210 150 -1210 {}
|
|
T {RBL1_29} 125 -1214 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1192.5 152.5 -1187.5 {name=RBL0_29 sig_type=std_logic dir=out }
|
|
L 4 130 -1190 150 -1190 {}
|
|
T {RBL0_29} 125 -1194 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1172.5 152.5 -1167.5 {name=RBL1_28 sig_type=std_logic dir=out }
|
|
L 4 130 -1170 150 -1170 {}
|
|
T {RBL1_28} 125 -1174 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1152.5 152.5 -1147.5 {name=RBL0_28 sig_type=std_logic dir=out }
|
|
L 4 130 -1150 150 -1150 {}
|
|
T {RBL0_28} 125 -1154 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1132.5 152.5 -1127.5 {name=RBL1_27 sig_type=std_logic dir=out }
|
|
L 4 130 -1130 150 -1130 {}
|
|
T {RBL1_27} 125 -1134 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1112.5 152.5 -1107.5 {name=RBL0_27 sig_type=std_logic dir=out }
|
|
L 4 130 -1110 150 -1110 {}
|
|
T {RBL0_27} 125 -1114 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1092.5 152.5 -1087.5 {name=RBL1_26 sig_type=std_logic dir=out }
|
|
L 4 130 -1090 150 -1090 {}
|
|
T {RBL1_26} 125 -1094 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1072.5 152.5 -1067.5 {name=RBL0_26 sig_type=std_logic dir=out }
|
|
L 4 130 -1070 150 -1070 {}
|
|
T {RBL0_26} 125 -1074 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1052.5 152.5 -1047.5 {name=RBL1_25 sig_type=std_logic dir=out }
|
|
L 4 130 -1050 150 -1050 {}
|
|
T {RBL1_25} 125 -1054 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1032.5 152.5 -1027.5 {name=RBL0_25 sig_type=std_logic dir=out }
|
|
L 4 130 -1030 150 -1030 {}
|
|
T {RBL0_25} 125 -1034 0 1 0.2 0.2 {}
|
|
B 5 147.5 -1012.5 152.5 -1007.5 {name=RBL1_24 sig_type=std_logic dir=out }
|
|
L 4 130 -1010 150 -1010 {}
|
|
T {RBL1_24} 125 -1014 0 1 0.2 0.2 {}
|
|
B 5 147.5 -992.5 152.5 -987.5 {name=RBL0_24 sig_type=std_logic dir=out }
|
|
L 4 130 -990 150 -990 {}
|
|
T {RBL0_24} 125 -994 0 1 0.2 0.2 {}
|
|
B 5 147.5 -972.5 152.5 -967.5 {name=RBL1_23 sig_type=std_logic dir=out }
|
|
L 4 130 -970 150 -970 {}
|
|
T {RBL1_23} 125 -974 0 1 0.2 0.2 {}
|
|
B 5 147.5 -952.5 152.5 -947.5 {name=RBL1_22 sig_type=std_logic dir=out }
|
|
L 4 130 -950 150 -950 {}
|
|
T {RBL1_22} 125 -954 0 1 0.2 0.2 {}
|
|
B 5 147.5 -932.5 152.5 -927.5 {name=RBL1_21 sig_type=std_logic dir=out }
|
|
L 4 130 -930 150 -930 {}
|
|
T {RBL1_21} 125 -934 0 1 0.2 0.2 {}
|
|
B 5 147.5 -912.5 152.5 -907.5 {name=RBL0_23 sig_type=std_logic dir=out }
|
|
L 4 130 -910 150 -910 {}
|
|
T {RBL0_23} 125 -914 0 1 0.2 0.2 {}
|
|
B 5 147.5 -892.5 152.5 -887.5 {name=RBL0_22 sig_type=std_logic dir=out }
|
|
L 4 130 -890 150 -890 {}
|
|
T {RBL0_22} 125 -894 0 1 0.2 0.2 {}
|
|
B 5 147.5 -872.5 152.5 -867.5 {name=RBL0_21 sig_type=std_logic dir=out }
|
|
L 4 130 -870 150 -870 {}
|
|
T {RBL0_21} 125 -874 0 1 0.2 0.2 {}
|
|
B 5 147.5 -852.5 152.5 -847.5 {name=RBL1_20 sig_type=std_logic dir=out }
|
|
L 4 130 -850 150 -850 {}
|
|
T {RBL1_20} 125 -854 0 1 0.2 0.2 {}
|
|
B 5 147.5 -832.5 152.5 -827.5 {name=RBL0_20 sig_type=std_logic dir=out }
|
|
L 4 130 -830 150 -830 {}
|
|
T {RBL0_20} 125 -834 0 1 0.2 0.2 {}
|
|
B 5 147.5 -812.5 152.5 -807.5 {name=RBL1_19 sig_type=std_logic dir=out }
|
|
L 4 130 -810 150 -810 {}
|
|
T {RBL1_19} 125 -814 0 1 0.2 0.2 {}
|
|
B 5 147.5 -792.5 152.5 -787.5 {name=RBL0_19 sig_type=std_logic dir=out }
|
|
L 4 130 -790 150 -790 {}
|
|
T {RBL0_19} 125 -794 0 1 0.2 0.2 {}
|
|
B 5 147.5 -772.5 152.5 -767.5 {name=RBL1_18 sig_type=std_logic dir=out }
|
|
L 4 130 -770 150 -770 {}
|
|
T {RBL1_18} 125 -774 0 1 0.2 0.2 {}
|
|
B 5 147.5 -752.5 152.5 -747.5 {name=RBL0_18 sig_type=std_logic dir=out }
|
|
L 4 130 -750 150 -750 {}
|
|
T {RBL0_18} 125 -754 0 1 0.2 0.2 {}
|
|
B 5 147.5 -732.5 152.5 -727.5 {name=RBL1_17 sig_type=std_logic dir=out }
|
|
L 4 130 -730 150 -730 {}
|
|
T {RBL1_17} 125 -734 0 1 0.2 0.2 {}
|
|
B 5 147.5 -712.5 152.5 -707.5 {name=RBL0_17 sig_type=std_logic dir=out }
|
|
L 4 130 -710 150 -710 {}
|
|
T {RBL0_17} 125 -714 0 1 0.2 0.2 {}
|
|
B 5 147.5 -692.5 152.5 -687.5 {name=RBL1_16 sig_type=std_logic dir=out }
|
|
L 4 130 -690 150 -690 {}
|
|
T {RBL1_16} 125 -694 0 1 0.2 0.2 {}
|
|
B 5 147.5 -672.5 152.5 -667.5 {name=RBL0_16 sig_type=std_logic dir=out }
|
|
L 4 130 -670 150 -670 {}
|
|
T {RBL0_16} 125 -674 0 1 0.2 0.2 {}
|
|
B 5 147.5 -652.5 152.5 -647.5 {name=RBL1_15 sig_type=std_logic dir=out }
|
|
L 4 130 -650 150 -650 {}
|
|
T {RBL1_15} 125 -654 0 1 0.2 0.2 {}
|
|
B 5 147.5 -632.5 152.5 -627.5 {name=RBL0_15 sig_type=std_logic dir=out }
|
|
L 4 130 -630 150 -630 {}
|
|
T {RBL0_15} 125 -634 0 1 0.2 0.2 {}
|
|
B 5 147.5 -612.5 152.5 -607.5 {name=RBL1_14 sig_type=std_logic dir=out }
|
|
L 4 130 -610 150 -610 {}
|
|
T {RBL1_14} 125 -614 0 1 0.2 0.2 {}
|
|
B 5 147.5 -592.5 152.5 -587.5 {name=RBL0_14 sig_type=std_logic dir=out }
|
|
L 4 130 -590 150 -590 {}
|
|
T {RBL0_14} 125 -594 0 1 0.2 0.2 {}
|
|
B 5 147.5 -572.5 152.5 -567.5 {name=RBL1_13 sig_type=std_logic dir=out }
|
|
L 4 130 -570 150 -570 {}
|
|
T {RBL1_13} 125 -574 0 1 0.2 0.2 {}
|
|
B 5 147.5 -552.5 152.5 -547.5 {name=RBL0_13 sig_type=std_logic dir=out }
|
|
L 4 130 -550 150 -550 {}
|
|
T {RBL0_13} 125 -554 0 1 0.2 0.2 {}
|
|
B 5 147.5 -532.5 152.5 -527.5 {name=RBL1_12 sig_type=std_logic dir=out }
|
|
L 4 130 -530 150 -530 {}
|
|
T {RBL1_12} 125 -534 0 1 0.2 0.2 {}
|
|
B 5 147.5 -512.5 152.5 -507.5 {name=RBL0_12 sig_type=std_logic dir=out }
|
|
L 4 130 -510 150 -510 {}
|
|
T {RBL0_12} 125 -514 0 1 0.2 0.2 {}
|
|
B 5 147.5 -492.5 152.5 -487.5 {name=RBL1_11 sig_type=std_logic dir=out }
|
|
L 4 130 -490 150 -490 {}
|
|
T {RBL1_11} 125 -494 0 1 0.2 0.2 {}
|
|
B 5 147.5 -472.5 152.5 -467.5 {name=RBL0_11 sig_type=std_logic dir=out }
|
|
L 4 130 -470 150 -470 {}
|
|
T {RBL0_11} 125 -474 0 1 0.2 0.2 {}
|
|
B 5 147.5 -452.5 152.5 -447.5 {name=RBL1_10 sig_type=std_logic dir=out }
|
|
L 4 130 -450 150 -450 {}
|
|
T {RBL1_10} 125 -454 0 1 0.2 0.2 {}
|
|
B 5 147.5 -432.5 152.5 -427.5 {name=RBL0_10 sig_type=std_logic dir=out }
|
|
L 4 130 -430 150 -430 {}
|
|
T {RBL0_10} 125 -434 0 1 0.2 0.2 {}
|
|
B 5 147.5 -412.5 152.5 -407.5 {name=RBL1_9 sig_type=std_logic dir=out }
|
|
L 4 130 -410 150 -410 {}
|
|
T {RBL1_9} 125 -414 0 1 0.2 0.2 {}
|
|
B 5 147.5 -392.5 152.5 -387.5 {name=RBL0_9 sig_type=std_logic dir=out }
|
|
L 4 130 -390 150 -390 {}
|
|
T {RBL0_9} 125 -394 0 1 0.2 0.2 {}
|
|
B 5 147.5 -372.5 152.5 -367.5 {name=RBL1_8 sig_type=std_logic dir=out }
|
|
L 4 130 -370 150 -370 {}
|
|
T {RBL1_8} 125 -374 0 1 0.2 0.2 {}
|
|
B 5 147.5 -352.5 152.5 -347.5 {name=RBL0_8 sig_type=std_logic dir=out }
|
|
L 4 130 -350 150 -350 {}
|
|
T {RBL0_8} 125 -354 0 1 0.2 0.2 {}
|
|
B 5 147.5 -332.5 152.5 -327.5 {name=RBL1_7 sig_type=std_logic dir=out }
|
|
L 4 130 -330 150 -330 {}
|
|
T {RBL1_7} 125 -334 0 1 0.2 0.2 {}
|
|
B 5 147.5 -312.5 152.5 -307.5 {name=RBL0_7 sig_type=std_logic dir=out }
|
|
L 4 130 -310 150 -310 {}
|
|
T {RBL0_7} 125 -314 0 1 0.2 0.2 {}
|
|
B 5 147.5 -292.5 152.5 -287.5 {name=RBL1_6 sig_type=std_logic dir=out }
|
|
L 4 130 -290 150 -290 {}
|
|
T {RBL1_6} 125 -294 0 1 0.2 0.2 {}
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|
B 5 147.5 -272.5 152.5 -267.5 {name=RBL0_6 sig_type=std_logic dir=out }
|
|
L 4 130 -270 150 -270 {}
|
|
T {RBL0_6} 125 -274 0 1 0.2 0.2 {}
|
|
B 5 147.5 -252.5 152.5 -247.5 {name=RBL1_5 sig_type=std_logic dir=out }
|
|
L 4 130 -250 150 -250 {}
|
|
T {RBL1_5} 125 -254 0 1 0.2 0.2 {}
|
|
B 5 147.5 -232.5 152.5 -227.5 {name=RBL0_5 sig_type=std_logic dir=out }
|
|
L 4 130 -230 150 -230 {}
|
|
T {RBL0_5} 125 -234 0 1 0.2 0.2 {}
|
|
B 5 147.5 -212.5 152.5 -207.5 {name=RBL1_4 sig_type=std_logic dir=out }
|
|
L 4 130 -210 150 -210 {}
|
|
T {RBL1_4} 125 -214 0 1 0.2 0.2 {}
|
|
B 5 147.5 -192.5 152.5 -187.5 {name=RBL0_4 sig_type=std_logic dir=out }
|
|
L 4 130 -190 150 -190 {}
|
|
T {RBL0_4} 125 -194 0 1 0.2 0.2 {}
|
|
B 5 147.5 -172.5 152.5 -167.5 {name=RBL1_3 sig_type=std_logic dir=out }
|
|
L 4 130 -170 150 -170 {}
|
|
T {RBL1_3} 125 -174 0 1 0.2 0.2 {}
|
|
B 5 147.5 -152.5 152.5 -147.5 {name=RBL0_3 sig_type=std_logic dir=out }
|
|
L 4 130 -150 150 -150 {}
|
|
T {RBL0_3} 125 -154 0 1 0.2 0.2 {}
|
|
B 5 147.5 -132.5 152.5 -127.5 {name=RBL0_2 sig_type=std_logic dir=out }
|
|
L 4 130 -130 150 -130 {}
|
|
T {RBL0_2} 125 -134 0 1 0.2 0.2 {}
|
|
B 5 147.5 -112.5 152.5 -107.5 {name=RBL1_2 sig_type=std_logic dir=out }
|
|
L 4 130 -110 150 -110 {}
|
|
T {RBL1_2} 125 -114 0 1 0.2 0.2 {}
|
|
B 5 147.5 -92.5 152.5 -87.5 {name=RBL1_31 sig_type=std_logic dir=out }
|
|
L 4 130 -90 150 -90 {}
|
|
T {RBL1_31} 125 -94 0 1 0.2 0.2 {}
|
|
B 5 147.5 -72.5 152.5 -67.5 {name=RBL0_1 sig_type=std_logic dir=out }
|
|
L 4 130 -70 150 -70 {}
|
|
T {RBL0_1} 125 -74 0 1 0.2 0.2 {}
|
|
B 5 147.5 -52.5 152.5 -47.5 {name=RBL1_1 sig_type=std_logic dir=out }
|
|
L 4 130 -50 150 -50 {}
|
|
T {RBL1_1} 125 -54 0 1 0.2 0.2 {}
|
|
B 5 147.5 -32.5 152.5 -27.5 {name=RBL0_0 sig_type=std_logic dir=out }
|
|
L 4 130 -30 150 -30 {}
|
|
T {RBL0_0} 125 -34 0 1 0.2 0.2 {}
|
|
B 5 147.5 -12.5 152.5 -7.5 {name=RBL1_0 sig_type=std_logic dir=out }
|
|
L 4 130 -10 150 -10 {}
|
|
T {RBL1_0} 125 -14 0 1 0.2 0.2 {}
|