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153 lines
4.4 KiB
Python
153 lines
4.4 KiB
Python
import unittest
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from nmigen import Elaboratable, Module, Signal
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from nmigen_soc.wishbone import Interface as WishboneInterface
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from nmigen.sim import Simulator
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from lpcperipheral.lpcperipheral import LPCPeripheral
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from .ROM import ROM
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from .helpers import Helpers
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START_IO = 0b0000
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START_FWRD = 0b1101
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START_FWWR = 0b1110
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CYCLE_IOWRITE = 0b0010
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CYCLE_IOREAD = 0b0000
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SYNC_READY = 0b0000
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SYNC_SHORT_WAIT = 0b0101
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SYNC_LONG_WAIT = 0b0110
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LPC_IO_TESTS = 16
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LPC_FW_TESTS = 2
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class LPC_AND_ROM(Elaboratable):
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def __init__(self):
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self.bmc_wb = WishboneInterface(data_width=32, addr_width=14, granularity=8)
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# LPC bus
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self.lclk = Signal()
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self.lframe = Signal()
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self.lad_in = Signal(4)
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self.lad_out = Signal(4)
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self.lad_en = Signal()
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self.lreset = Signal()
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# Interrupts
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self.bmc_vuart_irq = Signal()
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self.bmc_ipmi_irq = Signal()
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self.target_vuart_irq = Signal()
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self.target_ipmi_irq = Signal()
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def elaborate(self, platform):
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m = Module()
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m.submodules.lpc = lpc = LPCPeripheral()
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m.d.comb += [
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# BMC wishbone
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lpc.adr.eq(self.bmc_wb.adr),
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lpc.dat_w.eq(self.bmc_wb.dat_w),
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lpc.sel.eq(self.bmc_wb.sel),
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lpc.cyc.eq(self.bmc_wb.cyc),
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lpc.stb.eq(self.bmc_wb.stb),
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lpc.we.eq(self.bmc_wb.we),
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self.bmc_wb.dat_r.eq(lpc.dat_r),
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self.bmc_wb.ack.eq(lpc.ack),
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# LPC pins
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lpc.lclk.eq(self.lclk),
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lpc.lframe.eq(self.lframe),
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lpc.lad_in.eq(self.lad_in),
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self.lad_out.eq(lpc.lad_out),
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self.lad_en.eq(lpc.lad_en),
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lpc.lreset.eq(self.lreset),
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]
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# Initialize ROM with the offset so we can easily determine if we are
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# reading from the right address
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data = range(128)
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m.submodules.rom = rom = ROM(data=data)
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m.d.comb += [
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# DMA wishbone to ROM
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rom.adr.eq(lpc.dma_adr),
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rom.dat_w.eq(lpc.dma_dat_w),
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rom.sel.eq(lpc.dma_sel),
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rom.cyc.eq(lpc.dma_cyc),
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rom.stb.eq(lpc.dma_stb),
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rom.we.eq(lpc.dma_we),
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lpc.dma_dat_r.eq(rom.dat_r),
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lpc.dma_ack.eq(rom.ack),
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]
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return m
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wb_read_go = 0
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class TestSum(unittest.TestCase, Helpers):
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def setUp(self):
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self.dut = LPC_AND_ROM()
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def test_bench(self):
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def bench():
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global wb_read_go
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while wb_read_go == 0:
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yield
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yield from self.wishbone_read(self.dut.bmc_wb, 0x1014>>2, 0x65)
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yield from self.wishbone_read(self.dut.bmc_wb, 0x1014>>2, 0x48)
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wb_read_go = 0
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while wb_read_go == 0:
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yield
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yield from self.wishbone_read(self.dut.bmc_wb, 0x1010>>2, 0x4)
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def lbench():
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global wb_read_go
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wb_read_go = 0
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yield
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yield self.dut.lreset.eq(1)
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yield self.dut.lframe.eq(1)
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yield
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# Write 2 bytes to LPC IPMI-BT FIFO, read it on BMC wishbone
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yield from self.lpc_io_write(self.dut, 0xe5, 0x65)
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yield from self.lpc_io_write(self.dut, 0xe5, 0x48)
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wb_read_go = 1
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while wb_read_go == 1:
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yield
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# Test writing IPMI BT HOST2BMC attn bit, and reading it from the BMC
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yield from self.lpc_io_write(self.dut, 0xe4, 0x4)
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wb_read_go = 1
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#yield from self.lpc_fw_read(self.dut, 0xFFFFFFF, 1, 4)
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#yield from self.lpc_fw_read(self.dut, 1, 1, 4)
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#yield from self.lpc_fw_read(self.dut, 1, 1, 4)
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#yield from self.lpc_fw_read(self.dut, 1, 1, 4)
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#yield from self.lpc_fw_read(self.dut, 2, 2, 4)
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#yield from self.lpc_fw_read(self.dut, 2, 2, 4)
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#yield from self.lpc_fw_read(self.dut, 2, 2, 4)
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sim = Simulator(self.dut)
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# Make life easy by just running both clocks at same frequency
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sim.add_clock(1e-8)
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sim.add_clock(3e-8, domain="lclk")
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sim.add_clock(3e-8, domain="lclkrst")
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#sim._engine.add_clock_process(self.dut.lclk, phase=None, period=1e-8)
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sim.add_sync_process(lbench, domain="lclk")
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sim.add_sync_process(bench, domain="sync")
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with sim.write_vcd("test_lpc.vcd"):
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sim.run()
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if __name__ == '__main__':
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unittest.main()
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