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53 lines
1.1 KiB
Python
53 lines
1.1 KiB
Python
#!/usr/bin/env python
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# This is a little test program so I could work out how multiple clock
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# domains work. Not really part of this project but a handy refrence
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from nmigen import *
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from enum import Enum, unique
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class clocks(Elaboratable):
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def __init__(self):
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# LPC clock pin
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self.lclk = Signal()
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self.counter = Signal(8)
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self.lcounter = Signal(8)
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def elaborate(self, platform):
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m = Module()
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lclk = ClockDomain("lclk")
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# hook up lclk port to lclk_domain
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m.d.comb += self.lclk.eq(ClockSignal("lclk"))
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m.d.sync += self.counter.eq(self.counter + 1)
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m.d["lclk"] += self.lcounter.eq(self.lcounter + 1)
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return m
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# --- TEST ---
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from nmigen.sim import Simulator
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dut = clocks()
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def bench():
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for _ in range(10):
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yield
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def lbench():
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for _ in range(10):
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yield
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sim = Simulator(dut)
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sim.add_clock(1e-8) # 100 MHz systemclock
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sim.add_clock(3e-8, domain="lclk") # 33 MHz LPC clock
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sim.add_sync_process(bench, domain="sync")
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sim.add_sync_process(lbench, domain="lclk")
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with sim.write_vcd("clocks.vcd"):
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sim.run()
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