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520 lines
23 KiB
VHDL
520 lines
23 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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LIBRARY ieee; USE ieee.std_logic_1164.all;
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LIBRARY support; USE support.power_logic_pkg.all;
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PACKAGE tri_latches_pkg IS
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type clk_logic is record
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clk : std_ulogic;
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sreset : std_ulogic;
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clk2x : std_ulogic;
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clk4x : std_ulogic;
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end record;
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type clk_logic_vector is array ( NATURAL range <> ) of clk_logic;
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component tri_cw_nlat
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generic (
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bhc:string:="";
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ub:string:="";
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offset : natural range 0 to 65535 := 0;
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width : positive range 1 to 65536 := 1 ;
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init : std_ulogic_vector := "0";
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needs_sreset : integer := 1 ; -- for inferred latches
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expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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d_b : in std_ulogic_vector(0 to width-1);
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scan_in : in std_ulogic_vector(0 to width-1);
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d1clk : in std_ulogic;
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d2clk : in std_ulogic;
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lclk : in clk_logic;
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q_b : out std_ulogic_vector(0 to width-1);
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scan_out : out std_ulogic_vector(0 to width-1)
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);
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end component;
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component tri_direct_err_rpt
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generic (
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width : positive := 1 ; -- use to bundle error reporting checkers of the same exact type
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expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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err_in : in std_ulogic_vector(0 to width-1);
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err_out : out std_ulogic_vector(0 to width-1)
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);
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end component;
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component tri_err_rpt
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generic (
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width : positive := 1; -- number of errors of the same type
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mask_reset_value : std_ulogic_vector := "0";-- use to set default/flush value for mask bits
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inline : boolean := false; -- make hold latch be inline; err_out is sticky -- default to shadow
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reset_hold : boolean := false; -- make Hold latch use reset input
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needs_sreset : integer := 1 ; -- for inferred latches
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expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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err_d1clk : in std_ulogic; -- caution: if lcb uses powersavings, errors must always get reported
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err_d2clk : in std_ulogic;
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err_lclk : in clk_logic;
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-- error scan chain (func or mode)
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err_scan_in : in std_ulogic_vector(0 to width-1);
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err_scan_out : out std_ulogic_vector(0 to width-1);
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-- clock gateable mode clocks
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mode_dclk : in std_ulogic;
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mode_lclk : in clk_logic;
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-- mode scan chain
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mode_scan_in : in std_ulogic_vector(0 to width-1);
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mode_scan_out : out std_ulogic_vector(0 to width-1);
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err_in : in std_ulogic_vector(0 to width-1);
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err_out : out std_ulogic_vector(0 to width-1);
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hold_out : out std_ulogic_vector(0 to width-1); -- sticky error hold latch for trap usage
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mask_out : out std_ulogic_vector(0 to width-1)
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);
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end component;
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component tri_klat
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generic (
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width : positive range 1 to 65536 := 1 ;
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offset : natural range 0 to 65535 := 0;
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init : std_ulogic_vector := "0" ;
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synthclonedlatch : string := "" ;
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needs_sreset : integer := 1 ; -- for inferred latches
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expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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dclk : in std_ulogic;
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lclk : in clk_logic;
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din : in std_ulogic_vector(offset to offset+width-1);
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q : out std_ulogic_vector(offset to offset+width-1);
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q_b : out std_ulogic_vector(offset to offset+width-1)
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);
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end component;
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component tri_lcbcntl_array_mac
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generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vdd : inout power_logic;
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gnd : inout power_logic;
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sg : in std_ulogic;
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nclk : in clk_logic;
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scan_in : in std_ulogic;
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scan_diag_dc : in std_ulogic;
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thold : in std_ulogic;
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clkoff_dc_b : out std_ulogic;
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delay_lclkr_dc : out std_ulogic_vector(0 to 4);
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act_dis_dc : out std_ulogic;
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d_mode_dc : out std_ulogic;
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mpw1_dc_b : out std_ulogic_vector(0 to 4);
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mpw2_dc_b : out std_ulogic;
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scan_out : out std_ulogic
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);
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end component;
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component tri_lcbcntl_mac
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generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vdd : inout power_logic;
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gnd : inout power_logic;
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sg : in std_ulogic;
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nclk : in clk_logic;
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scan_in : in std_ulogic;
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scan_diag_dc : in std_ulogic;
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thold : in std_ulogic;
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clkoff_dc_b : out std_ulogic;
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delay_lclkr_dc : out std_ulogic_vector(0 to 4);
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act_dis_dc : out std_ulogic;
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d_mode_dc : out std_ulogic;
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mpw1_dc_b : out std_ulogic_vector(0 to 4);
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mpw2_dc_b : out std_ulogic;
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scan_out : out std_ulogic
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);
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end component;
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component tri_lcbkd
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generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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act : in std_ulogic;
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delay_lclkr : in std_ulogic;
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mpw1_b : in std_ulogic;
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mpw2_b : in std_ulogic;
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nclk : in clk_logic;
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forcee : in std_ulogic;
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thold_b : in std_ulogic;
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dclk : out std_ulogic;
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lclk : out clk_logic
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);
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end component;
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component tri_lcbnd
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generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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act : in std_ulogic;
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delay_lclkr : in std_ulogic;
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mpw1_b : in std_ulogic;
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mpw2_b : in std_ulogic;
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nclk : in clk_logic;
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forcee : in std_ulogic;
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sg : in std_ulogic;
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thold_b : in std_ulogic;
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d1clk : out std_ulogic;
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d2clk : out std_ulogic;
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lclk : out clk_logic
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);
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end component;
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component tri_lcbor
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generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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clkoff_b : in std_ulogic;
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thold : in std_ulogic;
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sg : in std_ulogic;
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act_dis : in std_ulogic;
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forcee : out std_ulogic;
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thold_b : out std_ulogic
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);
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end component;
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component tri_lcbs
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generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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delay_lclkr : in std_ulogic;
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nclk : in clk_logic;
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forcee : in std_ulogic;
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thold_b : in std_ulogic;
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dclk : out std_ulogic;
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lclk : out clk_logic
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);
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end component;
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component tri_nlat
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generic (
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offset : natural range 0 to 65535 := 0;
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reset_inverts_scan : boolean := true;
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width : positive range 1 to 65536 := 1 ;
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init : std_ulogic_vector := "0" ;
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synthclonedlatch : string := "" ;
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needs_sreset : integer := 1 ; -- for inferred latches
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expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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d1clk : in std_ulogic;
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d2clk : in std_ulogic;
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lclk : in clk_logic;
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scan_in : in std_ulogic;
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din : in std_ulogic_vector(offset to offset+width-1);
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q : out std_ulogic_vector(offset to offset+width-1);
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q_b : out std_ulogic_vector(offset to offset+width-1);
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scan_out : out std_ulogic
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);
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end component;
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component tri_nlat_scan
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generic (
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offset : natural range 0 to 65535 := 0;
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width : positive range 1 to 65536 := 1 ;
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init : std_ulogic_vector := "0" ;
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reset_inverts_scan : boolean := true;
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synthclonedlatch : string := "" ;
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needs_sreset : integer := 1 ; -- for inferred latches
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expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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d1clk : in std_ulogic;
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d2clk : in std_ulogic;
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lclk : in clk_logic;
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din : in std_ulogic_vector(offset to offset+width-1);
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scan_in : in std_ulogic_vector(offset to offset+width-1);
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q : out std_ulogic_vector(offset to offset+width-1);
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q_b : out std_ulogic_vector(offset to offset+width-1);
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scan_out : out std_ulogic_vector(offset to offset+width-1)
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);
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end component;
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component tri_plat
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generic (
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width : positive range 1 to 65536 := 1 ;
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offset : natural range 0 to 65535 := 0 ;
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init : integer := 0; -- will be converted to the least signficant 31 bits of init_v
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synthclonedlatch : string := "" ;
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flushlat : boolean := true ;
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expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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nclk : in clk_logic;
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flush : in std_ulogic;
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din : in std_ulogic_vector(offset to offset+width-1);
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q : out std_ulogic_vector(offset to offset+width-1) );
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end component;
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component tri_regk
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generic (
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width : integer := 4;
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offset : integer range 0 to 65535 := 0 ; --starting bit
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init : integer := 0; -- will be converted to the least signficant
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-- 31 bits of init_v
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synthclonedlatch : string := "";
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needs_sreset : integer := 1 ; -- for inferred latches
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expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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nclk : in clk_logic;
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act : in std_ulogic := '1'; -- 1: functional, 0: no clock
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forcee : in std_ulogic := '0'; -- 1: force LCB active
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thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock
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d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode
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delay_lclkr : in std_ulogic := '0'; -- 0: functional
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mpw1_b : in std_ulogic := '1'; -- pulse width control bit
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mpw2_b : in std_ulogic := '1'; -- pulse width control bit
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din : in std_ulogic_vector(offset to offset+width-1); -- data in
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dout : out std_ulogic_vector(offset to offset+width-1) );
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end component;
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component tri_regs
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generic (
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width : integer := 4;
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offset : integer range 0 to 65535 := 0 ; --starting bit
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init : integer := 0; -- will be converted to the least signficant
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-- 31 bits of init_v
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ibuf : boolean := false; --inverted latch IOs, if set to true.
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dualscan : string := ""; -- if "S", marks data ports as scan for Moebius
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needs_sreset : integer := 1 ; -- for inferred latches
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expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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nclk : in clk_logic;
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forcee : in std_ulogic := '0'; -- 1: force LCB active
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thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock
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delay_lclkr : in std_ulogic := '0'; -- 0: functional
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scin : in std_ulogic_vector(offset to offset+width-1); -- scan in
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scout : out std_ulogic_vector(offset to offset+width-1);
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dout : out std_ulogic_vector(offset to offset+width-1) );
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end component;
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component tri_rlmlatch_p
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generic (
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init : integer := 0; -- will be converted to the least signficant
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-- 31 bits of init_v
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ibuf : boolean := false; --inverted latch IOs, if set to true.
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dualscan : string := ""; -- if "S", marks data ports as scan for Moebius
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needs_sreset: integer := 1 ; -- for inferred latches
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expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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nclk : in clk_logic;
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act : in std_ulogic := '1'; -- 1: functional, 0: no clock
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forcee : in std_ulogic := '0'; -- 1: force LCB active
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thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock
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d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode
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sg : in std_ulogic := '0'; -- 0: functional, 1: scan
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delay_lclkr : in std_ulogic := '0'; -- 0: functional
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mpw1_b : in std_ulogic := '1'; -- pulse width control bit
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mpw2_b : in std_ulogic := '1'; -- pulse width control bit
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scin : in std_ulogic := '0'; -- scan in
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din : in std_ulogic; -- data in
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scout : out std_ulogic; -- scan out
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dout : out std_ulogic); -- data out
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end component;
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component tri_rlmreg_p
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generic (
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width : integer := 4;
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offset : integer range 0 to 65535 := 0 ; --starting bit
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init : integer := 0; -- will be converted to the least signficant
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-- 31 bits of init_v
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|
ibuf : boolean := false; --inverted latch IOs, if set to true.
|
||
|
dualscan : string := ""; -- if "S", marks data ports as scan for Moebius
|
||
|
needs_sreset: integer := 1 ; -- for inferred latches
|
||
|
expand_type : integer := 1 );-- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
|
||
|
port (
|
||
|
vd : inout power_logic;
|
||
|
gd : inout power_logic;
|
||
|
nclk : in clk_logic;
|
||
|
act : in std_ulogic := '1'; -- 1: functional, 0: no clock
|
||
|
forcee : in std_ulogic := '0'; -- 1: force LCB active
|
||
|
thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock
|
||
|
d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode
|
||
|
sg : in std_ulogic := '0'; -- 0: functional, 1: scan
|
||
|
delay_lclkr : in std_ulogic := '0'; -- 0: functional
|
||
|
mpw1_b : in std_ulogic := '1'; -- pulse width control bit
|
||
|
mpw2_b : in std_ulogic := '1'; -- pulse width control bit
|
||
|
scin : in std_ulogic_vector(offset to offset+width-1); -- scan in
|
||
|
din : in std_ulogic_vector(offset to offset+width-1); -- data in
|
||
|
scout : out std_ulogic_vector(offset to offset+width-1);
|
||
|
dout : out std_ulogic_vector(offset to offset+width-1) );
|
||
|
end component;
|
||
|
|
||
|
component tri_slat
|
||
|
generic (
|
||
|
width : positive range 1 to 65536 := 1;
|
||
|
offset : natural range 0 to 65535 := 0;
|
||
|
init : std_ulogic_vector := "0";
|
||
|
synthclonedlatch : string := "";
|
||
|
reset_inverts_scan : boolean := true;
|
||
|
expand_type : integer := 1); -- 1 - other (FPGA), 2 - MPG
|
||
|
port (
|
||
|
vd : inout power_logic;
|
||
|
gd : inout power_logic;
|
||
|
dclk : in std_ulogic;
|
||
|
lclk : in clk_logic;
|
||
|
scan_in : in std_ulogic;
|
||
|
scan_out : out std_ulogic;
|
||
|
q : out std_ulogic_vector(offset to offset+width-1);
|
||
|
q_b : out std_ulogic_vector(offset to offset+width-1));
|
||
|
end component;
|
||
|
|
||
|
component tri_slat_lbist
|
||
|
generic (
|
||
|
width : positive range 1 to 65536 := 1;
|
||
|
offset : natural range 0 to 65535 := 0;
|
||
|
init : std_ulogic_vector := "0";
|
||
|
synthclonedlatch : string := "";
|
||
|
reset_inverts_scan : boolean := true;
|
||
|
expand_type : integer := 1); -- 1 - other (FPGA), 2 - MPG
|
||
|
port (
|
||
|
vd : inout power_logic;
|
||
|
gd : inout power_logic;
|
||
|
dclk : in std_ulogic;
|
||
|
lclk : in clk_logic;
|
||
|
tc_xx_lbist_ac_mode_dc : in std_ulogic;
|
||
|
scan_in : in std_ulogic;
|
||
|
scan_out : out std_ulogic;
|
||
|
q : out std_ulogic_vector(offset to offset+width-1);
|
||
|
q_b : out std_ulogic_vector(offset to offset+width-1));
|
||
|
end component;
|
||
|
|
||
|
component tri_slat_scan
|
||
|
generic (
|
||
|
width : positive range 1 to 65536 := 1 ;
|
||
|
offset : natural range 0 to 65535 := 0;
|
||
|
init : std_ulogic_vector := "0" ;
|
||
|
synthclonedlatch : string := "" ;
|
||
|
btr : string := "c_slat_scan" ;
|
||
|
reset_inverts_scan : boolean := true;
|
||
|
expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
|
||
|
port (
|
||
|
vd : inout power_logic;
|
||
|
gd : inout power_logic;
|
||
|
dclk : in std_ulogic;
|
||
|
lclk : in clk_logic;
|
||
|
scan_in : in std_ulogic_vector(offset to offset+width-1);
|
||
|
scan_out : out std_ulogic_vector(offset to offset+width-1);
|
||
|
q : out std_ulogic_vector(offset to offset+width-1);
|
||
|
q_b : out std_ulogic_vector(offset to offset+width-1)
|
||
|
);
|
||
|
end component;
|
||
|
|
||
|
component tri_ser_rlmreg_p
|
||
|
generic (
|
||
|
width : positive range 1 to 65536 := 1 ;
|
||
|
offset : natural range 0 to 65535 := 0 ;
|
||
|
init : integer := 0;
|
||
|
ibuf : boolean := false;
|
||
|
dualscan : string := "";
|
||
|
needs_sreset : integer := 1 ;
|
||
|
expand_type : integer := 1 );
|
||
|
port (
|
||
|
vd : inout power_logic;
|
||
|
gd : inout power_logic;
|
||
|
nclk : in clk_logic;
|
||
|
act : in std_ulogic := '1';
|
||
|
forcee : in std_ulogic := '0';
|
||
|
thold_b : in std_ulogic := '1';
|
||
|
d_mode : in std_ulogic := '0';
|
||
|
sg : in std_ulogic := '0';
|
||
|
delay_lclkr : in std_ulogic := '0';
|
||
|
mpw1_b : in std_ulogic := '1';
|
||
|
mpw2_b : in std_ulogic := '1';
|
||
|
scin : in std_ulogic_vector(offset to offset+width-1);
|
||
|
din : in std_ulogic_vector(offset to offset+width-1);
|
||
|
scout : out std_ulogic_vector(offset to offset+width-1);
|
||
|
dout : out std_ulogic_vector(offset to offset+width-1));
|
||
|
end component;
|
||
|
|
||
|
component tri_aoi22_nlats_wlcb
|
||
|
generic (
|
||
|
width : integer := 4;
|
||
|
offset : integer range 0 to 65535 := 0 ; --starting bit
|
||
|
init : integer := 0; -- will be converted to the least signficant
|
||
|
-- 31 bits of init_v
|
||
|
ibuf : boolean := false; --inverted latch IOs, if set to true.
|
||
|
dualscan : string := ""; -- if "S", marks data ports as scan for Moebius
|
||
|
needs_sreset : integer := 1 ; -- for inferred latches
|
||
|
expand_type : integer := 1 ; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
|
||
|
synthclonedlatch : string := "" ;
|
||
|
btr : string := "NLL0001_X2_A12TH" );
|
||
|
port (
|
||
|
vd : inout power_logic;
|
||
|
gd : inout power_logic;
|
||
|
nclk : in clk_logic;
|
||
|
act : in std_ulogic := '1'; -- 1: functional, 0: no clock
|
||
|
forcee : in std_ulogic := '0'; -- 1: force LCB active
|
||
|
thold_b : in std_ulogic := '1'; -- 1: functional, 0: no clock
|
||
|
d_mode : in std_ulogic := '0'; -- 1: disable pulse mode, 0: pulse mode
|
||
|
sg : in std_ulogic := '0'; -- 0: functional, 1: scan
|
||
|
delay_lclkr : in std_ulogic := '0'; -- 0: functional
|
||
|
mpw1_b : in std_ulogic := '1'; -- pulse width control bit
|
||
|
mpw2_b : in std_ulogic := '1'; -- pulse width control bit
|
||
|
scin : in std_ulogic_vector(offset to offset+width-1); -- scan in
|
||
|
scout : out std_ulogic_vector(offset to offset+width-1);
|
||
|
A1 : in std_ulogic_vector(offset to offset+width-1);
|
||
|
A2 : in std_ulogic_vector(offset to offset+width-1);
|
||
|
B1 : in std_ulogic_vector(offset to offset+width-1);
|
||
|
B2 : in std_ulogic_vector(offset to offset+width-1);
|
||
|
QB : out std_ulogic_vector(offset to offset+width-1));
|
||
|
end component;
|
||
|
|
||
|
end tri_latches_pkg;
|
||
|
|
||
|
package body tri_latches_pkg is
|
||
|
|
||
|
end tri_latches_pkg;
|