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63 lines
2.1 KiB
Tcl
63 lines
2.1 KiB
Tcl
3 years ago
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# ip creator
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set project reverserator_4 ;# also top
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set keep 0 ;# keep project
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set xdc "" ;# set to xdc file if exists
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set synth_check 1
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proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} {
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set vhdl_dir [file normalize ./vhdl]
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set output_dir .
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set project_dir ./prj
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create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e
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add_files -norecurse $vhdl_dir
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update_compile_order -fileset sources_1
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set_property top $project [current_fileset]
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set_property target_language VHDL [current_project]
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set_property default_lib work [current_project]
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set_property top $project [get_filesets sim_1]
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set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
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set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
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set_property simulator_language VHDL [current_project]
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if {$xdc != ""} {
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set xdc_dir [file normalize ./xdc]
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read_xdc $xdc_dir/$xdc
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}
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update_compile_order -fileset sources_1
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if {$synth_check} {
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synth_design -rtl -name elab_for_sanity_check
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}
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ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
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ipx::unload_core $output_dir/$project/component.xml
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ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
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update_compile_order -fileset sources_1
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set_property core_revision 2 [ipx::current_core]
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ipx::update_source_project_archive -component [ipx::current_core]
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ipx::create_xgui_files [ipx::current_core]
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ipx::update_checksums [ipx::current_core]
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ipx::save_core [ipx::current_core]
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ipx::move_temp_component_back -component [ipx::current_core]
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if {$keep_project} {
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close_project
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puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
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} else {
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close_project -delete
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exec rm -rf $output_dir/$project_dir
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puts "Project built; only IP files kept."
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}
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}
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create_ip $project $keep $synth_check $xdc
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