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a2i/rel/build/xdc/main_extras.xdc

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connect_debug_port u_ila_0/probe2 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_sp
connect_debug_port u_ila_0/probe3 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]]
connect_debug_port u_ila_0/probe17 [get_nets [list u_ila_0_m00_axi_arready]]
connect_debug_port u_ila_0/probe18 [get_nets [list u_ila_0_m00_axi_arvalid]]
connect_debug_port u_ila_0/probe19 [get_nets [list u_ila_0_m00_axi_awready]]
connect_debug_port u_ila_0/probe20 [get_nets [list u_ila_0_m00_axi_awvalid]]
connect_debug_port u_ila_0/probe29 [get_nets [list u_ila_0_WEA]]
connect_debug_port u_ila_0/probe2 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_sp
connect_debug_port u_ila_0/probe3 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]]
connect_debug_port u_ila_0/probe2 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_sp
connect_debug_port u_ila_0/probe3 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]]
connect_debug_port u_ila_0/probe1 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_sp
connect_debug_port u_ila_0/probe2 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_reset_0/reset]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[13]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[17]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[3]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[25]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[23]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[21]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[19]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[15]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[1]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[5]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[8]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[9]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[41]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[39]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[37]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[35]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[33]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[31]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[29]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[47]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[45]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[43]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[59]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[61]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[63]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[27]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[49]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[51]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[53]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[55]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[57]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[11]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[12]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[24]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[22]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[20]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[18]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[16]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[14]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[2]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[4]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[6]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[7]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[10]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[40]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[38]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[36]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[34]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[32]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[30]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[28]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[26]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[54]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[56]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[50]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[52]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[48]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[46]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[44]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[42]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[62]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[58]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/cpl_spr_ex5_nia[60]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[31]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[3]}]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_bready]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_wlast]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[9]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[11]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[15]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[19]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[23]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[27]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[2]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[10]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[6]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[14]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[18]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[26]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[22]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[30]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[9]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[1]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[3]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[15]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[11]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[23]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[19]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[31]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[27]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[1]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[8]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[17]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[25]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[29]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[21]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[13]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[5]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[24]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[16]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[4]}]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_awready]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_wready]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_rlast]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[7]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[12]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[20]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[28]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[3]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[11]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[9]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[19]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[15]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[27]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[23]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[31]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[4]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[7]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[16]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[12]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[24]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[20]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[28]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[2]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[10]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[18]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[26]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[30]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[22]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[14]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[6]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[4]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[17]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[13]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[1]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[5]}]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_arready]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_rready]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_wvalid]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_bvalid]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[8]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[21]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[29]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[25]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[12]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[7]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[20]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[16]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[28]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[24]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[1]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[8]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[5]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[17]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[13]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[25]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[21]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[29]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[3]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[11]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[19]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[27]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[31]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[23]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[15]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[9]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[26]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[18]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[2]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[6]}]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_rvalid]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_arvalid]
set_property MARK_DEBUG true [get_nets a2x_axi_bd_i/a2x_axi_1/m00_axi_awvalid]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[14]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[10]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[22]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[30]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[5]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[1]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[13]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[8]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[21]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[17]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[29]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[25]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[2]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[10]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[6]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[18]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[14]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[26]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[22]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[30]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[4]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[12]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[20]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[28]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[24]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[16]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[7]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[1]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[2]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[3]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[4]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[5]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[6]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[7]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[8]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[9]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[10]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[11]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[12]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[13]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[14]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[15]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[16]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[17]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[18]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[19]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[20]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[21]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[22]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[23]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[24]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[25]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[26]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[27]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[28]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[29]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[30]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/xu_spr/xu_spr_cspr/tbl_latch/dout[31]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[19]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[3]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[26]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[27]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[24]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[25]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[22]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[23]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[20]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[21]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[18]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[16]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[17]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[14]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[15]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[12]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[30]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[31]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[28]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[29]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[13]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[1]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[2]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[4]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[5]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[6]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[7]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[8]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[9]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[10]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[11]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[19]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[3]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[26]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[27]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[24]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[25]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[22]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[23]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[20]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[21]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[18]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[16]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[17]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[14]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[15]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[12]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[30]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[31]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[28]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[29]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[13]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[1]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[2]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[4]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[5]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[6]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[7]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[8]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[9]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[10]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[11]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[21]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[18]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[19]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[20]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[22]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[23]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[24]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[25]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[26]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[27]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[28]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[29]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[30]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[31]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_trig[0]}]
set_property MARK_DEBUG true [get_nets {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_ack[0]}]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list clk]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 248 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {u_ila_0_cpl_spr_ex5_nia[247]} {u_ila_0_cpl_spr_ex5_nia[246]} {u_ila_0_cpl_spr_ex5_nia[245]} {u_ila_0_cpl_spr_ex5_nia[244]} {u_ila_0_cpl_spr_ex5_nia[243]} {u_ila_0_cpl_spr_ex5_nia[242]} {u_ila_0_cpl_spr_ex5_nia[241]} {u_ila_0_cpl_spr_ex5_nia[240]} {u_ila_0_cpl_spr_ex5_nia[239]} {u_ila_0_cpl_spr_ex5_nia[238]} {u_ila_0_cpl_spr_ex5_nia[237]} {u_ila_0_cpl_spr_ex5_nia[236]} {u_ila_0_cpl_spr_ex5_nia[235]} {u_ila_0_cpl_spr_ex5_nia[234]} {u_ila_0_cpl_spr_ex5_nia[233]} {u_ila_0_cpl_spr_ex5_nia[232]} {u_ila_0_cpl_spr_ex5_nia[231]} {u_ila_0_cpl_spr_ex5_nia[230]} {u_ila_0_cpl_spr_ex5_nia[229]} {u_ila_0_cpl_spr_ex5_nia[228]} {u_ila_0_cpl_spr_ex5_nia[227]} {u_ila_0_cpl_spr_ex5_nia[226]} {u_ila_0_cpl_spr_ex5_nia[225]} {u_ila_0_cpl_spr_ex5_nia[224]} {u_ila_0_cpl_spr_ex5_nia[223]} {u_ila_0_cpl_spr_ex5_nia[222]} {u_ila_0_cpl_spr_ex5_nia[221]} {u_ila_0_cpl_spr_ex5_nia[220]} {u_ila_0_cpl_spr_ex5_nia[219]} {u_ila_0_cpl_spr_ex5_nia[218]} {u_ila_0_cpl_spr_ex5_nia[217]} {u_ila_0_cpl_spr_ex5_nia[216]} {u_ila_0_cpl_spr_ex5_nia[215]} {u_ila_0_cpl_spr_ex5_nia[214]} {u_ila_0_cpl_spr_ex5_nia[213]} {u_ila_0_cpl_spr_ex5_nia[212]} {u_ila_0_cpl_spr_ex5_nia[211]} {u_ila_0_cpl_spr_ex5_nia[210]} {u_ila_0_cpl_spr_ex5_nia[209]} {u_ila_0_cpl_spr_ex5_nia[208]} {u_ila_0_cpl_spr_ex5_nia[207]} {u_ila_0_cpl_spr_ex5_nia[206]} {u_ila_0_cpl_spr_ex5_nia[205]} {u_ila_0_cpl_spr_ex5_nia[204]} {u_ila_0_cpl_spr_ex5_nia[203]} {u_ila_0_cpl_spr_ex5_nia[202]} {u_ila_0_cpl_spr_ex5_nia[201]} {u_ila_0_cpl_spr_ex5_nia[200]} {u_ila_0_cpl_spr_ex5_nia[199]} {u_ila_0_cpl_spr_ex5_nia[198]} {u_ila_0_cpl_spr_ex5_nia[197]} {u_ila_0_cpl_spr_ex5_nia[196]} {u_ila_0_cpl_spr_ex5_nia[195]} {u_ila_0_cpl_spr_ex5_nia[194]} {u_ila_0_cpl_spr_ex5_nia[193]} {u_ila_0_cpl_spr_ex5_nia[192]} {u_ila_0_cpl_spr_ex5_nia[191]} {u_ila_0_cpl_spr_ex5_nia[190]} {u_ila_0_cpl_spr_ex5_nia[189]} {u_ila_0_cpl_spr_ex5_nia[188]} {u_ila_0_cpl_spr_ex5_nia[187]} {u_ila_0_cpl_spr_ex5_nia[186]} {u_ila_0_cpl_spr_ex5_nia[185]} {u_ila_0_cpl_spr_ex5_nia[184]} {u_ila_0_cpl_spr_ex5_nia[183]} {u_ila_0_cpl_spr_ex5_nia[182]} {u_ila_0_cpl_spr_ex5_nia[181]} {u_ila_0_cpl_spr_ex5_nia[180]} {u_ila_0_cpl_spr_ex5_nia[179]} {u_ila_0_cpl_spr_ex5_nia[178]} {u_ila_0_cpl_spr_ex5_nia[177]} {u_ila_0_cpl_spr_ex5_nia[176]} {u_ila_0_cpl_spr_ex5_nia[175]} {u_ila_0_cpl_spr_ex5_nia[174]} {u_ila_0_cpl_spr_ex5_nia[173]} {u_ila_0_cpl_spr_ex5_nia[172]} {u_ila_0_cpl_spr_ex5_nia[171]} {u_ila_0_cpl_spr_ex5_nia[170]} {u_ila_0_cpl_spr_ex5_nia[169]} {u_ila_0_cpl_spr_ex5_nia[168]} {u_ila_0_cpl_spr_ex5_nia[167]} {u_ila_0_cpl_spr_ex5_nia[166]} {u_ila_0_cpl_spr_ex5_nia[165]} {u_ila_0_cpl_spr_ex5_nia[164]} {u_ila_0_cpl_spr_ex5_nia[163]} {u_ila_0_cpl_spr_ex5_nia[162]} {u_ila_0_cpl_spr_ex5_nia[161]} {u_ila_0_cpl_spr_ex5_nia[160]} {u_ila_0_cpl_spr_ex5_nia[159]} {u_ila_0_cpl_spr_ex5_nia[158]} {u_ila_0_cpl_spr_ex5_nia[157]} {u_ila_0_cpl_spr_ex5_nia[156]} {u_ila_0_cpl_spr_ex5_nia[155]} {u_ila_0_cpl_spr_ex5_nia[154]} {u_ila_0_cpl_spr_ex5_nia[153]} {u_ila_0_cpl_spr_ex5_nia[152]} {u_ila_0_cpl_spr_ex5_nia[151]} {u_ila_0_cpl_spr_ex5_nia[150]} {u_ila_0_cpl_spr_ex5_nia[149]} {u_ila_0_cpl_spr_ex5_nia[148]} {u_ila_0_cpl_spr_ex5_nia[147]} {u_ila_0_cpl_spr_ex5_nia[146]} {u_ila_0_cpl_spr_ex5_nia[145]} {u_ila_0_cpl_spr_ex5_nia[144]} {u_ila_0_cpl_spr_ex5_nia[143]} {u_ila_0_cpl_spr_ex5_nia[142]} {u_ila_0_cpl_spr_ex5_nia[141]} {u_ila_0_cpl_spr_ex5_nia[140]} {u_ila_0_cpl_spr_ex5_nia[139]} {u_ila_0_cpl_spr_ex5_nia[138]} {u_ila_0_cpl_spr_ex5_nia[137]} {u_ila_0_cpl_spr_ex5_nia[136]} {u_ila_0_cpl_spr_ex5_nia[135]} {u_ila_0_cpl_spr_ex5_nia[134]} {u_ila_0_cpl_spr_ex5_nia[133]} {u_ila_0_cpl_spr_ex5_nia[132]} {u_ila_0_cpl_spr_ex5_nia[131]} {u_ila_0_cpl_spr_ex5_nia[130]} {u_ila_0_cpl_spr_ex5_nia[129]} {u_ila_0_cpl_spr_ex5_nia[128]} {u_ila_0_cpl_spr_ex5_nia[127]} {u_ila_0_cpl_spr_ex5_nia[126]} {u_ila_0_cpl_spr_ex5_nia[125]} {u_ila_0_cpl_spr_ex5_nia[124]} {u_ila_0_cpl_spr_ex5_nia[123]} {u_ila_0_cpl_spr_ex5_nia[122]} {u_ila_0_cpl_spr_ex5_nia[121]} {u_ila_0_cpl_spr_ex5_nia[120]} {u_ila_0_cpl_spr_ex5_nia[119]} {u_ila_0_cpl_spr_ex5_nia[118]} {u_ila_0_cpl_sp
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {u_ila_0_dout[31]} {u_ila_0_dout[30]} {u_ila_0_dout[29]} {u_ila_0_dout[28]} {u_ila_0_dout[27]} {u_ila_0_dout[26]} {u_ila_0_dout[25]} {u_ila_0_dout[24]} {u_ila_0_dout[23]} {u_ila_0_dout[22]} {u_ila_0_dout[21]} {u_ila_0_dout[20]} {u_ila_0_dout[19]} {u_ila_0_dout[18]} {u_ila_0_dout[17]} {u_ila_0_dout[16]} {u_ila_0_dout[15]} {u_ila_0_dout[14]} {u_ila_0_dout[13]} {u_ila_0_dout[12]} {u_ila_0_dout[11]} {u_ila_0_dout[10]} {u_ila_0_dout[9]} {u_ila_0_dout[8]} {u_ila_0_dout[7]} {u_ila_0_dout[6]} {u_ila_0_dout[5]} {u_ila_0_dout[4]} {u_ila_0_dout[3]} {u_ila_0_dout[2]} {u_ila_0_dout[1]} {u_ila_0_dout[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[0]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[1]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[2]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[3]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[4]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[5]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[6]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[7]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[8]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[9]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[10]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[11]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[12]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[13]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[14]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[15]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[16]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[17]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U1/DIA[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[0]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[1]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[2]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[3]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[4]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[5]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[6]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[7]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[8]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[9]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[10]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[11]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[12]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[13]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[14]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[15]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[16]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[17]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U2/DIA[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[0]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[1]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[2]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[3]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[4]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[5]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[6]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[7]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[8]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[9]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[10]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[11]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[12]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[13]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[14]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[15]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[16]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[17]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[18]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[19]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[20]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[21]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[22]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[23]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[24]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[25]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[26]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[27]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[28]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[29]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[30]} {a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/fxadat/xuq_fxu_a/xuq_fxu_gpr/xu_gpr_a/a.U0/DIA[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 32 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[3]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_araddr[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 28 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_awaddr[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 2 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_bresp[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 32 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[3]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_rdata[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 32 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[0]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[1]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[2]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[3]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[4]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[5]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[6]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[7]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[8]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[9]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[10]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[11]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[12]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[13]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[14]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[15]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[16]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[17]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[18]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[19]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[20]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[21]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[22]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[23]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[24]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[25]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[26]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[27]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[28]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[29]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[30]} {a2x_axi_bd_i/a2x_axi_1/m00_axi_wdata[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_trig[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {a2x_axi_bd_i/ila_axi_protocol/TRIG_OUT_ack[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_1_n_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_2_n_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_3_n_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_4_n_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list a2x_axi_bd_i/a2x_axi_1/U0/acq/a_xuq/ctlspr/ctrl/lsucmd/l2cmdq/latch_store_cmd_count_i_5_n_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_bready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_bvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_rlast]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_rready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_rvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_wlast]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_wready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list a2x_axi_bd_i/a2x_axi_1/m00_axi_wvalid]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]