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273 lines
10 KiB
VHDL
273 lines
10 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri,work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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library clib ;
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entity fuq_mul is
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generic( expand_type : integer := 2 );
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port(
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vdd :inout power_logic;
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gnd :inout power_logic;
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clkoff_b :in std_ulogic;
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act_dis :in std_ulogic;
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flush :in std_ulogic;
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delay_lclkr :in std_ulogic;
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mpw1_b :in std_ulogic;
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mpw2_b :in std_ulogic;
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sg_1 :in std_ulogic;
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thold_1 :in std_ulogic;
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fpu_enable :in std_ulogic;
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nclk :in clk_logic;
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f_mul_si :in std_ulogic;
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f_mul_so :out std_ulogic;
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ex1_act :in std_ulogic;
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f_fmt_ex1_a_frac :in std_ulogic_vector(0 to 52) ;
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f_fmt_ex1_a_frac_17 :in std_ulogic;
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f_fmt_ex1_a_frac_35 :in std_ulogic;
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f_fmt_ex1_c_frac :in std_ulogic_vector(0 to 53) ;
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f_mul_ex2_sum :out std_ulogic_vector(1 to 108);
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f_mul_ex2_car :out std_ulogic_vector(1 to 108)
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);
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end fuq_mul;
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architecture fuq_mul of fuq_mul is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal thold_0_b, thold_0, forcee :std_ulogic;
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signal sg_0 :std_ulogic;
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signal spare_unused :std_ulogic_vector(0 to 3);
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signal act_so , act_si :std_ulogic_vector(0 to 3);
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signal m92_0_so, m92_1_so, m92_2_so :std_ulogic;
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signal pp3_05 :std_ulogic_vector(36 to 108) ;
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signal pp3_04 :std_ulogic_vector(35 to 108) ;
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signal pp3_03 :std_ulogic_vector(18 to 90) ;
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signal pp3_02 :std_ulogic_vector(17 to 90) ;
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signal pp3_01 :std_ulogic_vector(0 to 72) ;
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signal pp3_00 :std_ulogic_vector(0 to 72) ;
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signal hot_one_msb_unused :std_ulogic;
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signal hot_one_74 :std_ulogic;
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signal hot_one_92 :std_ulogic;
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signal xtd_unused :std_ulogic;
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signal pp5_00 :std_ulogic_vector(1 to 108);
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signal pp5_01 :std_ulogic_vector(1 to 108);
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begin
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thold_reg_0: tri_plat generic map (expand_type => expand_type) port map (
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => flush ,
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din(0) => thold_1,
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q(0) => thold_0 );
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sg_reg_0: tri_plat generic map (expand_type => expand_type) port map (
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => flush ,
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din(0) => sg_1 ,
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q(0) => sg_0 );
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lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
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clkoff_b => clkoff_b,
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thold => thold_0,
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sg => sg_0,
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act_dis => act_dis,
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forcee => forcee,
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thold_b => thold_0_b );
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act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type, needs_sreset => 0) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr ,
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mpw1_b => mpw1_b ,
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mpw2_b => mpw2_b ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => fpu_enable,
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thold_b => thold_0_b,
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sg => sg_0,
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scout => act_so,
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scin => act_si,
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din(0) => spare_unused(0),
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din(1) => spare_unused(1),
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din(2) => spare_unused(2),
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din(3) => spare_unused(3),
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dout(0) => spare_unused(0),
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dout(1) => spare_unused(1),
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dout(2) => spare_unused(2) ,
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dout(3) => spare_unused(3) );
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act_si(0 to 3) <= act_so(1 to 3) & m92_2_so;
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f_mul_so <= act_so(0) ;
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m92_2: entity work.fuq_mul_92(fuq_mul_92) generic map(inst=> 2, expand_type => expand_type) port map(
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vdd => vdd ,
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gnd => gnd ,
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nclk => nclk ,
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forcee => forcee,
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lcb_delay_lclkr => delay_lclkr ,
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lcb_mpw1_b => mpw1_b ,
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lcb_mpw2_b => mpw2_b ,
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thold_b => thold_0_b ,
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lcb_sg => sg_0 ,
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si => f_mul_si ,
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so => m92_0_so ,
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ex1_act => ex1_act ,
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c_frac(0 to 53) => f_fmt_ex1_c_frac(0 to 53) ,
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a_frac(17 to 34) => f_fmt_ex1_a_frac(35 to 52) ,
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a_frac(35) => tidn ,
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hot_one_out => hot_one_92 ,
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sum92(2 to 74) => pp3_05(36 to 108) ,
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car92(1 to 74) => pp3_04(35 to 108) );
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m92_1: entity work.fuq_mul_92(fuq_mul_92) generic map(inst=> 1, expand_type => expand_type) port map(
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vdd => vdd ,
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gnd => gnd ,
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nclk => nclk ,
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forcee => forcee,
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lcb_delay_lclkr => delay_lclkr ,
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lcb_mpw1_b => mpw1_b ,
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lcb_mpw2_b => mpw2_b ,
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thold_b => thold_0_b ,
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lcb_sg => sg_0 ,
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si => m92_0_so ,
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so => m92_1_so ,
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ex1_act => ex1_act ,
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c_frac(0 to 53) => f_fmt_ex1_c_frac(0 to 53) ,
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a_frac(17 to 34) => f_fmt_ex1_a_frac(17 to 34) ,
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a_frac(35) => f_fmt_ex1_a_frac_35 ,
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hot_one_out => hot_one_74 ,
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sum92(2 to 74) => pp3_03(18 to 90) ,
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car92(1 to 74) => pp3_02(17 to 90) );
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m92_0: entity work.fuq_mul_92(fuq_mul_92) generic map(inst=> 0, expand_type => expand_type) port map(
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vdd => vdd ,
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gnd => gnd ,
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nclk => nclk ,
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forcee => forcee,
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lcb_delay_lclkr => delay_lclkr ,
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lcb_mpw1_b => mpw1_b ,
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lcb_mpw2_b => mpw2_b ,
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thold_b => thold_0_b ,
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lcb_sg => sg_0 ,
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si => m92_1_so ,
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so => m92_2_so ,
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ex1_act => ex1_act ,
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c_frac(0 to 53) => f_fmt_ex1_c_frac(0 to 53) ,
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a_frac(17) => tidn ,
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a_frac(18 to 34) => f_fmt_ex1_a_frac(0 to 16) ,
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a_frac(35) => f_fmt_ex1_a_frac_17 ,
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hot_one_out => hot_one_msb_unused ,
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sum92(2 to 74) => pp3_01(0 to 72) ,
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car92(1) => xtd_unused ,
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car92(2 to 74) => pp3_00(0 to 72) );
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m62: entity work.fuq_mul_62(fuq_mul_62) port map(
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vdd => vdd,
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gnd => gnd,
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hot_one_92 => hot_one_92 ,
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hot_one_74 => hot_one_74 ,
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pp3_05(36 to 108) => pp3_05(36 to 108) ,
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pp3_04(35 to 108) => pp3_04(35 to 108) ,
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pp3_03(18 to 90) => pp3_03(18 to 90) ,
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pp3_02(17 to 90) => pp3_02(17 to 90) ,
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pp3_01( 0 to 72) => pp3_01( 0 to 72) ,
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pp3_00( 0 to 72) => pp3_00( 0 to 72) ,
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sum62(1 to 108) => pp5_01(1 to 108) ,
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car62(1 to 108) => pp5_00(1 to 108) );
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f_mul_ex2_sum(1 to 108) <= pp5_01(1 to 108);
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f_mul_ex2_car(1 to 108) <= pp5_00(1 to 108);
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end;
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