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41 lines
1.1 KiB
Python
41 lines
1.1 KiB
Python
3 years ago
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import math
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from nmigen import Elaboratable, Module, Memory
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from nmigen_soc.wishbone import Interface
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from nmigen.back import verilog
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class ROM(Elaboratable, Interface):
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def __init__(self, data, data_width=32):
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self.data = data
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self.size = len(data)
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self.data_width = data_width
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# Initialize wishbone interface
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addr_width = math.ceil(math.log2(self.size + 1))
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super().__init__(data_width=data_width, addr_width=addr_width)
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def elaborate(self, platform):
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m = Module()
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data = Memory(width=self.data_width, depth=self.size, init=self.data)
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read_port = data.read_port()
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m.submodules.data = read_port
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m.d.comb += [
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read_port.addr.eq(self.adr),
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self.dat_r.eq(read_port.data),
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]
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# Ack cycle after cyc and stb are asserted
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m.d.sync += self.ack.eq(self.cyc & self.stb)
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return m
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if __name__ == "__main__":
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data = [0x11111111, 0x22222222, 0x33333333, 0x44444444]
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top = ROM(data=data)
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with open("ROM.v", "w") as f:
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f.write(verilog.convert(top))
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