forked from librebmc/lpcperipheral
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64 lines
2.1 KiB
Python
64 lines
2.1 KiB
Python
3 years ago
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import unittest
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from nmigen.sim import Simulator
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from lpcperipheral.io_space import IOSpace
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from lpcperipheral.ipmi_bt import RegEnum, BMCRegEnum
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from .helpers import Helpers
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class TestSum(unittest.TestCase, Helpers):
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def setUp(self):
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self.dut = IOSpace()
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def test_io_space_vuart(self):
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def bench():
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yield
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# Look for TX empty bits
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yield from self.wishbone_read(self.dut.bmc_wb, (0x0 + (5 * 4)) // 4, 0x60)
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# Test 1 byte from BMC to target
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yield from self.wishbone_write(self.dut.bmc_wb, 0x0 // 4, 0x12)
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yield
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yield from self.wishbone_read(self.dut.target_wb, 0x3f8, 0x12)
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# Test 1 byte from target to BMC
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yield from self.wishbone_write(self.dut.target_wb, 0x3f8, 0x13)
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yield
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yield from self.wishbone_read(self.dut.bmc_wb, 0x0 // 4, 0x13)
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# Test 3 bytes from BMC to target
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yield from self.wishbone_write(self.dut.bmc_wb, 0x0 // 4, 0x15)
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yield from self.wishbone_write(self.dut.bmc_wb, 0x0 // 4, 0x16)
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yield from self.wishbone_write(self.dut.bmc_wb, 0x0 // 4, 0x17)
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yield from self.wishbone_read(self.dut.target_wb, 0x3f8, 0x15)
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yield from self.wishbone_read(self.dut.target_wb, 0x3f8, 0x16)
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yield from self.wishbone_read(self.dut.target_wb, 0x3f8, 0x17)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_io_space_vuart.vcd"):
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sim.run()
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def test_io_space_ipmi_bt(self):
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def bench():
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yield
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# Test 1 byte from BMC to target via IPMI BT
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yield from self.wishbone_write(self.dut.bmc_wb, 0x1000//4 + BMCRegEnum.BMC2HOST_HOST2BMC, 0x43)
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yield
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yield from self.wishbone_read(self.dut.target_wb, 0xe4 + RegEnum.BMC2HOST_HOST2BMC, 0x43)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_io_space_ipmi_bt.vcd"):
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sim.run()
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if __name__ == '__main__':
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unittest.main()
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