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63 lines
2.6 KiB
Python
63 lines
2.6 KiB
Python
3 years ago
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import unittest
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from nmigen.sim import Simulator
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from lpcperipheral.vuart import RegEnum
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from lpcperipheral.vuart_joined import VUartJoined
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from .helpers import Helpers
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class TestSum(unittest.TestCase, Helpers):
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def setUp(self):
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self.dut = VUartJoined(depth=2)
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def test_vuart_joined(self):
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def bench():
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yield
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# Try writing one byte and reading it from the other VUart
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yield from self.wishbone_write(self.dut.wb_a, RegEnum.RXTX_DLL, 0x65)
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yield # SyncFIFOBuffered needs one cycle for write -> read ready
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yield from self.wishbone_read(self.dut.wb_b, RegEnum.RXTX_DLL, 0x65)
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# Same test from other VUart
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yield from self.wishbone_write(self.dut.wb_b, RegEnum.RXTX_DLL, 0x79)
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yield # SyncFIFOBuffered needs one cycle for write -> read ready
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yield from self.wishbone_read(self.dut.wb_a, RegEnum.RXTX_DLL, 0x79)
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# Try reading from an empty FIFO
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yield from self.wishbone_read(self.dut.wb_a, RegEnum.RXTX_DLL, 0x0)
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yield from self.wishbone_read(self.dut.wb_b, RegEnum.RXTX_DLL, 0x0)
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# Write 2 bytes and read them
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yield from self.wishbone_write(self.dut.wb_a, RegEnum.RXTX_DLL, 0x45)
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# SyncFIFOBuffered drops w_rdy for 1 cycle on almost (n-1)
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# full, likely because there is a separate 1 entry read
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# buffer. Bug?
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yield
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yield from self.wishbone_write(self.dut.wb_a, RegEnum.RXTX_DLL, 0x32)
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yield from self.wishbone_read(self.dut.wb_b, RegEnum.RXTX_DLL, 0x45)
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yield from self.wishbone_read(self.dut.wb_b, RegEnum.RXTX_DLL, 0x32)
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# Write 3 bytes and read 2 (We configured the FIFO to be 2 deep)
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yield from self.wishbone_write(self.dut.wb_a, RegEnum.RXTX_DLL, 0x11)
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# (n-1) full issue as above
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yield
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yield from self.wishbone_write(self.dut.wb_a, RegEnum.RXTX_DLL, 0x22)
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# (n-1) full issue as above
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yield
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yield from self.wishbone_write(self.dut.wb_a, RegEnum.RXTX_DLL, 0x33)
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yield from self.wishbone_read(self.dut.wb_b, RegEnum.RXTX_DLL, 0x11)
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yield from self.wishbone_read(self.dut.wb_b, RegEnum.RXTX_DLL, 0x22)
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yield from self.wishbone_read(self.dut.wb_b, RegEnum.RXTX_DLL, 0x00)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("vuart_joined.vcd"):
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sim.run()
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if __name__ == '__main__':
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unittest.main()
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