forked from librebmc/lpcperipheral
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94 lines
3.1 KiB
Python
94 lines
3.1 KiB
Python
3 years ago
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import unittest
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from nmigen import Elaboratable, Module
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from nmigen_soc.wishbone import Interface as WishboneInterface
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from nmigen.sim import Simulator
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from lpcperipheral.lpc_ctrl import LPC_Ctrl
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from .ROM import ROM
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from .helpers import Helpers
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class LPC_AND_ROM(Elaboratable):
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def __init__(self):
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self.io_wb = WishboneInterface(data_width=32, addr_width=2, granularity=8)
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self.lpc_wb = WishboneInterface(data_width=32, addr_width=26, granularity=8)
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def elaborate(self, platform):
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m = Module()
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m.submodules.ctrl = ctrl = LPC_Ctrl()
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m.d.comb += [
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self.io_wb.connect(ctrl.io_wb),
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self.lpc_wb.connect(ctrl.lpc_wb),
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]
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# Initialize ROM with the offset so we can easily determine if we are
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# reading from the right address
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data = range(128)
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m.submodules.rom = rom = ROM(data=data)
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m.d.comb += ctrl.dma_wb.connect(rom)
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return m
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class TestSum(unittest.TestCase, Helpers):
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def setUp(self):
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self.dut = LPC_AND_ROM()
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def test_read_write(self):
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def bench():
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# base register, offset 0
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# Note CSRs have an extra cycle before ack, hence delay=2
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yield from self.wishbone_write(self.dut.io_wb, 0, 0x12345678, delay=2)
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yield
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yield from self.wishbone_read(self.dut.io_wb, 0, 0x12345678, delay=2)
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# mask register, offset 2
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yield from self.wishbone_write(self.dut.io_wb, 2, 0xBADC0FFE, delay=2)
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yield
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yield from self.wishbone_read(self.dut.io_wb, 2, 0xBADC0FFE, delay=2)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_lpc_ctrl_read_write.vcd"):
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sim.run()
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def test_base_offset(self):
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def bench():
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yield
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# No offset, don't mask off any bits
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# Note CSRs have an extra cycle before ack, hence delay=2
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yield from self.wishbone_write(self.dut.io_wb, 0, 0x0, delay=2)
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yield from self.wishbone_write(self.dut.io_wb, 0x2, 0xffffffff, delay=2)
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for i in range(64):
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yield from self.wishbone_read(self.dut.lpc_wb, i, i)
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# Apply offset and test. The base/mask registers are in bytes
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# So we have to convert from wishbone addresses (assuming a 32
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# bit wishbone, multiply by 4)
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base = 32 # In wishbone units
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yield from self.wishbone_write(self.dut.io_wb, 0, base * 4, delay=2)
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for i in range(32):
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yield from self.wishbone_read(self.dut.lpc_wb, i, i + base, delay=2)
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# Apply mask and test
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yield from self.wishbone_write(self.dut.io_wb, 0x2, 0xf * 4, delay=2)
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for i in range(32):
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yield from self.wishbone_read(self.dut.lpc_wb, i, ((i % 0x10) + base), delay=2)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_lpc_ctrl_base_offset.vcd"):
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sim.run()
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if __name__ == '__main__':
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unittest.main()
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