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192 lines
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192 lines
15 KiB
XML
<!--
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Copyright (c) 2016 OpenPOWER Foundation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<chapter version="5.0" xml:lang="en" xmlns="http://docbook.org/ns/docbook" xmlns:xi="http://www.w3.org/2001/XInclude"
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xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="chapter_capi20_bsp">
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<!-- Chapter Title goes here. -->
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<title xml:id="chapter_capi20_bsp_title">Enable CAPI2.0 BSP</title>
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<section><title>Structure</title>
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<para>Each card supplier may design their FPGA board with different FPGA chips, circuit components, memory and IOs, so BSP (Board support package) is different from card to card. That's why an open-sourced project is so helpful: It allows card supplier and every developer to explore the functions of the card freely, and get benefits from CAPI technology. </para>
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<figure pgwide="1" xml:id="capi2-bsp">
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<title>Project hierarchy for HDK mode</title>
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<mediaobject>
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<imageobject>
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<imagedata fileref="figures/bsp.png" format="PNG" scalefit="1" width="90%" align="center" />
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</imageobject>
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</mediaobject>
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</figure>
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<para>CAPI2.0 BSP (capi_bsp_wrap) contains following modules:</para>
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<itemizedlist>
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<listitem><para>PSL9 (PSL9_WRAP)</para></listitem>
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<listitem><para>PCIe hard IP core (pcie3/4_ultrascale_plus_0)</para></listitem>
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<listitem><para>Flash Controller (capi_flash_spi_mt25qt)</para></listitem>
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<listitem><para>VSEC: Vendor Specific Extended Capability (capi_vsec)</para></listitem>
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<listitem><para>Xilinx MultiBoot control logic (capi_xilmltbt)</para></listitem>
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<listitem><para>Other miscelleneous logic</para></listitem>
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</itemizedlist>
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<para>In this diagram, psl_fpga.vhdl is the top design. How to connect the ports to FPGA pins is different from card to card, and the information is provided by Card Supplier. They may include:</para>
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<itemizedlist>
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<listitem><para>Flash interface (usually SPIx4 or dual SPIx4)</para></listitem>
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<listitem><para>PCIe interface: perst, refclk, TX and RX data lanes (PCIe Gen3.0x16, or Gen4.0x8)</para></listitem>
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<listitem><para>Peripheral IPs: I2C, LED, DDR, Ethernet, etc. </para></listitem>
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</itemizedlist>
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<para> At least Flash interface pins and PCIe interface pins are required to be assigned in xdc files precisely.</para>
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<para> Between capi_bsp_wrap and user AFU (psl_accel), there are 6 groups of signals: Command, DMA, Buffer, Response, MMIO and Control. Please refer to <link xlink:href="http://openpowerfoundation.org/wp-content/uploads/resources/v2-psl-afu-spec/content/ch_preface.html"> CAPI2.0 PSL/AFU interface Spec</link> for the details. </para>
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</section>
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<section><title>Step-by-step guidance</title>
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<section><title>Work on github</title>
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<para>capi2-bsp is a public Github repository. You need to have a Github account first. Then create a "fork" (Click the "fork" button) on <link xlink:href="https://github.com/open-power/capi2-bsp">https://github.com/open-power/capi2-bsp</link>.</para>
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<screen>git clone https://github.com/[YOUR_USERNAME]/capi2-bsp</screen>
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<note><para>capi2-bsp is also a submodule of snap.</para></note>
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<para>Keep working on your own capi2-bsp fork, when it has been validated to work well, submit a pull request to "open-power/capi2-bsp" and request merging into the public upstream.</para>
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</section>
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<section><title>Preparations</title>
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<para>First, define a FPGACARD name. It can start from the company's name, following with the card name and be short. For example, ADKU3 = Alpha-Data ADM-PCIE-KU3. Get information from the card supplier.</para>
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<!-- A table starts -->
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<table frame="all" pgwide="1" xml:id="supplier-info">
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<title>Information to collect</title>
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<tgroup cols="2">
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<colspec colname="c2" colwidth="15*" />
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<colspec colname="c3" colwidth="35*" />
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<thead>
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<row>
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<entry>
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<para>
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<emphasis role="bold">Item</emphasis>
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</para>
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</entry>
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<entry>
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<para>
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<emphasis role="bold">Description</emphasis>
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</para>
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</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry><para>FPGACARD</para></entry>
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<entry><para>Short card name</para></entry>
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</row>
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<row>
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<entry><para>FPGACHIP</para></entry>
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<entry><para>FPGA part name, for example, xcvu9p-fsgd2104-2L-e</para></entry>
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</row>
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<row>
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<entry><para>Flash Type and IO pins</para></entry>
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<entry><para>Flash chip that attached to FPGA, for example mt28gu01gaax1e-bpi-x16. And the related xdc files for FPGA config.</para></entry>
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</row>
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<row>
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<entry><para>PCIe Config and IO pins</para></entry>
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<entry><para>The tcl/xdc information about the PCIe hardware IP for this card. </para></entry>
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</row>
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<row>
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<entry><para>DDR MC IP</para></entry>
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<entry><para>DDR memory controller Vivado IP tcl/xdc file. </para></entry>
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</row>
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<row>
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<entry><para>Other peripherals</para></entry>
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<entry><para>NVMe IP, Ethernet IP and so on (Optional)</para></entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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<note><para>DDR MC and other peripheral IP's configurations are not needed at the beginning. They are not in the capi_bsp_wrap diagram. However, when you query information from the FPGA Supplier, it's wise to include them also. </para></note>
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</section>
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<section><title>Download PSL Zip package</title>
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<para>Download PSL9 Zip package from <link xlink:href="https://www-355.ibm.com/systems/power/openpower/posting.xhtml?postingId=1BED44BCA884D845852582B70076A89A">OpenPower Portal</link> and put it in "capi2-bsp/psl" directory. </para>
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</section>
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<section><title>Copy and modify</title>
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<para>Choose an existing card as a base. Copy the folder to your new FPGACARD name. Then modify the contents according to the information collected from FPGA supplier.</para>
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<important><para> Make sure the information in xdc/tcl files are permitted to be open-source. </para></important>
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<para>There are some other modifications you should pay attention to:</para>
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<orderedlist>
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<listitem><para><emphasis role="underline">PCIe core IP creation:</emphasis></para>
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<itemizedlist>
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<listitem><para>"Vendor ID" and "Device ID" have to be 0x1014 and 0x0477, so kernel module cxl can recognize the card as a CAPI device. (See in <link xlink:href="https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/tree/drivers/misc/cxl/pci.c">pci.c</link>)</para></listitem>
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<listitem><para>If the card vendor has a code allocated by PCISIG (See in <link xlink:href="https://pcisig.com/membership/member-companies">PCISIG Member companies</link>), use it as "Subsystem Vendor ID". "Subsystem Device ID" can be chosen freely. </para></listitem>
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<listitem><para>If the card vendor doesn't have a code allocated by PCISIG, or just for testing and evaluation purpose, please use default "Subsystem Vendor ID" = 0x1014, and send email to <email>aclwg-chair@openpowerfoundation.org</email> to get a distinct "Subsystem Device ID" to differentiate this card from others.</para>
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<para>Example: (in create_ip.tcl)</para>
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<screen>create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 -dir $ip_dir >> $log_file
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set_property -dict [list \
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CONFIG.PF0_CLASS_CODE {1200ff} \
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CONFIG.PF0_REVISION_ID {02} \
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CONFIG.VENDOR_ID {1014} \
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CONFIG.PF0_DEVICE_ID {0477} \
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CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1014} \
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CONFIG.PF0_SUBSYSTEM_ID {0661} \
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...... \
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...... \
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] [get_ips pcie4_uscale_plus_0] >> $log_file</screen>
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<para>The corresponding "Subsytem Vendor ID" and "Subsystem Device ID" need to be added into <link xlink:href="https://github.com/ibm-capi/capi-utils">capi-utils</link>, file "psl-devices".</para>
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</listitem>
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</itemizedlist>
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</listitem>
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<listitem><para><emphasis role="underline">Product Family support:</emphasis></para>
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<para>If the FPGA chip types are Xilinx VU33P or VU37P who have HBM, this is actually a new FPGA family <userinput>virtexuplushbm</userinput>. For a new FPGA Production family, additional steps need to take:</para>
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<itemizedlist>
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<listitem><para>"capi2-bsp/psl/create_ip.tcl": <userinput>set_property supported_families ...</userinput>, add new family name like "virtexuplushbm Production"</para></listitem>
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<listitem><para>"capi2-bsp/common/tcl/create_capi_bsp.tcl": <userinput>set_property supported_families ...</userinput>, do the same as above.</para></listitem>
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<listitem><para>Add family support to PSL9 ZIP package: unzip the package, do the modifications, and zip them back again. Commands:</para>
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<screen>$ unzip ibm.com_CAPI_PSL9_WRAP_2.00.zip
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(modify compnent.xml to add new family name, search "supportedFamilies")
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$ zip -r ibm.com_CAPI_PSL9_WRAP_2.00.zip component.xml src/ xgui/
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$ rm -fr component.xml src/ xgui/</screen>
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</listitem>
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</itemizedlist>
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</listitem>
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<listitem><para><emphasis role="underline">VSEC starting address: </emphasis></para>
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<para>VSEC (Vendor Specific Extended Capability Structure) is a part of PCIe capability list architecture. It needs to be properly linked in PCIe config space. </para> <para>"capi2-bsp/[FPGACARD]/src/capi_vsec.vhdl": <userinput>vsec_addr[21:32]</userinput> defines the address for VSEC. It should be matched with PCIe core value <userinput>PF0_SECONDARY_PCIE_CAP_NEXTPTR</userinput>. Take card U200 for example, its <userinput>vsec_addr[21:32]</userinput> starts from 12'h400 (12'b0100_0000_0000), and "tcl/patch_ip.tcl" modifies it from default value 12'h480 to 12'h400." </para>
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<screen>exec /bin/bash -c "sed -i \"s/PF0_SECONDARY_PCIE_CAP_NEXTPTR=0x480/PF0_SECONDARY_PCIE_CAP_NEXTPTR=0x400/\" $pcie_source"
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exec /bin/bash -c "sed -i \"s/PF0_SECONDARY_PCIE_CAP_NEXTPTR('H480)/PF0_SECONDARY_PCIE_CAP_NEXTPTR('H400)/\" $pcie_source"</screen>
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<para>Xilinx PCIe code information for extended configuration space can be found on <link xlink:href="https://www.xilinx.com/support/documentation/ip_documentation/pcie3_ultrascale/v4_4/pg156-ultrascale-pcie-gen3.pdf">PG156 (for Ultrascale Device)</link> or <link xlink:href="https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf">PG213 (for Ultrascale+ Device)</link>.</para>
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<para>For Ultrascale+ HBM device's pcie4c core, the VSEC starts from 12'hE80. At this time <userinput>vsec_addr[21:32]</userinput> must be changed in "capi_vsec.vhdl". And the above two lines in "patch_ip.tcl" are not needed anymore.</para>
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</listitem>
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<listitem>
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<para><emphasis role="underline">Vital Product Data: </emphasis><emphasis role="bold">This step is optional.</emphasis></para>
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<para>"capi2-bsp/[FPGACARD]/src/capi_vsec.vhdl": Edit the hardcoded <userinput>vpd44data_be</userinput> to add VPD (Vital Product Data) information. Ideally this information should be read from an I2C EEPROM. The FPGA supplier wrote the content of EEPROM before shipping. Today the simpliest way is taken -- writing some hard coded value. "capi2-bsp/common/script" has a script "gen_vsec.sh" to do this. </para>
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</listitem>
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<listitem>
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<para><emphasis role="underline">User Image Address: </emphasis></para>
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<para>"capi2-bsp/[FPGACARD]/src/capi_xilmltbt.vhdl": Edit the User image starting address <userinput>wbstart_addr</userinput>. </para>
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<screen>wbstart_addr <= "User_image_address" when (cpld_user_bs_req = '1') else "00000000000000000000000000000000";</screen>
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<para>"capi_xilmltbt.vhdl" has a Xilinx multi-boot core. That means you can create two kinds of images: Factory image and User image. Factory images will be placed at address 0 of FPGA Flash, and User image will be placed at "User_image_address" on the flash. When power-on or the FPGA card is reset, the multiboot core knows where to load the image. Usually a Golden factory image is put on address 0 and is never changed. Multiboot core always tries to load user image first. If the user image has something wrong, multiboot logic will tell the FPGA to "fallback" to factory image. You still see the card in the system and you can just program a new user image to try again. </para>
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</listitem>
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<listitem>
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<para><emphasis role="underline">Check Vivado Version:</emphasis></para>
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<para>Make sure this version of Vivado tool supports the FPGA part name you have assigned in "capi2-bsp/[FPGACARD]/Makefile". For some very new FPGA chip types, in one Vivado version they may have a suffix of "es" (engineering sample), and in a newer Vivado version the "es" suffix is removed.</para>
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</listitem>
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</orderedlist>
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</section>
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<section><title>Generate capi_bsp_wrap</title>
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<screen>cd capi2-bsp
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make [FPGACARD]</screen>
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<para>If it is successfully done, the generation of BSP for CAPI2.0 is completed. Developers using HDK mode can create their own Vivado project and import capi_bsp_wrap as an IP. But for SNAP developers there are some other work to do, see in next chapter.</para>
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</section>
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</section>
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</chapter>
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