Preliminary documentation review updates

- Issue #2: Intel and Itanium trademark notices returned to ch_preface.xml.
- Issue #3: "About this Document" section returned to ch_preface.xml.
- Issue #4: Hyperlinks corrected in ch_1.xml.
- Issue #5: Removed "section" tags to promote Introduction to main chapter
  text in ch_1.xml.
- Issue #7: Corrected Table 2.10 borders in ch_2.xml.
- Issue #10: Manually added spacing prior to all bridehead documentation to
  increase visible groupings in ch_2.xml and other sections.
- Issue #11: Corrected bullet nesting in ch_2.xml.

Additional, non-issue updates throughout document:
- Manual review and update of table sizes, spacing
- Updates to program listings to ensure proper spacing.
- Change bars for POWER9 and erratum work added.

Signed-off-by: Jeff Scheel <scheel@us.ibm.com>
pull/92/head
Jeff Scheel 8 years ago
parent 5de854880b
commit c7599451a7

File diff suppressed because it is too large Load Diff

@ -1,6 +1,6 @@
<appendix xmlns="http://docbook.org/ns/docbook"
xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en"
xml:id="dbdoclet.50655245_pgfId-1450875">
xml:id="dbdoclet.50655245_pgfId-1450875" revisionflag="added">
<title>Binary-Coded Decimal Built-In Functions</title>
<para>Binary-coded decimal (BCD) values are compressed; each decimal digit
and sign bit occupies 4 bits. Digits are ordered right-to-left in the order
@ -19,8 +19,8 @@ xml:id="dbdoclet.50655245_pgfId-1450875">
bytes.</para>
<note>
<para>BCD built-in functions are valid only when -
<emphasis>march</emphasis> or -
<emphasis>qarch</emphasis> is set to target POWER8 processors or
<emphasis role="bold">march</emphasis> or -
<emphasis role="bold">qarch</emphasis> is set to target POWER8 processors or
later.</para>
</note>
<para>
@ -411,12 +411,11 @@ xml:id="dbdoclet.50655245_pgfId-1450875">
in
<xref linkend="dbdoclet.50655245_48437" />.</para>
<para>The bcd data type is defined as follows in the bcd.h:</para>
<para><literal>typedef bcd vector unsigned char;</literal></para>
<programlisting>typedef bcd vector unsigned char;</programlisting>
<para>The header file also defines a bcd_default_format as follows:</para>
<para><literal>#ifndef bcd_default_format</literal></para>
<para><literal>#define bcd_default_format __BCD_SIGN_IBM</literal></para>
<para><literal>#endif</literal></para>
<para> </para>
<programlisting>#ifndef bcd_default_format
#define bcd_default_format __BCD_SIGN_IBM
#endif</programlisting>
<table frame="all" pgwide="1" xml:id="dbdoclet.50655245_12427">
<title>BCD Functions Defined by bcd.h</title>
<tgroup cols="2">
@ -810,42 +809,45 @@ xml:id="dbdoclet.50655245_pgfId-1450875">
</section>
<section xml:id="dbdoclet.50655245_52184">
<title>Sample bcd.h Listing</title>
<programlisting>
#ifndef __BCD_H
#define __BCD_H
typedef bcd vector unsigned char;
#define BCD_FORMAT_IBM 0
#define BCD_FORMAT_Z 0
#define BCD_FORMAT_POWER 0
#define BCD_FORMAT_IBMi 1
#define BCD_FORMAT_I 1
#define BCD_FORMAT_NCR 1
#ifndef bcd_default_format
#define bcd_default_format __BCD_SIGN_IBM
#endif
#define bcd_add(a,b) ((bcd)__builtin_bcdadd (a,b,bcd_default_format))
#define bcd_sub(A,b) ((bcd)__builtin_bcdsub (a,b,bcd_default_format))
#define bcd_add_ofl(a,b) ((_Bool)__builtin_bcdadd_ofl (a,b))
#define bcd_add_ofl(a,b) ((_Bool)__builtin_bcdsub_ofl (a,b))
#define bcd_invalid(a) ((_Bool)__builtin_bcd_invalid (a))
#define bcd_cmpeq(a,b) ((_Bool)__builtin_bcdcmpeq (a,b))
#define bcd_cmpge(a,b) ((_Bool)__builtin_bcdcmpge (a,b))
#define bcd_cmpgt(a,b) ((_Bool)__builtin_bcdcmpgt (a,b))
#define bcd_cmple(a,b) ((_Bool)__builtin_bcdcmple (a,b))
#define bcd_cmplt(a,b) ((_Bool)__builtin_bcdcmplt (a,b))
#define bcd_cmpne(a,b) (!(_Bool)__builtin_bcdcmpeq (a,b))
#define bcd_xl(a,b) ((bcd)vec_xl_len_r(a,b))
#define bcd_xst(a,b) ((bcd)vec_xst_len_r(a,b))
#define bcd_quantize(d) (__builtin_bcdquantize(d))
#define bcd_dfp(a) (__builtin_bcd2dfp (a))
#define bcd_dfp2bcd(DFP) ((bcd)__builtin_vec_DFP2BCD (_Decimal128 dfp))
#define bcd_string2bcd(string) ((bcd) __bcd_string2bcd (string, bcd_default_format)
#define bcd_mul10(a) ((bcd) __builtin_bcdmul10 (a))
#define bcd_div10(a) ((bcd) __builtin_bcddiv10 (a))
#define bcd_mul(a,b) ((bcd) __bcd_mul (a,b,bcd_default_format))
#define bcd_div(a,b) ((bcd) __bcd_div (a,b,bcd_default_format))
#endif /* __BCD_H */
</programlisting>
<programlisting>#ifndef __BCD_H
#define __BCD_H

typedef bcd vector unsigned char;

#define BCD_FORMAT_IBM 0
#define BCD_FORMAT_Z 0
#define BCD_FORMAT_POWER 0
#define BCD_FORMAT_IBMi 1
#define BCD_FORMAT_I 1
#define BCD_FORMAT_NCR 1

#ifndef bcd_default_format
#define bcd_default_format __BCD_SIGN_IBM
#endif

#define bcd_add(a,b) ((bcd)__builtin_bcdadd (a,b,bcd_default_format))
#define bcd_sub(A,b) ((bcd)__builtin_bcdsub (a,b,bcd_default_format))
#define bcd_add_ofl(a,b) ((_Bool)__builtin_bcdadd_ofl (a,b))
#define bcd_add_ofl(a,b) ((_Bool)__builtin_bcdsub_ofl (a,b))
#define bcd_invalid(a) ((_Bool)__builtin_bcd_invalid (a))
#define bcd_cmpeq(a,b) ((_Bool)__builtin_bcdcmpeq (a,b))
#define bcd_cmpge(a,b) ((_Bool)__builtin_bcdcmpge (a,b))
#define bcd_cmpgt(a,b) ((_Bool)__builtin_bcdcmpgt (a,b))
#define bcd_cmple(a,b) ((_Bool)__builtin_bcdcmple (a,b))
#define bcd_cmplt(a,b) ((_Bool)__builtin_bcdcmplt (a,b))
#define bcd_cmpne(a,b) (!(_Bool)__builtin_bcdcmpeq (a,b))
#define bcd_xl(a,b) ((bcd)vec_xl_len_r(a,b))
#define bcd_xst(a,b) ((bcd)vec_xst_len_r(a,b))
#define bcd_quantize(d) (__builtin_bcdquantize(d))
#define bcd_dfp(a) (__builtin_bcd2dfp (a))
#define bcd_dfp2bcd(DFP) ((bcd)__builtin_vec_DFP2BCD (_Decimal128 dfp))
#define bcd_string2bcd(string) ((bcd) __bcd_string2bcd (string, bcd_default_format)
#define bcd_mul10(a) ((bcd) __builtin_bcdmul10 (a))
#define bcd_div10(a) ((bcd) __builtin_bcddiv10 (a))
#define bcd_mul(a,b) ((bcd) __bcd_mul (a,b,bcd_default_format))
#define bcd_div(a,b) ((bcd) __bcd_div (a,b,bcd_default_format))

#endif /* __BCD_H */</programlisting>
</section>
</section>
</appendix>

@ -16,7 +16,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Application binary interface</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>AES</para>
</entry>
@ -24,7 +24,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Advanced Encryption Standard</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>API</para>
</entry>
@ -32,7 +32,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Application programming interface</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>ASCII</para>
</entry>
@ -40,7 +40,7 @@ xml:id="dbdoclet.50655246_33489">
<para>American Standard Code for Information Interchange</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>BCD</para>
</entry>
@ -56,7 +56,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Big-endian</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>COBOL</para>
</entry>
@ -72,7 +72,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Condition Register</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>CTR</para>
</entry>
@ -80,7 +80,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Count Register</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>DFP</para>
</entry>
@ -96,7 +96,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Double precision</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>DRN</para>
</entry>
@ -105,7 +105,7 @@ xml:id="dbdoclet.50655246_33489">
register.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>DSCR</para>
</entry>
@ -137,7 +137,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Debug with arbitrary record format</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>EA</para>
</entry>
@ -153,7 +153,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Executable and Linking Format</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>EOS</para>
</entry>
@ -177,7 +177,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Floating-Point Status and Control Register</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>GCC</para>
</entry>
@ -185,7 +185,7 @@ xml:id="dbdoclet.50655246_33489">
<para>GNU Compiler Collection</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>GEP</para>
</entry>
@ -209,7 +209,7 @@ xml:id="dbdoclet.50655246_33489">
<para>General Purpose Register</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>HTM</para>
</entry>
@ -281,7 +281,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Little-endian</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>LEP</para>
</entry>
@ -305,7 +305,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Least-significant byte</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>MB</para>
</entry>
@ -313,7 +313,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Megabyte</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>MSB</para>
</entry>
@ -321,7 +321,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Most-significant byte</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>MSR</para>
</entry>
@ -329,7 +329,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Machine State Register</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>N/A</para>
</entry>
@ -345,7 +345,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Not-a-Number</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>NOP</para>
</entry>
@ -354,7 +354,7 @@ xml:id="dbdoclet.50655246_33489">
affect registers or generate bus activity.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>NOR</para>
</entry>
@ -362,7 +362,7 @@ xml:id="dbdoclet.50655246_33489">
<para>In Boolean logic, the negation of a logical OR.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>OE</para>
</entry>
@ -387,7 +387,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Position-independent executable</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>PIM</para>
</entry>
@ -411,7 +411,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Performance Monitor Registers</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>POSIX</para>
</entry>
@ -419,7 +419,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Portable Operating System Interface</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>PS</para>
</entry>
@ -427,7 +427,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Positive sign</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>RN</para>
</entry>
@ -436,7 +436,7 @@ xml:id="dbdoclet.50655246_33489">
FPSCR register.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>RPG</para>
</entry>
@ -444,7 +444,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Report Program Generator</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>SHA</para>
</entry>
@ -476,7 +476,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Special Purpose Register</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>SVID</para>
</entry>
@ -516,7 +516,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Thread pointer</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>UE</para>
</entry>
@ -533,7 +533,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Unit of least precision</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>VDSO</para>
</entry>
@ -541,7 +541,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Virtual dynamic shared object</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>VE</para>
</entry>
@ -574,7 +574,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Vector scalar extension</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>XE</para>
</entry>
@ -583,7 +583,7 @@ xml:id="dbdoclet.50655246_33489">
FPSCR register.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>XER</para>
</entry>
@ -591,7 +591,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Fixed-Point Exception Register</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>XNOR</para>
</entry>
@ -599,7 +599,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Exclusive NOR</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>XOR</para>
</entry>
@ -607,7 +607,7 @@ xml:id="dbdoclet.50655246_33489">
<para>Exclusive OR</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>ZE</para>
</entry>

@ -50,8 +50,8 @@
<pubdate/>

<!-- TODO: Change license to "gnuFreeDoc" when JAR 1.5 becomes available. -->
<!--legalnotice role="gnuFreeDoc"-->
<legalnotice role="apache2">
<legalnotice role="gnuFreeDoc">
<!--legalnotice role="apache2"-->

<annotation>
<remark>Copyright details are filled in by the template.</remark>
@ -86,7 +86,38 @@
<revdescription>
<itemizedlist spacing="compact">
<listitem>
<para>Revision 1.1b - initial conversion from framemaker</para>
<para>Revision 1.2b - initial conversion from framemaker</para>
</listitem>
</itemizedlist>
</revdescription>
</revision>
<revision>
<date revisionflag="added">2016-06-13</date>
<revdescription>
<itemizedlist revisionflag="added" spacing="compact">
<listitem>
<para>Version 1.2 - POWER8 erratum and POWER9 support.
</para>
</listitem>
</itemizedlist>
</revdescription>
</revision>
<revision>
<date>2015-07-16</date>
<revdescription>
<itemizedlist spacing="compact">
<listitem>
<para>Version 1.1 - initial conversion from framemaker</para>
</listitem>
</itemizedlist>
</revdescription>
</revision>
<revision>
<date>2014-07-21</date>
<revdescription>
<itemizedlist spacing="compact">
<listitem>
<para>Version 1.0 initial release.</para>
</listitem>
</itemizedlist>
</revdescription>

@ -1,52 +1,49 @@
<chapter xmlns="http://docbook.org/ns/docbook"
xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
xmlns:xi="http://www.w3.org/2001/XInclude"
xmlns:xl="http://www.w3.org/1999/xlink"
version="5.0" xml:lang="en"
xml:id="ch_1">
<title>Introduction</title>
<section xml:id="dbdoclet.50655239_pgfId-1101854">
<title>Introduction</title>
<para>The Executable and Linking Format (ELF) defines a linking interface
for executables and shared objects in two parts.</para>
<itemizedlist>
<listitem>
<para>The first part is the generic System V ABI (
<emphasis>
<link xl:href="http://refspecs.linuxfoundation.org/LSB_4.1.0/LSB-Core-generic/LSB-Core-generic/normativerefs.html#NORMATIVEREFSSECT">
<para>The Executable and Linking Format (ELF) defines a linking interface
for executables and shared objects in two parts.</para>
<itemizedlist>
<listitem>
<para>The first part is the generic System V ABI
(<link xl:href="http://refspecs.linuxfoundation.org/LSB_4.1.0/LSB-Core-generic/LSB-Core-generic/normativerefs.html#NORMATIVEREFSSECT">http://refspecs.linuxfoundation.org/LSB_4.1.0/LSB-Core-generic/LSB-Core-generic/normativerefs.html#NORMATIVEREFSSECT</link>).
</para>
</listitem>
<listitem>
<para>The second part is a processor-specific supplement.</para>
</listitem>
</itemizedlist>
<para>This document, the OpenPOWER ABI for Linux Supplement for the Power
Architecture 64-bit ELF V2 ABI, is the OpenPOWER-compliant
processor-specific supplement for use with ELF V2 on 64-bit IBM Power
Architecture® systems. This is not a complete System V ABI supplement
because it does not define any library interfaces.</para>
<para>This document establishes both big-endian and little-endian
application binary interfaces (see
<xref linkend="dbdoclet.50655240___RefHeading___Toc377640574" />).
OpenPOWER-compliant processors in the 64-bit Power Architecture can execute
in either big-endian or little-endian mode. Executables and
executable-generated data (in general) that subscribes to either byte
ordering is not portable to a system running in the other mode.</para>
<itemizedlist>
<listitem>
<para>Note:
<link xl:href="http://www.power.org/">This ABI specification does not
address little-endian byte ordering before Power ISA 2.03.</link>
</para>
</listitem>
</itemizedlist>
<para>The OpenPOWER ELF V2 ABI is not the same as either the Power
Architecture 32-bit ABI supplement or the 64-bit IBM PowerPC® ELF ABI (ELF
V1).</para>
<para>The Power Architecture 64-bit OpenPOWER ELF V2 ABI supplement is
intended to use the same structural layout now followed in practice by
other processor-specific ABIs.</para>

<citetitle>
http://refspecs.linuxfoundation.org/LSB_4.1.0/LSB-Core-generic/LSB-Core-generic/normativerefs.html#NORMATIVEREFSSECT</citetitle>
</link>
</emphasis>).</para>
</listitem>
<listitem>
<para>The second part is a processor-specific supplement.</para>
</listitem>
</itemizedlist>
<para>This document, the OpenPOWER ABI for Linux Supplement for the Power
Architecture 64-bit ELF V2 ABI, is the OpenPOWER-compliant
processor-specific supplement for use with ELF V2 on 64-bit IBM Power
Architecture® systems. This is not a complete System V ABI supplement
because it does not define any library interfaces.</para>
<para>This document establishes both big-endian and little-endian
application binary interfaces (see
<xref linkend="dbdoclet.50655240___RefHeading___Toc377640574" />).
OpenPOWER-compliant processors in the 64-bit Power Architecture can execute
in either big-endian or little-endian mode. Executables and
executable-generated data (in general) that subscribes to either byte
ordering is not portable to a system running in the other mode.</para>
<itemizedlist>
<listitem>
<para>Note:
<link xl:href="http://www.power.org/">
<citetitle>http://www.power.org/</citetitle>
</link></para>
</listitem>
</itemizedlist>
<para>The OpenPOWER ELF V2 ABI is not the same as either the Power
Architecture 32-bit ABI supplement or the 64-bit IBM PowerPC® ELF ABI (ELF
V1).</para>
<para>The Power Architecture 64-bit OpenPOWER ELF V2 ABI supplement is
intended to use the same structural layout now followed in practice by
other processor-specific ABIs.</para>
</section>
<section xml:id="dbdoclet.50655239___RefHeading___Toc377640569">
<title>Reference Documentation</title>
<para>The archetypal ELF ABI is described by the System V ABI.
@ -60,8 +57,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<emphasis>Power Instruction Set Architecture,</emphasis> Version 3.0,
IBM, 2016.
<emphasis>
<link xl:href="http://www.power.org">
<citetitle>http://www.power.org</citetitle>
<link xl:href="http://www.power.org">http://www.power.org
</link>
</emphasis></para>
</listitem>
@ -70,19 +66,14 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<emphasis>DWARF Debugging Information Format,</emphasis> Version 4,
DWARF Debugging Information Format Workgroup, 2010.
<emphasis>
<link xl:href="http://dwarfstd.org/Dwarf4Std.php">
<citetitle>http://dwarfstd.org/Dwarf4Std.php</citetitle>
</link>
<link xl:href="http://dwarfstd.org/Dwarf4Std.php">http://dwarfstd.org/Dwarf4Std.php</link>
</emphasis></para>
</listitem>
<listitem>
<para>
<emphasis>ISO/IEC 9899:2011: Programming languages—C</emphasis>.
<emphasis>
<link xl:href="http://www.iso.org/iso/home/store/catalogue_tc/catalogue_detail.htm?csnumber=57853">

<citetitle>
http://www.iso.org/iso/home/store/catalogue_tc/catalogue_detail.htm?csnumber=57853</citetitle>
<link xl:href="http://www.iso.org/iso/home/store/catalogue_tc/catalogue_detail.htm?csnumber=57853">http://www.iso.org/iso/home/store/catalogue_tc/catalogue_detail.htm?csnumber=57853
</link>
</emphasis></para>
</listitem>
@ -90,10 +81,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<para>Itanium C++ ABI: Exception Handling. Rev 1.22, CodeSourcery,
2001.
<emphasis>
<link xl:href="http://www.codesourcery.com/public/cxx-abi/abi-eh.html">

<citetitle>
http://www.codesourcery.com/public/cxx-abi/abi-eh.html</citetitle>
<link xl:href="http://www.codesourcery.com/public/cxx-abi/abi-eh.html">http://www.codesourcery.com/public/cxx-abi/abi-eh.html
</link>
</emphasis></para>
</listitem>
@ -104,10 +92,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
programming language C to support decimal floating-point
arithmetic</emphasis>, ISO/IEC, January 05, 2009. Available from ISO.
<emphasis>
<link xl:href="http://www.iso.org/iso/home/store/catalogue_tc/catalogue_tc_browse.htm?commid=45202">

<citetitle>
http://www.iso.org/iso/home/store/catalogue_tc/catalogue_tc_browse.htm?commid=45202</citetitle>
<link xl:href="http://www.iso.org/iso/home/store/catalogue_tc/catalogue_tc_browse.htm?commid=45202">http://www.iso.org/iso/home/store/catalogue_tc/catalogue_tc_browse.htm?commid=45202
</link>
</emphasis></para>
</listitem>
@ -116,8 +101,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<emphasis>ELF Handling for Thread-Local Storage</emphasis>, Version
0.20, Ulrich Drepper, Red Hat Inc., December 21, 2005.
<emphasis>
<link xl:href="http://people.redhat.com/drepper/tls.pdf">
<citetitle>http://people.redhat.com/drepper/tls.pdf</citetitle>
<link xl:href="http://people.redhat.com/drepper/tls.pdf">http://people.redhat.com/drepper/tls.pdf
</link>
</emphasis></para>
</listitem>
@ -130,10 +114,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<emphasis>64-bit PowerPC ELF Application Binary Interface Supplement
1.9.</emphasis>
<emphasis>
<link xl:href="http://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html">

<citetitle>
http://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html</citetitle>
<link xl:href="http://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html">http://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html
</link>
</emphasis>
</para>
@ -169,10 +150,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<emphasis>ALTIVEC PIM: AltiVec™ Technology Programming Interface
Manual</emphasis>, Freescale Semiconductor, 1999.
<emphasis>
<link xl:href="http://www.freescale.com/files/32bit/doc/ref_manual/ALTIVECPIM.pdf">

<citetitle>
http://www.freescale.com/files/32bit/doc/ref_manual/ALTIVECPIM.pdf</citetitle>
<link xl:href="http://www.freescale.com/files/32bit/doc/ref_manual/ALTIVECPIM.pdf">http://www.freescale.com/files/32bit/doc/ref_manual/ALTIVECPIM.pdf
</link>
</emphasis></para>
</listitem>

File diff suppressed because it is too large Load Diff

@ -10,11 +10,9 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
ELF header identification array, e_ident[EI_DATA], holds the value 2,
defined as data encoding ELFDATA2MSB. For a little-endian encoded ELF file,
it holds the value 1, defined as data encoding ELFDATA2LSB.</para>
<programlisting>
e_ident[EI_CLASS] ELFCLASS64 For all 64-bit implementations.
e_ident[EI_DATA] ELFDATA2MSB For all big-endian implementations.
e_ident[EI_DATA] ELFDATA2LSB For all little-endian implementations.
</programlisting>
<programlisting>e_ident[EI_CLASS] ELFCLASS64 For all 64-bit implementations.
e_ident[EI_DATA] ELFDATA2MSB For all big-endian implementations.
e_ident[EI_DATA] ELFDATA2LSB For all little-endian implementations.</programlisting>
<para>The ELF header's e_flags member holds bit flags associated with the
file. The 64-bit PowerPC processor family defines the following
flags.</para>
@ -57,9 +55,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
</informaltable>
<para>The ABI version to be used for the ELF header file is specified with
the .abiversion pseudo-op:</para>
<programlisting>
.abiversion 2
</programlisting>
<programlisting>.abiversion 2</programlisting>
<para>Processor identification resides in the ELF header's e_machine
member, and must have the value EM_PPC64, defined as the value 21.</para>
</section>
@ -253,18 +249,16 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<para>The TOC may straddle the boundary between initialized and
uninitialized data in the data segment. The common order of sections in the
data segment, some of which may be empty, follows:</para>
<programlisting>
.rodata
.data
.data1
.got
.toc
.sdata
.sbss
.plt
.bss1
.bss
</programlisting>
<programlisting>.rodata
.data
.data1
.got
.toc
.sdata
.sbss
.plt
.bss1
.bss</programlisting>
<para>The medium code model is expected to provide a sufficiently large TOC
to provide all data addressing needs of a module with a single TOC.</para>
<para>Compilers may generate two-instruction medium code model references
@ -275,6 +269,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
instruction of the two instruction form with a nop and rewriting the second
instruction. Consequently, the TOC pointer must be live during the first
and second instruction of a two-instruction reference.)</para>
<para>&#160;</para>
<bridgehead>Modules Containing Multiple TOCs</bridgehead>
<para>The link editor may create multiple TOCs. In such a case, the
constituent .got, .toc, .sdata, and .sbss sections are conceptually
@ -436,16 +431,14 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
</informaltable>
<para>The local-entry-point handling field of st_other is generated with
the .localentry pseudo op:</para>
<programlisting>
.globl my_func
.type my_func, @function
my_func:
addis r2, r12, my_sym@ha(.TOC.-my_func)
addi r2, r2, my_sym@l(.TOC.-my_func)
.localentry my_func, .-my_func
... ; function definition
blr
</programlisting>
<programlisting revisionflag="changed"> .globl my_func
.type my_func, @function
my_func:
addis r2, r12, my_sym@ha(.TOC.-my_func)
addi r2, r2, my_sym@l(.TOC.-my_func)
.localentry my_func, .-my_func
... ; function definition
blr</programlisting>
<para>Functions called via symbols with an st_other value of 0 may be
called without a valid TOC pointer in r2. Symbols of functions that
require a local entry with a valid TOC pointer should generate a symbol
@ -2433,13 +2426,10 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<tfoot>
<row>
<entry nameend="c4" namest="c1" align="left">
<para>
<note>
<para>Relocation values 8, 9, 12, 13, 18, 23, 32,
<para><emphasis role="bold">Note:</emphasis>Relocation values 8, 9, 12, 13, 18, 23, 32,
and 247 are not used. This is to maintain a
correspondence to the relocation values used by the
32-bit PowerPC ELF ABI.</para>
</note>
32-bit PowerPC ELF ABI.
</para>
</entry>
</row>
@ -4201,10 +4191,8 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
stored is given by the assembly syntax symbol@got. The value of the
symbol alone is the address of the variable named symbol.</para>
<para>For example:</para>
<programlisting>
addis r3, r2,x@got@ha
ld r3,x@got@l(r3)
</programlisting>
<programlisting>addis r3, r2,x@got@ha
ld r3,x@got@l(r3)</programlisting>
<para>Although the Power ISA only defines 16-bit displacements, many TOCs
(and hence a GOT) are larger then 64 KB but fit within 2 GB, which can be
addressed with 32-bit offsets from r2. Therefore, this ABI defines a
@ -4239,18 +4227,14 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
current object file.</para>
<para>The following code might appear in a PIC code setup sequence to
compute the distance from a function entry point to the TOC base:</para>
<programlisting>
addis 2,12,.TOC.-func@ha
addi 2,2,.TOC.-func@l
</programlisting>
<programlisting>addis 2,12,.TOC.-func@ha
addi 2,2,.TOC.-func@l</programlisting>
<para>The syntax
<emphasis>SYMBOL@localentry</emphasis> refers to the value of the local
entry point associated with a function symbol. It can be used to
initialize a memory word with the address of the local entry point as
follows:</para>
<programlisting>
.quad func@localentry
</programlisting>
<programlisting>.quad func@localentry</programlisting>
</section>
</section>
<section>
@ -4282,15 +4266,11 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<emphasis>may</emphasis> optimize TOC reference code that consists of two
instructions with equivalent code when offset@ha is 0.</para>
<para>TOC reference code:</para>
<programlisting>
addis rt, r2, offset@ha
lwz rt, offset@l(rt)
</programlisting>
<programlisting>addis rt, r2, offset@ha
lwz rt, offset@l(rt)</programlisting>
<para>Equivalent code:</para>
<programlisting>
NOP
lwz rt, offset(r2)
</programlisting>
<programlisting>NOP
lwz rt, offset(r2)</programlisting>
<para>Compilers and programmers
<emphasis>must</emphasis> ensure that r2 is live at the actual data access
point associated with extended displacement addressing.</para>
@ -4308,32 +4288,30 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
disabling linker optimization. However, this behavior in support of
non-ABI-compliant code is not guaranteed to be portable and supported in
all systems.</para>
<para>&#160;</para>
<bridgehead>Compliant example</bridgehead>
<programlisting>
addis r4, r2, mysym@toc@ha
b target
...
addis r4, r2, mysym@toc@ha
target:
addi r4, r4, mysym@toc@l
...
</programlisting>
<programlisting> addis r4, r2, mysym@toc@ha
b target
...

addis r4, r2, mysym@toc@ha
target:
addi r4, r4, mysym@toc@l
...</programlisting>
<para>&#160;</para>
<bridgehead>Non-compliant example</bridgehead>
<programlisting>
li r4, 0 ; #d1
b target
...
addis r4, r2, mysym@toc@ha ; #d2
target:
addi r4, r4, mysym@toc@l ; incompatible definitions #d1 and #d2 reach this
...
</programlisting>
<programlisting> li r4, 0 ; #d1
b target
...
addis r4, r2, mysym@toc@ha ; #d2
target:
addi r4, r4, mysym@toc@l ; incompatible definitions #d1 and #d2 reach this
...</programlisting>
</section>
<section>
<title>Table Jump Sequences</title>
@ -4349,13 +4327,11 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
first an addis followed by a second instruction using a D form
instruction to create or load from a 32-bit offset from a register to
enable hardware fusion whenever possible:</para>
<programlisting>
addis r4, r3, upper
&lt;lbz,lhz,lwz,ld&gt; r4, lower(r4)
addis r4, r3, upper
addi r4, r4, lower
</programlisting>
<programlisting>addis r4, r3, upper
&lt;lbz,lhz,lwz,ld&gt; r4, lower(r4)
addis r4, r3, upper
addi r4, r4, lower</programlisting>
<para>It is encouraged that assemblers provide pseudo-ops to facilitate
such code generation with a single assembler mnemonic.</para>
</section>
@ -4408,59 +4384,53 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
computed as negative offsets from the TCB address. The fields must never
be rearranged for any reason.</para>
<para>The current glibc extended TCB is:</para>
<programlisting>
typedef struct {
/* Reservation for HWCAP data. */
unsigned int hwcap2;
unsigned int hwcap; /* not used in LE ABI */
/* Indicate if HTM capable (ISA 2.07). */
int tm_capable;
int tm_pad;
/* Reservation for dynamic system optimizer ABI. */
uintptr_t dso_slot2;
uintptr_t dso_slot1;
/* Reservation for tar register (ISA 2.07). */
uintptr_t tar_save;
/* GCC split stack support. */
void *__private_ss;
/* Reservation for the event-based branching ABI. */
uintptr_t ebb_handler;
uintptr_t ebb_ctx_pointer;
uintptr_t ebb_reserved1;
uintptr_t ebb_reserved2;
uintptr_t pointer_guard;
/* Reservation for stack guard */
uintptr_t stack_guard;
/* DTV pointer */
dtv_t *dtv;
} tcbhead_t;
</programlisting>
<programlisting>typedef struct {
/* Reservation for HWCAP data. */
unsigned int hwcap2;
unsigned int hwcap; /* not used in LE ABI */
/* Indicate if HTM capable (ISA 2.07). */
int tm_capable;
int tm_pad;
/* Reservation for dynamic system optimizer ABI. */
uintptr_t dso_slot2;
uintptr_t dso_slot1;
/* Reservation for tar register (ISA 2.07). */
uintptr_t tar_save;
/* GCC split stack support. */
void *__private_ss;
/* Reservation for the event-based branching ABI. */
uintptr_t ebb_handler;
uintptr_t ebb_ctx_pointer;
uintptr_t ebb_reserved1;
uintptr_t ebb_reserved2;
uintptr_t pointer_guard;
/* Reservation for stack guard */
uintptr_t stack_guard;
/* DTV pointer */
dtv_t *dtv;
} tcbhead_t;</programlisting>
<para>Modules that will not be unloaded will be present at startup time;
the TLS blocks for these are created consecutively and immediately follow
the TCB. The offset of the TLS block of an initially available module
from the TCB remains fixed after program start.</para>
<para>The tlsoffset(m) values for a module with index m, where m ranges 1
- M, M being the total number of modules, are computed as follows:</para>
<programlisting>
tlsoffset(1) = round(16, align(1))
tlsoffset(m + 1) = round(tlsoffset(m) + tlssize(m), align(m + 1))
</programlisting>
<programlisting>tlsoffset(1) = round(16, align(1))
tlsoffset(m + 1) = round(tlsoffset(m) + tlssize(m), align(m + 1))</programlisting>
<itemizedlist>
<listitem>
<para>The function round() returns its first argument rounded up to
the next multiple of its second argument:</para>
</listitem>
</itemizedlist>
<programlisting>
round(x, y) = y × ceiling(x / y)
</programlisting>
<programlisting>round(x, y) = y × ceiling(x / y)</programlisting>
<itemizedlist>
<listitem>
<para>The function ceiling() returns the smallest integer greater
@ -4468,24 +4438,20 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
1 &lt; x ≤ n:</para>
</listitem>
</itemizedlist>
<programlisting>
ceiling(x) = n
</programlisting>
<programlisting>ceiling(x) = n</programlisting>
<para>In the case of dynamic shared objects (DSO), TLS blocks are
allocated on an as-needed basis, with the details of allocation
abstracted away by the __tls_get_addr() function, which is used to
retrieve the address of any TLS variable.</para>
<para>The prototype for the __tls_get_addr() function, is defined as
follows.</para>
<programlisting>
typedef struct
{
unsigned long int ti_module;
unsigned long int ti_offset;
} tls_index;
extern void *__tls_get_addr (tls_index *ti);
</programlisting>
<programlisting>typedef struct
{
unsigned long int ti_module;
unsigned long int ti_offset;
} tls_index;
extern void *__tls_get_addr (tls_index *ti);</programlisting>
<para>The thread pointer (TP) is held in r13 and is used to access the
TCB. The TP is initialized to point 0x7000 bytes past the end of the TCB.
The TP offset allows for efficient addressing of the TCB and up to 4 KB -
@ -4551,10 +4517,8 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
thread-local variable x, the __tls_get_addr() function is called with one
parameter. That parameter is a pointer to a data object of type
tls_index.</para>
<programlisting>
extern __thread unsigned int x;
&amp;x;
</programlisting>
<programlisting>extern __thread unsigned int x;
&amp;x;</programlisting>
<table frame="all" pgwide="1">
<title>General Dynamic Initial Relocations</title>
<tgroup cols="3">
@ -4702,14 +4666,12 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
sequences may be used, depending on the size of the thread storage block
offset to the variable. For the following code sequence, a different
relocation sequence is used for each variable.</para>
<programlisting>
static __thread unsigned int x1;
static __thread unsigned int x2;
static __thread unsigned int x3;
&amp;x1;
&amp;x2;
&amp;x3;
</programlisting>
<programlisting>static __thread unsigned int x1;
static __thread unsigned int x2;
static __thread unsigned int x3;
&amp;x1;
&amp;x2;
&amp;x3;</programlisting>
<table frame="all" pgwide="1" xml:id="dbdoclet.50655241_45768">
<title>Local Dynamic Initial Relocations</title>
<tgroup cols="3">
@ -5100,10 +5062,8 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<para>Given the following code fragment, the relocation sequence in
<xref linkend="dbdoclet.50655241_17435" /> is used for the Initial Exec
TLS Model:</para>
<programlisting>
extern __thread unsigned int x;
&amp;x;
</programlisting>
<programlisting>extern __thread unsigned int x;
&amp;x;</programlisting>
<table frame="all" pgwide="1" xml:id="dbdoclet.50655241_17435">
<title>Initial Exec Initial Relocations</title>
<tgroup cols="3">
@ -5232,10 +5192,8 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
less than 2 GB + 28 KB relative to the end of the TCB. The third sequence
is identical to the Initial Exec sequence shown in
<xref linkend="dbdoclet.50655241_17435" />.</para>
<programlisting>
static __thread unsigned int x;
&amp;x;
</programlisting>
<programlisting>static __thread unsigned int x;
&amp;x;</programlisting>
<para><xref linkend="dbdoclet.50655241_51121" /> illustrates which sequence is
used.</para>
<para> </para>
@ -5765,12 +5723,10 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<xref linkend="dbdoclet.50655241_16273" />, a linker may reschedule the
sequence to exploit fusion by generating a sequence that may be fused
by Power processors:</para>
<programlisting>
nop
addis r3, r13, x@tprel@ha
addi r3, r3, x@tprel@l
nop
</programlisting>
<programlisting>nop
addis r3, r13, x@tprel@ha
addi r3, r3, x@tprel@l
nop</programlisting>
</footnote></para>
<para> </para>
<table frame="all" pgwide="1">
@ -6752,6 +6708,7 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<para>For more information, see
<xref linkend="dbdoclet.50655241_18894" />. For TLS relocations, see
<xref linkend="dbdoclet.50655241_47572" />.</para>
<para>&#160;</para>
<bridgehead>TLS Relocation Descriptions</bridgehead>
<para>The following marker relocations tie together instructions in TLS
code sequences. They allow the link editor to reliably optimize TLS code.

@ -341,10 +341,8 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
argument passing. For example, a C program might typically issue the
following declaration to begin executing at the local entry point of a
function named main:</para>
<programlisting>
extern int main (int argc, char *argv[], char *envp[], void *auxv[]);
int main(int argc, char *argv[], char *envp[], ElfW(auxv_t) *auxvec)
</programlisting>
<programlisting revisionflag="changed">extern int main (int argc, char *argv[], char *envp[], void *auxv[]);
int main(int argc, char *argv[], char *envp[], ElfW(auxv_t) *auxvec)</programlisting>
<para>where:</para>
<itemizedlist mark="none">
<listitem>
@ -546,55 +544,53 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
application program to another. However, the auxiliary vector conveys
information from the operating system to the program. This vector is an
array of structures, defined as follows:</para>
<programlisting>
typedef struct
<programlisting>typedef struct
{
long a_type;
union
{
long a_type;
union
{
long a_val;
void *a_ptr;
void (*a_fcn)();
} a_un;
} auxv_t;
Name Value a_un field Comment
AT_NULL 0 ignored /* End of vector */
AT_PHDR 3 a_ptr /* Program headers for program */
AT_PHENT 4 a_val /* Size of program header entry */
AT_PHNUM 5 a_val /* Number of program headers */
AT_PAGESZ 6 a_val /* System page size */
AT_BASE 7 a_ptr /* Base address of interpreter */
AT_FLAGS 8 a_val /* Flags */
AT_ENTRY 9 a_ptr /* Entry point of program */
AT_UID 11 /* Real user ID (uid) */
AT_EUID 12 /* Effective user ID (euid) */
AT_GID 13 /* Real group ID (gid) */
AT_EGID 14 /* Effective group ID (egid) */
AT_PLATFORM 15 a_ptr /* String identifying platform. */
AT_HWCAP 16 a_val /* Machine-dependent hints about
processor capabilities. */
AT_CLKTCK 17 /* Frequency of times(), always 100 */
AT_DCACHEBSIZE 19 a_val /* Data cache block size */
AT_ICACHEBSIZE 20 a_val /* Instruction cache block size */
AT_UCACHEBSIZE 21 a_val /* Unified cache block size */
AT_IGNOREPPC 22 /* Ignore this entry! */
AT_SECURE 23 /* Boolean, was exec authorized to use
setuid or setgid */
AT_BASE_PLATFORM 24 a_ptr /* String identifying real platforms */
AT_RANDOM 25 /* Address of 16 random bytes */
AT_HWCAP2 26 a_val /* More machine-dependent hints about
processor capabilities. */
AT_EXECFN 31 /* File name of executable */
AT_SYSINFO_EHDR 33 /* In many architectures, the kernel
provides a virtual dynamic shared
object (VDSO) that contains a function
callable from the user state.
AT_SYSINFO_EHDR is the address of the
VDSO header that is used by the
dynamic linker to resolve function
symbols with the VDSO. */
</programlisting>
long a_val;
void *a_ptr;
void (*a_fcn)();
} a_un;
} auxv_t;
Name Value a_un field Comment
AT_NULL 0 ignored /* End of vector */
AT_PHDR 3 a_ptr /* Program headers for program */
AT_PHENT 4 a_val /* Size of program header entry */
AT_PHNUM 5 a_val /* Number of program headers */
AT_PAGESZ 6 a_val /* System page size */
AT_BASE 7 a_ptr /* Base address of interpreter */
AT_FLAGS 8 a_val /* Flags */
AT_ENTRY 9 a_ptr /* Entry point of program */
AT_UID 11 /* Real user ID (uid) */
AT_EUID 12 /* Effective user ID (euid) */
AT_GID 13 /* Real group ID (gid) */
AT_EGID 14 /* Effective group ID (egid) */
AT_PLATFORM 15 a_ptr /* String identifying platform. */
AT_HWCAP 16 a_val /* Machine-dependent hints about
processor capabilities. */
AT_CLKTCK 17 /* Frequency of times(), always 100 */
AT_DCACHEBSIZE 19 a_val /* Data cache block size */
AT_ICACHEBSIZE 20 a_val /* Instruction cache block size */
AT_UCACHEBSIZE 21 a_val /* Unified cache block size */
AT_IGNOREPPC 22 /* Ignore this entry! */
AT_SECURE 23 /* Boolean, was exec authorized to use
setuid or setgid */
AT_BASE_PLATFORM 24 a_ptr /* String identifying real platforms */
AT_RANDOM 25 /* Address of 16 random bytes */
AT_HWCAP2 26 a_val /* More machine-dependent hints about
processor capabilities. */
AT_EXECFN 31 /* File name of executable */
AT_SYSINFO_EHDR 33 /* In many architectures, the kernel
provides a virtual dynamic shared
object (VDSO) that contains a function
callable from the user state.
AT_SYSINFO_EHDR is the address of the
VDSO header that is used by the
dynamic linker to resolve function
symbols with the VDSO. */</programlisting>
<para>AT_NULL</para>
<para>The auxiliary vector has no fixed length; instead an entry of this
type denotes the end of the vector. The corresponding value of a_un is
@ -660,44 +656,40 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<para>AT_HWCAP</para>
<para>The a_val member of this entry is a bit map of hardware
capabilities. Some bit mask values include:</para>
<programlisting>
PPC_FEATURE_32 0x80000000 /* Always set for powerpc64 */
PPC_FEATURE_64 0x40000000 /* Always set for powerpc64 */
PPC_FEATURE_HAS_ALTIVEC 0x10000000
PPC_FEATURE_HAS_FPU 0x08000000
PPC_FEATURE_HAS_MMU 0x04000000
PPC_FEATURE_UNIFIED_CACHE 0x01000000
PPC_FEATURE_NO_TB 0x00100000 /* 601/403gx have no timebase */
PPC_FEATURE_POWER4 0x00080000 /* POWER4 ISA 2.00 */
PPC_FEATURE_POWER5 0x00040000 /* POWER5 ISA 2.02 */
PPC_FEATURE_POWER5_PLUS 0x00020000 /* POWER5+ ISA 2.03 */
PPC_FEATURE_CELL_BE 0x00010000 /* CELL Broadband Engine */
PPC_FEATURE_BOOKE 0x00008000 /* ISA Category Embedded */
PPC_FEATURE_SMT 0x00004000 /* Simultaneous Multi-Threading */
PPC_FEATURE_ICACHE_SNOOP 0x00002000
PPC_FEATURE_ARCH_2_05 0x00001000 /* ISA 2.05 */
PPC_FEATURE_PA6T 0x00000800 /* PA Semi 6T Core */
PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal FP Unit */
PPC_FEATURE_POWER6_EXT 0x00000200 /* P6 + mffgpr/mftgpr */
PPC_FEATURE_ARCH_2_06 0x00000100 /* ISA 2.06 */
PPC_FEATURE_HAS_VSX 0x00000080 /* P7 Vector Extension. */
PPC_FEATURE_PSERIES_PERFMON_COMPAT 0x00000040
PPC_FEATURE_TRUE_LE 0x00000002
PPC_FEATURE_PPC_LE 0x00000001
</programlisting>
<programlisting>PPC_FEATURE_32 0x80000000 /* Always set for powerpc64 */
PPC_FEATURE_64 0x40000000 /* Always set for powerpc64 */
PPC_FEATURE_HAS_ALTIVEC 0x10000000
PPC_FEATURE_HAS_FPU 0x08000000
PPC_FEATURE_HAS_MMU 0x04000000
PPC_FEATURE_UNIFIED_CACHE 0x01000000
PPC_FEATURE_NO_TB 0x00100000 /* 601/403gx have no timebase */
PPC_FEATURE_POWER4 0x00080000 /* POWER4 ISA 2.00 */
PPC_FEATURE_POWER5 0x00040000 /* POWER5 ISA 2.02 */
PPC_FEATURE_POWER5_PLUS 0x00020000 /* POWER5+ ISA 2.03 */
PPC_FEATURE_CELL_BE 0x00010000 /* CELL Broadband Engine */
PPC_FEATURE_BOOKE 0x00008000 /* ISA Category Embedded */
PPC_FEATURE_SMT 0x00004000 /* Simultaneous Multi-Threading */
PPC_FEATURE_ICACHE_SNOOP 0x00002000
PPC_FEATURE_ARCH_2_05 0x00001000 /* ISA 2.05 */
PPC_FEATURE_PA6T 0x00000800 /* PA Semi 6T Core */
PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal FP Unit */
PPC_FEATURE_POWER6_EXT 0x00000200 /* P6 + mffgpr/mftgpr */
PPC_FEATURE_ARCH_2_06 0x00000100 /* ISA 2.06 */
PPC_FEATURE_HAS_VSX 0x00000080 /* P7 Vector Extension. */
PPC_FEATURE_PSERIES_PERFMON_COMPAT 0x00000040
PPC_FEATURE_TRUE_LE 0x00000002
PPC_FEATURE_PPC_LE 0x00000001</programlisting>
<para>AT_HWCAP2</para>
<para>The a_val member of this entry is a bit map of hardware
capabilities. Some bit mask values include:</para>
<programlisting>
PPC_FEATURE2_ARCH_2_07 0x80000000 /* ISA 2.07 */
PPC_FEATURE2_HAS_HTM 0x40000000 /* Hardware Transactional Memory */
PPC_FEATURE2_HAS_DSCR 0x20000000 /* Data Stream Control Register */
PPC_FEATURE2_HAS_EBB 0x10000000 /* Event Base Branching */
PPC_FEATURE2_HAS_ISEL 0x08000000 /* Integer Select */
PPC_FEATURE2_HAS_TAR 0x04000000 /* Target Address Register */
PPC_FEATURE2_HAS_VCRYPTO 0x02000000 /* The processor implements the
Vector.AES category */
</programlisting>
<programlisting>PPC_FEATURE2_ARCH_2_07 0x80000000 /* ISA 2.07 */
PPC_FEATURE2_HAS_HTM 0x40000000 /* Hardware Transactional Memory */
PPC_FEATURE2_HAS_DSCR 0x20000000 /* Data Stream Control Register */
PPC_FEATURE2_HAS_EBB 0x10000000 /* Event Base Branching */
PPC_FEATURE2_HAS_ISEL 0x08000000 /* Integer Select */
PPC_FEATURE2_HAS_TAR 0x04000000 /* Target Address Register */
PPC_FEATURE2_HAS_VCRYPTO 0x02000000 /* The processor implements the
Vector.AES category */</programlisting>
<para>When a process starts to execute, its stack holds the arguments,
environment, and auxiliary vector received from the exec call. The system
makes no guarantees about the relative arrangement of argument strings,
@ -934,14 +926,12 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
following the call.</para>
</listitem>
</orderedlist>
<programlisting>
tocsaveloc:
nop
...
bl target
.reloc ., R_PPC64_TOCSAVE, tocsaveloc
nop
</programlisting>
<programlisting>tocsaveloc:
nop
...
bl target
.reloc ., R_PPC64_TOCSAVE, tocsaveloc
nop</programlisting>
<orderedlist>
<listitem>
<para>3. The caller has not set up r2 to hold the TOC pointer. This
@ -965,45 +955,37 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<para>A possible implementation for case 1 looks as follows (if
func@plt@toc is less than 32 KB, the call stub may be simplified to omit
the addis):</para>
<programlisting>
std r2,24(r1)
addis r12,r2,func@plt@toc@ha
ld r12,func@plt@toc@l(r12)
mtctr r12
bctr
</programlisting>
<programlisting>std r2,24(r1)
addis r12,r2,func@plt@toc@ha
ld r12,func@plt@toc@l(r12)
mtctr r12
bctr</programlisting>
<para>For case 2, the same implementation as for case 1 may be used,
except that the first instruction “std r2,24(r1)” is omitted:</para>
<programlisting>
addis r12,r2,func@plt@toc@ha
ld r12,func@plt@toc@l(r12)
mtctr r12
bctr
</programlisting>
<programlisting>addis r12,r2,func@plt@toc@ha
ld r12,func@plt@toc@l(r12)
mtctr r12
bctr</programlisting>
<para>
<anchor xml:id="dbdoclet.50655242___DdeLink__61883_1749258592"
xreflabel="" /> A possible implementation for case 3 looks as
follows:</para>
<programlisting>
mflr r0
bcl 20,31,1f
1: mflr r2
mtlr r0
addis r2,r2,(.TOC.-1b)@ha
addi r2,r2,(.TOC.-1b)@l
addis r12,r2,func@plt@toc@ha
ld r12,func@plt@toc@l(r12)
mtctr r12
bctr
</programlisting>
<programlisting> mflr r0
bcl 20,31,1f
1: mflr r2
mtlr r0
addis r2,r2,(.TOC.-1b)@ha
addi r2,r2,(.TOC.-1b)@l
addis r12,r2,func@plt@toc@ha
ld r12,func@plt@toc@l(r12)
mtctr r12
bctr</programlisting>
<para>When generating non-PIC code for the small or medium code model, a
simpler variant may alternatively be used for cases 2 or 3:</para>
<programlisting>
lis r12,func@plt@ha
ld r12,func@plt@l(r12)
mtctr r12
bctr
</programlisting>
<programlisting>lis r12,func@plt@ha
ld r12,func@plt@l(r12)
mtctr r12
bctr</programlisting>
<para>To support lazy binding, the link editor also provides a set of
symbol resolver stubs, one for each PLT entry. Each resolver stub
consists of a single instruction, which is usually a branch to a common
@ -1029,52 +1011,50 @@ xmlns:xl="http://www.w3.org/1999/xlink" version="5.0" xml:lang="en">
<para>Beyond the above requirements, the implementation of the .glink
resolver stubs is up to the link editor. The following shows an example
implementation:</para>
<programlisting>
# ABI note: At entry to the resolver stub:
# - r12 holds the address of the res_N stub for the target routine
# - all argument registers hold arguments for the target routine
PLTresolve:
# Determine addressability. This sequence works for both PIC
# and non-PIC code and does not rely on presence of the TOC pointer.
mflr r0
bcl 20,31,1f
1: mflr r11
mtlr r0
# Compute .plt section index from entry point address in r12
# .plt section index is placed into r0 as argument to the resolver
sub r0,r12,r11
subi r0,r0,res_0-1b
srdi r0,r0,2
# Load address of the first byte of the PLT
ld r12,PLToffset-1b(r11)
add r11,r12,r11
# Load resolver address and DSO identifier from the
# first two doublewords of the PLT
ld r12,0(r11)
ld r11,8(r11)
# Branch to resolver
mtctr r12
bctr
# ABI note: At entry to the resolver:
# - r12 holds the resolver address
# - r11 holds the DSO identifier
# - r0 holds the PLT index of the target routine
# - all argument registers hold arguments for the target routine
# Constant pool holding offset to the PLT
# Note that there is no actual symbol PLT; the link editor
# synthesizes this value when creating the .glink section
PLToffset:
.quad PLT-.
# A table of branches, one for each PLT entry
# The idea is that the PLT call stub loads r12 with these
# addresses, so (r12 - res_0) gives the PLT index × 4.
res_0: b PLTresolve
res_1: b PLTresolve
...
</programlisting>
<programlisting> # ABI note: At entry to the resolver stub:
# - r12 holds the address of the res_N stub for the target routine
# - all argument registers hold arguments for the target routine
PLTresolve:
# Determine addressability. This sequence works for both PIC
# and non-PIC code and does not rely on presence of the TOC pointer.
mflr r0
bcl 20,31,1f
1: mflr r11
mtlr r0
# Compute .plt section index from entry point address in r12
# .plt section index is placed into r0 as argument to the resolver
sub r0,r12,r11
subi r0,r0,res_0-1b
srdi r0,r0,2
# Load address of the first byte of the PLT
ld r12,PLToffset-1b(r11)
add r11,r12,r11
# Load resolver address and DSO identifier from the
# first two doublewords of the PLT
ld r12,0(r11)
ld r11,8(r11)
# Branch to resolver
mtctr r12
bctr
# ABI note: At entry to the resolver:
# - r12 holds the resolver address
# - r11 holds the DSO identifier
# - r0 holds the PLT index of the target routine
# - all argument registers hold arguments for the target routine
# Constant pool holding offset to the PLT
# Note that there is no actual symbol PLT; the link editor
# synthesizes this value when creating the .glink section
PLToffset:
.quad PLT-.
# A table of branches, one for each PLT entry
# The idea is that the PLT call stub loads r12 with these
# addresses, so (r12 - res_0) gives the PLT index × 4.
res_0: b PLTresolve
res_1: b PLTresolve
...</programlisting>
<para>After resolution, the value of a PLT entry in the PLT is the
address of the functions global entry point, unless the resolver can
determine that a module-local call occurs with a shared TOC value wherein

@ -45,9 +45,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317">
by the linker as necessary to resolve symbols.</para>
</section>
<section xml:id="dbdoclet.50655243_page131">
<title>Types Defined in the Standard Header
<anchor xml:id="dbdoclet.50655243___RefHeading___Toc377640670"
xreflabel="" /> Types Defined in the Standard Header</title>
<title xml:id="dbdoclet.50655243___RefHeading___Toc377640670">Types Defined in the Standard Header</title>
<para>The type va_list shall be defined as follows:</para>
<para><literal>typedef void * va_list;</literal></para>
<para>The following integer types are defined in headers, which must be
@ -55,13 +53,13 @@ xml:id="dbdoclet.50655243_pgfId-1099317">
such headers. They shall have the following definitions:</para>
<itemizedlist spacing="compact">
<listitem>
<para>typedef long ptrdiff_t;</para>
<para>typedef long <phrase revisionflag="deleted">long</phrase> ptrdiff_t;</para>
</listitem>
<listitem>
<para>typedef unsigned long size_t;</para>
<para>typedef unsigned <phrase revisionflag="added">long</phrase><phrase revisionflag="deleted">int</phrase> size_t;</para>
</listitem>
<listitem>
<para>typedef int wchar_t;</para>
<para>typedef <phrase revisionflag="added">int</phrase><phrase revisionflag="deleted">long</phrase> wchar_t;</para>
</listitem>
<listitem>
<para>typedef int sig_atomic_t;</para>
@ -79,7 +77,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317">
<para>typedef int int32_t;</para>
</listitem>
<listitem>
<para>typedef long int64_t;</para>
<para>typedef long <phrase revisionflag="deleted">long</phrase> int64_t;</para>
</listitem>
<listitem>
<para>typedef unsigned char uint8_t;</para>
@ -91,7 +89,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317">
<para>typedef unsigned int uint32_t;</para>
</listitem>
<listitem>
<para>typedef unsigned long uint64_t;</para>
<para>typedef unsigned long <phrase revisionflag="deleted">long</phrase> uint64_t;</para>
</listitem>
<listitem>
<para>typedef signed char int_least8_t;</para>
@ -103,7 +101,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317">
<para>typedef int int_least32_t;</para>
</listitem>
<listitem>
<para>typedef long int_least64_t;</para>
<para>typedef long <phrase revisionflag="deleted">long</phrase> int_least64_t;</para>
</listitem>
<listitem>
<para>typedef unsigned char uint_least8_t;</para>
@ -115,7 +113,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317">
<para>typedef unsigned int uint_least32_t;</para>
</listitem>
<listitem>
<para>typedef unsigned long uint_least64_t;</para>
<para>typedef unsigned long <phrase revisionflag="deleted">long</phrase> uint_least64_t;</para>
</listitem>
<listitem>
<para>typedef signed char int_fast8_t;</para>
@ -127,7 +125,7 @@ xml:id="dbdoclet.50655243_pgfId-1099317">
<para>typedef int int_fast32_t;</para>
</listitem>
<listitem>
<para>typedef long int_fast64_t;</para>
<para>typedef long <phrase revisionflag="deleted">long</phrase> int_fast64_t;</para>
</listitem>
<listitem>
<para>typedef unsigned char uint_fast8_t;</para>
@ -139,19 +137,19 @@ xml:id="dbdoclet.50655243_pgfId-1099317">
<para>typedef unsigned int uint_fast32_t;</para>
</listitem>
<listitem>
<para>typedef unsigned long uint_fast64_t;</para>
<para>typedef unsigned long <phrase revisionflag="deleted">long</phrase> uint_fast64_t;</para>
</listitem>
<listitem>
<para>typedef long intptr_t;</para>
<para>typedef long <phrase revisionflag="deleted">long</phrase> intptr_t;</para>
</listitem>
<listitem>
<para>typedef unsigned long uintptr_t;</para>
<para>typedef unsigned long <phrase revisionflag="deleted">long</phrase> uintptr_t;</para>
</listitem>
<listitem>
<para>typedef long intmax_t;</para>
<para>typedef long <phrase revisionflag="deleted">long</phrase> intmax_t;</para>
</listitem>
<listitem>
<para>typedef unsigned long uintmax_t;</para>
<para>typedef unsigned long <phrase revisionflag="deleted">long</phrase> uintmax_t;</para>
</listitem>
</itemizedlist>
</section>

@ -65,27 +65,23 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
access the n-th vector element from a vector pointer. The use of vector
built-in functions such as vec_xl and vec_xst is discouraged except for
languages where no dereference operators are available.</para>
<programlisting>
vector char vca;
vector char vcb;
vector int via;
int a[4];
void *vp;
via = *(vector int *) &amp;a[0];
vca = (vector char) via;
vcb = vca;
vca = *(vector char *)vp;
*(vector char *)&amp;a[0] = vca;
</programlisting>
<programlisting>vector char vca;
vector char vcb;
vector int via;
int a[4];
void *vp;
via = *(vector int *) &amp;a[0];
vca = (vector char) via;
vcb = vca;
vca = *(vector char *)vp;
*(vector char *)&amp;a[0] = vca;</programlisting>
<para>Compilers are expected to recognize and optimize multiple operations
that can be optimized into a single hardware instruction. For example, a
load and splat hardware instruction might be generated for the following
sequence:</para>
<programlisting>
double *double_ptr;
register vector double vd = vec_splats(*double_ptr);
</programlisting>
<programlisting>double *double_ptr;
register vector double vd = vec_splats(*double_ptr);</programlisting>
</section>
<section xml:id="dbdoclet.50655244_83520">
<title>Vector Operators</title>
@ -231,7 +227,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
</row>
</thead>
<tbody>
<row>
<row revisionflag="added">
<entry>
<para>vec_bperm</para>
</entry>
@ -243,7 +239,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
the result.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_cntlz_lsbb</para>
</entry>
@ -254,7 +250,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
<para>For LE, use vctzlsbb.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_cnttz_lsbb</para>
</entry>
@ -276,7 +272,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
<para>vec_extract (v, 3) is equivalent to v[3].</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_extract_fp32_</para>
<para>from_shorth</para>
@ -288,7 +284,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
<para>For LE, extract the left four elements.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_extract_fp32_</para>
<para>from_shortl</para>
@ -300,7 +296,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
<para>For LE, extract the right four elements.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_extract4b</para>
</entry>
@ -312,7 +308,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
halves of the result.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_first_match</para>
<para>_index</para>
@ -324,7 +320,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
<para>For LE, use vctz.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_first_match</para>
<para>_index_or_eos</para>
@ -348,7 +344,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
<emphasis>third</emphasis> element modified to contain x.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_insert4b</para>
</entry>
@ -546,7 +542,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
<para>Use vupkhsb, and so on, for LE.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_xl_len_r</para>
</entry>
@ -559,7 +555,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
number of bytes specified to be loaded by vec_xl_len_r.</para>
</entry>
</row>
<row>
<row revisionflag="added">
<entry>
<para>vec_xst_len_r</para>
</entry>
@ -582,6 +578,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
another vector data type in accordance with the C and C++
programming languages.</para>
</note>
<para>&#160;</para>
<bridgehead>Extended Data Movement Functions</bridgehead>
<para>The built-in functions in
<xref linkend="dbdoclet.50655244_42521" /> map to Altivec/VMX load and
@ -1176,7 +1173,7 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
</row>
<row>
<entry>
<para>vec_xlw4
<para>vec_xlw<phrase revisionflag="added">4</phrase>
<footnote xml:id="dbdoclet.50655244_78719">
<para>Deprecated. The use of vector data type
assignment and overloaded vec_xl and vec_xst vector
@ -1298,54 +1295,6 @@ xml:id="dbdoclet.50655244_pgfId-1095944">
</row>
</thead>
<tbody>
<row>
<entry>
<para>VEC_CONCAT (ARG1, ARG2)</para>
<para>(Fortran)</para>
<para>POWER ISA 3.0</para>
</entry>
<entry>
<para>Purpose:</para>
<para>Concatenates two elements to form a vector.</para>
<para>Result value:</para>
<para>The resulting vector consists of the two scalar elements,
ARG1 and ARG2, assigned to elements 0 and 1 (using the
environments native endian numbering), respectively.</para>
<itemizedlist>
<listitem>
<para><emphasis role="bold">Note: </emphasis>This function corresponds to the C/C++ vector
constructor (vector type){a,b}. It is provided only for
languages without vector constructors.</para>
</listitem>
</itemizedlist>
</entry>
</row>
<row>
<entry>
<para>POWER ISA 3.0</para>
</entry>
<entry>
<para>vector signed long long vec_concat (signed long long,
signed long long);</para>
</entry>
</row>
<row>
<entry>
<para>POWER ISA 3.0</para>
</entry>
<entry>
<para>vector unsigned long long vec_concat (unsigned long long,
unsigned long long);</para>
</entry>
</row>
<row>
<entry>
<para>POWER ISA 3.0</para>
</entry>
<entry>
<para>vector double vec_concat (double, double);</para>
</entry>
</row>
<row>
<entry>
<para>VEC_CONVERT(V, MOLD)</para>

@ -19,7 +19,55 @@
xmlns:xi="http://www.w3.org/2001/XInclude"
xmlns:xlink="http://www.w3.org/1999/xlink"
version="5.0"
xml:id="ch_PAPR_preface">
xml:id="ch_ABI_preface">
<title>About this Document</title>

<para>This specification defines the OpenPOWER ELF V2 application binary interface (ABI).
This ABI is derived from and represents the first major update to the Power ABI since the
original release of the IBM® RS/6000® ABI. It was developed to make extensive use of new
functions available in OpenPOWER-compliant processors. It expects an OpenPOWER-compliant
processor to implement at least Power ISA V2.07B with all OpenPOWER Architecture instruction
categories as well as OpenPOWER-defined implementation characteristics for some
implementation-specific features.
</para>
<para>Specifically, to use this ABI and ABI-compliant programs, OpenPOWER-compliant
processors must implement the following categories:
<itemizedlist>
<listitem><para>Base</para></listitem>
<listitem><para>64-Bit</para></listitem>
<listitem><para>Server (subject to system-level requirements)</para></listitem>
<listitem><para>Floating-Point</para></listitem>
<listitem><para>Floating-Point.Record</para></listitem>
<listitem><para>Load/Store Quadword x2</para></listitem>
<listitem><para>Store Conditional Page Mobility (subject to system-level requirements)</para></listitem>
<listitem><para>Stream</para></listitem>
<listitem><para>Transactional Memory</para></listitem>
<listitem><para>Vector</para></listitem>
<listitem><para>Vector.Little-Endian</para></listitem>
<listitem><para>Vector-Scalar</para></listitem>
</itemizedlist>
</para>
<para>For more information about these categories, see “Categories” in Book I of
<citetitle>Power ISA</citetitle>, version 2.07B.
</para>
<para>The OpenPOWER ELF V2 ABI is intended for use in little- and big-endian environments.
</para>
<section>
<title>Notices</title>
<?dbhtml stop-chunking?>

@ -61,6 +109,10 @@
<link xlink:href="http://www.freescale.com/files/abstract/help_page/TERMSOFUSE.html">www.freescale.com/files/abstract/help_page/TERMSOFUSE.html</link>.
</para>

<para>Itanium, Intel logo, Intel Inside logo, and Intel Centrino logo are trademarks or registered
trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
</para>
<para>Linux is a trademark of Linus Torvalds in the United States, other countries, or both.
</para>

@ -70,5 +122,6 @@

<para>Other company, product, and service names may be trademarks or service marks of others.
</para>

</section>
</preface>

@ -53,10 +53,10 @@
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