DWARF mapping of XER does not match its size #111

In chapter 2, section 2.4, the table "DWARF Mappings of Common Registers" shows XER with a "Register Width (Bytes)" of 4. The POWER ISA (chapter 3, section 3.2.2, "Fixed-Point Exception Register") says "The Fixed-Point Exception Register (XER) is a 64-bit register", or 8 bytes.

Does the DWARF mapping of XER only map the lower 32bits (4 bytes)? It should be noted that all of the upper 32 bits are "Reserved" in the POWER ISA. If so, then perhaps a footnote in the table would suffice to explain the discrepancy.

In chapter 2, section 2.4, the table "DWARF Mappings of Common Registers" shows XER with a "Register Width (Bytes)" of 4. The POWER ISA (chapter 3, section 3.2.2, "Fixed-Point Exception Register") says "The Fixed-Point Exception Register (XER) is a 64-bit register", or 8 bytes. Does the DWARF mapping of XER only map the lower 32bits (4 bytes)? It should be noted that all of the upper 32 bits are "Reserved" in the POWER ISA. If so, then perhaps a footnote in the table would suffice to explain the discrepancy.

Yes, the DWARF register is defined as only 32 bits. Changing that is a lot of pain, and since
nothing uses any of the upper 32 bits, we do not have to change. A footnote can be helpful
(if it is helpful, doesn't confuse the reader more :-) )

Yes, the DWARF register is defined as only 32 bits. Changing that is a lot of pain, and since nothing uses any of the upper 32 bits, we do not have to change. A footnote can be helpful (if it *is* helpful, doesn't confuse the reader more :-) )

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DWARF mapping of XER does not match its size #111