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712 lines
25 KiB
XML
712 lines
25 KiB
XML
7 years ago
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<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright (c) 2016 OpenPOWER Foundation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<section xmlns="http://docbook.org/ns/docbook"
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xmlns:xi="http://www.w3.org/2001/XInclude"
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xmlns:xlink="http://www.w3.org/1999/xlink"
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version="5.0"
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xml:id="Internal_Error_Indications">
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<title>Internal Error Indications</title>
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<para>Hardware may detect a variety of problems during operation, ranging
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from soft errors which have already been corrected by the time they are
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reported, to hard errors of such severity that the OS (and perhaps the
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hardware) cannot meaningfully continue operation. The mechanisms
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described in
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<xref linkend="dbdoclet.50569337_66258"/> are used to report such errors to the
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OS. This section describes the architectural sources of errors, and
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describes a method that platforms can use to report the error. All OSs
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need to be prepared to encounter the errors reported as they are
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described here. However, in some platforms more sophisticated handling
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may be introduced via RTAS, and the OS may not have to handle the error
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directly. More robust error detection, reporting, and correcting are at
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the option of the hardware vendor.</para>
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<para>
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<anchor xml:id="dbdoclet.50569337_marker-13885" xreflabel="" />
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<anchor xml:id="dbdoclet.50569337_marker-13886" xreflabel="" />The
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primary architectural mechanism for indicating hardware errors to an OS
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is the machine check interrupt. If an error condition is surfaced by
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placing the system in checkstop, it precludes any immediate participation
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by the OS in handling the error (that is, no error capture, logging,
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recovery, analysis, or notification by the OS). For this reason, the
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machine check interrupt is preferred over going to the checkstop state.
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However, checkstop may be necessary in certain situations where further
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processing represents an exposure to loss of data integrity. To better
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handle such cases, a special hardware mechanism may be provided to gather
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and store residual error data, to be analyzed when the system goes
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through a subsequent successful reboot.</para>
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<para>Less critical internal errors may also be signaled to the OS
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through a platform-specific interrupt in the “Internal
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Errors” class, or by periodic polling with the
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<emphasis>event-scan</emphasis> RTAS function.</para>
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<para><emphasis role="bold">Architecture Note:</emphasis> The machine check interrupt will not be listed
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in the OF node for the “Internal Errors” class, since it is a
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standard architectural mechanism. The machine check interrupt mechanism
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is enabled from software or firmware by setting the MSRME bit =1. Upon
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the occurrence of a machine check interrupt, bits in SRR1 will indicate
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the source of the interrupt and SRR0 will contain the address of the next
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instruction that would have been executed if the interrupt had not
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occurred. Depending on where the error is detected, the machine check
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interrupt may be surfaced from within the processor, via logical
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connection to the processor machine check interrupt pin, or via a system
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bus error indicator (for example, Transfer Error Acknowledge -
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TEA).</para>
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<variablelist>
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<varlistentry xml:id="dbdoclet.50569337_38528">
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<term><emphasis role="bold">R1-<xref linkend="Internal_Error_Indications"
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xrefstyle="select: labelnumber nopage"/>-1.</emphasis></term>
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<listitem>
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<para>OSs must set
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MSRME=1 prior to the occurrence of a machine check interrupt in order to
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enable machine check processing via the
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<emphasis>check-exception</emphasis> RTAS function.</para>
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<para>
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<emphasis role="bold">Architecture Note:</emphasis> Requirement
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<xref linkend="dbdoclet.50569337_38528"/> is not applicable when the FWNMI
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option is used.</para>
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</listitem>
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</varlistentry>
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<varlistentry xml:id="dbdoclet.50569337_36603">
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<term><emphasis role="bold">R1-<xref linkend="Internal_Error_Indications"
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xrefstyle="select: labelnumber nopage"/>-2.</emphasis></term>
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<listitem>
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<para>For
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hardware-detected errors, platforms must generate error indications as
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described in
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<xref linkend="dbdoclet.50569337_30773"/>, unless the error can be handled
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through a less severe platform-specific interrupt, or the nature of the
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error forces a checkstop condition.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">R1-<xref linkend="Internal_Error_Indications"
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xrefstyle="select: labelnumber nopage"/>-3.</emphasis></term>
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<listitem>
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<para>Platforms which detect and report the
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errors described in
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<xref linkend="dbdoclet.50569337_30773"/> must provide information to the OS
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via the RTAS
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<emphasis>check-exception</emphasis> function, using the reporting format
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described in
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<xref linkend="dbdoclet.50569337_21249"/>.</para>
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</listitem>
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</varlistentry>
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<varlistentry xml:id="dbdoclet.50569337_16228">
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<term><emphasis role="bold">R1-<xref linkend="Internal_Error_Indications"
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xrefstyle="select: labelnumber nopage"/>-4.</emphasis></term>
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<listitem>
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<para>To prevent error
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propagation and allow for synchronization of error handling, all
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processors in a multi-processor system must receive any machine check
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interrupt signaled via the external machine check interrupt pin.</para>
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</listitem>
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</varlistentry>
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</variablelist>
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<para>
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<emphasis role="bold">Platform Implementation Notes:</emphasis>
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</para>
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<orderedlist>
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<listitem>
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<para>The intent of Requirement
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<xref linkend="dbdoclet.50569337_36603"/> is to define standard error
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notification mechanisms for different hardware error types. For most
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hardware errors, the signaling mechanism is the machine check interrupt,
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although this requirement hints at the use of a less severe
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platform-specific interrupt for some errors. The important point here is
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actually whether the error can be handled through that interrupt. Simply
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using an external interrupt to signal the error is not sufficient. The
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hardware and RTAS also need to limit the propagation of corrupted data,
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prevent loss of error state data, and support the cleanup and recovery of
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such an error. Since the response to an external interrupt may be
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significantly slower than a machine check, and in fact may be masked, the
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error should not require immediate action on the part of the OS and/or
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RTAS. In addition, external interrupts (except external machine check
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interrupts) are reported to only one processor, so operations by the
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other processors in an MP system should not be impacted by this error
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unless they specifically try to access the failing hardware element. To
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summarize, platforms should not use platform-specific interrupts to
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signal hardware errors unless there is a complete hardware/RTAS platform
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solution for handling such errors.</para>
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</listitem>
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<listitem>
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<para>The intent of Requirement
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<xref linkend="dbdoclet.50569337_16228"/> is that most hardware errors would be
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signaled simultaneously to all processors, so that processors could
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synchronize the error handling process; that is, one processor would be
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chosen to do the call to
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<emphasis>check-exception</emphasis>, while the other processors remained
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idle so that they would not interfere with RTAS while it gathered machine
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check error data. While this is a straightforward wiring solution for
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errors signaled via the external machine check interrupt pin, that is not
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the case for internal processor errors or processor bus errors.
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Typically, only one processor will see such errors. An internal processor
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error can be identified with just the contents of SRR1, and so can be
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handled without synchronization with other processors. Processor bus
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errors, however, can be more difficult, especially if the error is
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propagated up to the processor bus from a lower-level bus. In general,
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such propagation should be avoided, and such errors should be signaled
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through the machine check interrupt pin to ensure proper error
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handling.</para>
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</listitem>
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</orderedlist>
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<section xml:id="dbdoclet.50569337_52952">
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<title>Error Indication Mechanisms</title>
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<para>
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<xref linkend="dbdoclet.50569337_30773"/> describes the mechanisms by
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which software will be notified of the occurrence of operational failures
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during the types of data transfer operations listed below. The assumption
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here is that the error notification can occur only if a hardware
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mechanism for error detection (for example, a parity checker) is present.
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In cases where there is no specific error detection mechanism, the
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resulting condition, and whether the software will eventually recognize
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that condition as a failure, is undefined.</para>
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<para> </para>
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<table frame="all" pgwide="1" xml:id="dbdoclet.50569337_30773">
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<title>Error Indications for System Operations</title>
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<tgroup cols="6">
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<colspec colname="c1" colwidth="10*" />
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<colspec colname="c2" colwidth="10*" />
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<colspec colname="c3" colwidth="20*" />
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<colspec colname="c4" colwidth="20*" />
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<colspec colname="c5" colwidth="20*" />
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<colspec colname="c6" colwidth="20*" />
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<thead>
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<row>
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<entry>
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<para>
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<emphasis role="bold">Initiator</emphasis>
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</para>
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</entry>
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<entry>
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<para>
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<emphasis role="bold">Target</emphasis>
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</para>
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</entry>
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<entry>
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<para>
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<emphasis role="bold">Operation</emphasis>
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</para>
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</entry>
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<entry>
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<para>
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<emphasis role="bold">Error Type(if detected)</emphasis>
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</para>
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</entry>
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<entry>
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<para>
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<emphasis role="bold">Indication to Software</emphasis>
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</para>
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</entry>
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<entry>
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<para>
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<emphasis role="bold">Comments</emphasis>
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</para>
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</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry>
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<para>Processor</para>
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</entry>
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<entry>
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<para>N/A</para>
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</entry>
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<entry>
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<para>Internal</para>
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</entry>
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<entry>
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<para>Various</para>
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</entry>
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<entry>
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<para>Machine check</para>
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</entry>
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<entry>
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<para>Some may cause checkstop</para>
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</entry>
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</row>
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<row>
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<entry morerows="11">
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<para>Processor</para>
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</entry>
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<entry morerows="11">
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<para>Memory</para>
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</entry>
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<entry morerows="4">
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<para>Load</para>
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</entry>
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<entry>
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<para>Invalid address</para>
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</entry>
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<entry>
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<para>Machine check</para>
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</entry>
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<entry>
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<para> </para>
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</entry>
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</row>
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<row>
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<entry>
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<para>System bus time-out</para>
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</entry>
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<entry>
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<para>Machine check</para>
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</entry>
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<entry>
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<para> </para>
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</entry>
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</row>
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<row>
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<entry>
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<para>Address parity on system bus</para>
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</entry>
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<entry>
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<para>Machine check</para>
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</entry>
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<entry>
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<para> </para>
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</entry>
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</row>
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<row>
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<entry>
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<para>Data parity on system bus</para>
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</entry>
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<entry>
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<para>Machine check</para>
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</entry>
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<entry>
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<para> </para>
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</entry>
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</row>
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<row>
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<entry>
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<para>Memory parity or uncorrectable ECC</para>
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</entry>
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<entry>
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<para>Machine check</para>
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</entry>
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<entry>
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<para> </para>
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</entry>
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</row>
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<row>
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<entry morerows="3">
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<para>Store</para>
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</entry>
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<entry>
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<para>Invalid address</para>
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</entry>
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<entry>
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<para>Machine check</para>
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||
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</entry>
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<entry>
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<para> </para>
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||
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</entry>
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||
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</row>
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<row>
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||
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<entry>
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<para>System bus time-out</para>
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</entry>
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<entry>
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<para>Machine check</para>
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</entry>
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<entry>
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<para> </para>
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</entry>
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</row>
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<row>
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<entry>
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<para>Address parity on system bus</para>
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</entry>
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<entry>
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<para>Machine check</para>
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||
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</entry>
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||
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<entry>
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<para> </para>
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</entry>
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</row>
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<row>
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<entry>
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<para>Data parity on system bus</para>
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||
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</entry>
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<entry>
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<para>Machine check</para>
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</entry>
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<entry>
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<para> </para>
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||
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</entry>
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||
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</row>
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<row>
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|
|
<entry>
|
||
|
|
<para>External cache load</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Memory parity or uncorrectable ECC</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Machine check</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Associated with Instruction Fetch or Data Load</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>External cache flush</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Cache parity or</para>
|
||
|
|
<para>uncorrectable ECC</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Machine check</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para> </para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>External cache access</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Cache parity or</para>
|
||
|
|
<para>uncorrectable ECC</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Machine check</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Associated with Instruction Fetch or Data Transfer</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>Processor</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>I/O</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Load or Store</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Various errors between the processor and the I/O
|
||
|
|
fabric</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Machine check</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>I/O fabrics include hubs and bridges and interconnecting
|
||
|
|
buses or links.</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry morerows="3">
|
||
|
|
<para>Processor</para>
|
||
|
|
</entry>
|
||
|
|
<entry morerows="3">
|
||
|
|
<para>I/O bus configuration space</para>
|
||
|
|
</entry>
|
||
|
|
<entry morerows="1">
|
||
|
|
<para>Read</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Various, except no response from IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Firmware receives a machine check, OS receives
|
||
|
|
all=1’s data along with a
|
||
|
|
<emphasis>Status</emphasis> of -1 from the RTAS call</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>If EEH is implemented and enabled, firmware does not get
|
||
|
|
a machine check and the PE is in the EEH Stopped State on
|
||
|
|
return from the RTAS call</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>No response from an IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>All-1’s data returned, along with a
|
||
|
|
“Success”
|
||
|
|
<emphasis>Status</emphasis> from the RTAS call</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>If EEH is implemented and enabled, the PE is not in the
|
||
|
|
EEH Stopped State on return from the RTAS call</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry morerows="1">
|
||
|
|
<para>Write</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Various, except no response from IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Firmware receives a machine check, OS receives a
|
||
|
|
<emphasis>Status</emphasis> of -1 from the RTAS call</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>If EEH is implemented and enabled, firmware does not get
|
||
|
|
a machine check and the PE is in the EEH Stopped State on
|
||
|
|
return from the RTAS call</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>No response from an IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Operation ignored, OS receives a “Success”
|
||
|
|
<emphasis>Status</emphasis> from the RTAS call</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>If EEH is implemented and enabled, the PE is in the EEH
|
||
|
|
Stopped State on return from the RTAS call</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry morerows="3">
|
||
|
|
<para>Processor</para>
|
||
|
|
</entry>
|
||
|
|
<entry morerows="3">
|
||
|
|
<para>I/O bus;</para>
|
||
|
|
<para>I/O Space</para>
|
||
|
|
<para>or</para>
|
||
|
|
<para>Memory Space</para>
|
||
|
|
</entry>
|
||
|
|
<entry morerows="1">
|
||
|
|
<para>Load</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Various, except no response from IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Machine check</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>If EEH is implemented and enabled, no machine check is
|
||
|
|
received, all-1’s data is returned, and the PE enters the
|
||
|
|
EEH Stopped State</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>No response from an IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>All-1’s data returned</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Invalid address, broken IOA, or configuration cycle to
|
||
|
|
non-existent IOA; if EEH is implemented and enabled, the PE
|
||
|
|
enters the EEH Stopped State</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry morerows="1">
|
||
|
|
<para>Store</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Various, except no response from IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Machine check</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>If EEH is implemented and enabled, no machine check is
|
||
|
|
received and the PE enters the EEH Stopped State</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>No response from IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Ignore Store</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Invalid address, broken IOA, or configuration cycle to
|
||
|
|
non-existent IOA; if EEH is implemented and enabled, the PE
|
||
|
|
enters the EEH Stopped State</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>Processor</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Invalid address (addressing an “undefined”
|
||
|
|
address area)</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Load or Store</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>No response from system</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Machine check</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para> </para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>I/O</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Memory</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>DMA - either direction</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Various, including but not limited to:</para>
|
||
|
|
|
||
|
|
<itemizedlist>
|
||
|
|
<listitem>
|
||
|
|
<para>Invalid addr accepted by a bridge</para>
|
||
|
|
</listitem>
|
||
|
|
|
||
|
|
<listitem>
|
||
|
|
<para>TCE extent</para>
|
||
|
|
</listitem>
|
||
|
|
|
||
|
|
<listitem>
|
||
|
|
<para>TCE Page Mapping and Control mis-match or invalid
|
||
|
|
TCE</para>
|
||
|
|
</listitem>
|
||
|
|
</itemizedlist>
|
||
|
|
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Machine check unless reportable directly to the IOA in a
|
||
|
|
way that allows the IOA to signal the error to its device
|
||
|
|
driver</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>If EEH is implemented and enabled, no machine check is
|
||
|
|
received and the PE enters the EEH Stopped State</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>I/O</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>I/O</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>DMA - either direction</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Various</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Machine check unless reportable to master of the transfer
|
||
|
|
in a way that allows master to recover</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para> </para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>I/O</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Invalid address</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>DMA - either direction</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>No response from any IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>PCI IOA</para>
|
||
|
|
<para>master-aborts</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Signal device driver using an external interrupt</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
<row>
|
||
|
|
<entry>
|
||
|
|
<para>PCI IOA</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>-</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Any</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>Internal, indicated by SERR# or ERR_FATAL</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>SERR# or ERR_FATAL, causing machine check</para>
|
||
|
|
</entry>
|
||
|
|
<entry>
|
||
|
|
<para>If EEH is implemented and enabled, no machine check is
|
||
|
|
received and the PE enters the EEH Stopped State</para>
|
||
|
|
</entry>
|
||
|
|
</row>
|
||
|
|
</tbody>
|
||
|
|
</tgroup>
|
||
|
|
</table>
|
||
|
|
|
||
|
|
<para><emphasis role="bold">Implementation Note:</emphasis> IOAs should, whenever possible, detect the
|
||
|
|
occurrence of PCI errors on DMA and report them via an external interrupt
|
||
|
|
(for possible device driver recovery) or retry the operation. Since
|
||
|
|
system state has not been lost, reporting these errors via a machine
|
||
|
|
check to the CPUs is inappropriate. Some devices or device drivers may
|
||
|
|
cause a catastrophic error. Systems which wish to recover from these
|
||
|
|
types of errors should choose devices and device drivers which are
|
||
|
|
designed to handle them correctly.</para>
|
||
|
|
|
||
|
|
</section>
|
||
|
|
|
||
|
|
</section>
|