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@ -6824,8 +6824,19 @@
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<para>For LSIs, the platform shall adhere to the
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<xref linkend="dbdoclet.50569387_67880" /> interrupt structure OF
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representation.</para>
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<section>
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<para>PAPR may support one of two generations of interrupt controllers with
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backward compatible firmware interfaces. The first generation interrupt
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controller is represented per
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<xref linkend="sec_powerpc_external_interrupt_controller_nodes" />
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and its sub sections.
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The second generation, External Interrupt Virtualization Engine is
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represented either per
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<xref linkend="sec_powerpc_external_interrupt_controller_nodes" />
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when operated in Legacy Compatibility mode, or per
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<xref linkend="sec_powerpc_external_interrupt_virtualization_engine_node" />
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and its sub sections when operated in Exploitation mode.</para>
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<section xml:id="sec_powerpc_external_interrupt_controller_nodes">
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<title>PowerPC External Interrupt Controller Nodes</title>
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<para>This section describes the properties for the PowerPC External
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@ -7177,6 +7188,130 @@
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</section>
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<section xml:id="sec_powerpc_external_interrupt_virtualization_engine_node">
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<title>PowerPC External Interrupt Virtualization Engine Nodes</title>
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<para>This section describes the properties for the External Interrupt Virtualization
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node. Interrupt controllers are normally packaged inside system chips, however,
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they are logically represented in the device tree by the interrupt controller
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node. This node reports the logical real addresses through which the client
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program can manage the interrupt context for its physical processor thread.</para>
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<para>Event source resources consist of either a single or pair of page addresses
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associated with each individual event source that is allocated to the partition.
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These addresses do not appear in the device tree; rather the platform provides
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the hcall(), H_INT_GET_SOURCE_INFO.</para>
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<para>At a dynamic reconfiguration event, such as adding or removing an IO adapter,
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or processor, the associated
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<emphasis role="bold"><literal>“int”</literal></emphasis>
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property is added or removed from the partition
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configuration and along with it the associated page addresses.</para>
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<variablelist>
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<varlistentry>
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<term><emphasis role="bold"><literal>“name”</literal></emphasis> [S]</term>
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<listitem>
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<para>Standard
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<emphasis>property name</emphasis> that denotes a PowerPC External
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Interrupt Controller.</para>
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<para><emphasis>prop-encoded-array</emphasis>: A string, encoded as with
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<emphasis role="bold"><literal>encode-string</literal></emphasis>.</para>
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<para>The value of this string shall be
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<literal>“interrupt-controller”</literal>.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold"><literal>“device_type”</literal></emphasis> [S]</term>
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<listitem>
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<para>Standard
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<emphasis>property name</emphasis> that indicates an Interrupt
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Controller.</para>
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<para><emphasis>prop-encoded-array</emphasis>: A string, encoded as with
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<emphasis role="bold"><literal>encode-string</literal></emphasis>.</para>
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<para>The value of this property shall be
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<literal>“power-ivpe”</literal>.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold"><literal>“reg”</literal></emphasis> [S]</term>
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<listitem>
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<para>Standard
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<emphasis>property name</emphasis> to define the base logical addresses
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and sizes of the registers for managing the interrupt context of a
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physical processor thread</para>
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<para>
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<emphasis>prop-encoded-array</emphasis>: Two
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(<emphasis>encode-phys, endcode-int</emphasis>)
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pairs. The entries represent the user and OS level views of the
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XIVE physical processor thread interrupt management areas respectively
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(“TIMA” addresses). The first of the two entries is the base address and
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size of the user level view and the second of the two entries is the
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base address and size of the OS level view.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold"><literal>“compatible”</literal></emphasis> [S]</term>
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<listitem>
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<para>Standard
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<emphasis>property name</emphasis> to define alternate
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<emphasis role="bold"><literal>“name”</literal></emphasis> property values.</para>
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<para>
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<emphasis>prop-encoded-array</emphasis>: The concatenation, with
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<emphasis role="bold"><literal>encode+</literal></emphasis>, of an arbitrary number of text strings,
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each encoded as with
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<emphasis role="bold"><literal>encode-string</literal></emphasis>.</para>
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<para>The property value shall include
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<emphasis role="bold"><literal>“ibm,power-ivpe”</literal></emphasis>.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold"><literal>“ibm,xive_eq-sizes”</literal></emphasis></term>
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<listitem>
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<para><emphasis>property name</emphasis>: Defines the sizes of event
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queues that are supported by for the XIVE option.</para>
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<para>
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<emphasis>prop-encoded-value</emphasis>: One to N integers, encoded as with
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<emphasis role="bold"><literal>encode-int</literal></emphasis>.</para>
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<para>Each integer is expressed as the power of 2 of the event queue size.
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For example, a 4K event queue size is represented by the value of 12
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(4K = 2<superscript>12</superscript>). The integers are arranged in ascending order.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold"><literal>“ibm,xive-lisn-ranges”</literal></emphasis></term>
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<listitem>
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<para><emphasis>property name:</emphasis> Defines the LISN ranges assigned
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to the client program.</para>
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<para><emphasis>prop-encoded-array</emphasis>: One or more
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(<emphasis>LISN, number</emphasis>) pairs, where LISN is a single cell
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hexadecimal value between 0x00000000 and 0x7FFFFFFF, and number is an
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integer. Each pair represents a contiguous range of LISNs. These LISNs
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can be used by the OS for any purpose (eg IPIs). The first range will
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contain at least one per possible thread in the partition.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold"><literal>“interrupt-controller”</literal></emphasis> [S]</term>
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<listitem>
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<para>Standard
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<emphasis>property name</emphasis> to indicate an interrupt (sub-)tree
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root.</para>
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<para><emphasis>prop-encoded-array</emphasis>: <none> The presence of
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this property indicates that this node represents an interrupt
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controller.</para>
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</listitem>
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</varlistentry>
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</variablelist>
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</section>
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</section>
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<section>
|
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