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47 KiB
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<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright (c) 2016, 2020 OpenPOWER Foundation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<appendix xmlns="http://docbook.org/ns/docbook"
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xmlns:xi="http://www.w3.org/2001/XInclude"
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xmlns:xlink="http://www.w3.org/1999/xlink"
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version="5.0"
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xml:id="dbdoclet.50569388_37308">
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<?dbhtml stop-chunking?>
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<title>Glossary</title>
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<para>This glossary contains an alphabetical list of terms, phrases, and abbreviations used in this document. </para>
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<variablelist>
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<varlistentry>
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<term><emphasis role="bold">Term</emphasis></term>
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<listitem><para><emphasis role="bold">Definition</emphasis></para></listitem>
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</varlistentry>
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<varlistentry>
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<term>AC</term>
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<listitem><para>Alternating current</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>ACR </term>
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<listitem><para>Architecture Change Request</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>AD</term>
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<listitem><para>Address Data line</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>Adapter</term>
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<listitem><para>A device which attaches a device to a bus or which converts one
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bus to another; for example, an I/O Adapter (IOA), a PCI Host Bridge (PHB),
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or a NUMA fabric attachment device.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term>addr</term>
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<listitem><para>Address</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>Architecture</term>
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<listitem><para>The hardware/software interface definition or software module to
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software module interface definition.</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>ASCII</term>
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<listitem><para>American National Standards Code for Information
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Interchange</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>ASR</term>
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<listitem><para>Address Space Register</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BAT</term>
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<listitem><para>Block Address Translation</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BE</term>
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<listitem><para>Big-Endian or Branch Trace Enable bit in the
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MSR (MSR<subscript>BE</subscript>)</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BIO</term>
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<listitem><para>Bottom of Peripheral Input/Output Space </para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BIOS</term>
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<listitem><para>Basic Input/Output system</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BIST</term>
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<listitem><para>Built in Self Test</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>Boundedly undefined</term>
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<listitem><para>Describes some addresses and registers which when referenced provide
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one of a small set of predefined results.</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BPA</term>
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<listitem><para>Bulk Power Assembly. Refers to components used for power distribution
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from a central point in the rack.</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BPM</term>
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<listitem><para>Bottom of Peripheral Memory</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BSCA</term>
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<listitem><para>Bottom of System Control Area</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BSM</term>
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<listitem><para>Bottom of System Memory</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>BUID</term>
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<listitem><para>Bus Unit Identifier. The high-order part of an interrupt source number
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which is used for hardware routing purposes by the platform.</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>CCIN</term>
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<listitem><para>Custom Card Identification Number</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>CD-ROM</term>
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<listitem><para>Compact Disk Read-Only Memory</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>CIS</term>
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<listitem><para>Client Interface Service</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>CMO</term>
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<listitem><para>Cooperative Memory Over-commitment option. See
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<xref linkend="dbdoclet.50569344_44716"/> for more information.</para>
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<!-- TODO: Use local reference in Virtualization document -->
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<!-- xref linkend="dbdoclet.50569344_44716"/> for more information.</para>--></listitem>
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</varlistentry>
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<varlistentry>
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<term>CMOS</term>
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<listitem><para>Complimentary Metal Oxide Semiconductor</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>Conventional PCI</term>
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<listitem><para>Behavior or features that conform to <xref linkend="dbdoclet.50569387_65468"/>.</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>CPU</term>
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<listitem><para>Central Processing Unit</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>CR</term>
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<listitem><para>Condition Register</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>CTR</term>
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<listitem><para>Count Register</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DABR</term>
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<listitem><para>Data Address Breakpoint Register</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DAR</term>
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<listitem><para>Data Address Register</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DASD</term>
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<listitem><para>Direct Access Storage Device (a synonym for “hard disk”)</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DBAT</term>
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<listitem><para>Data Block Address Translation</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DC</term>
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<listitem><para>Direct current</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DEC</term>
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|
<listitem><para>Decrementer</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DIMM</term>
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<listitem><para>Dual In-line Memory Module</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DMA</term>
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<listitem><para>Direct Memory Access</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DMA Read</term>
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<listitem><para>A data transfer from System Memory to I/O. A DMA Read Request
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is the inbound operation and the DMA Read Reply (or Read Completion) is the
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outbound data coming back from a DMA Read Request.</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DMA Write</term>
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|
<listitem><para>A data transfer to System Memory from I/O or a Message Signalled Interrupt (MSI) DMA Write. This is an inbound operation.</para></listitem>
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</varlistentry>
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<varlistentry>
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|
<term>DOS</term>
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|
<listitem><para>Disk OS</para></listitem>
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</varlistentry>
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|
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<varlistentry>
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|
<term>DR</term>
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|
<listitem><para>Data Relocate bit in MSR (MSR<subscript>DR</subscript>)</para></listitem>
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</varlistentry>
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<varlistentry>
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|
<term>DRA</term>
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|
<listitem><para>Deviation Risk Assessment</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DRAM</term>
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|
<listitem><para>Dynamic Random Access Memory</para></listitem>
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</varlistentry>
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<varlistentry>
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|
<term>DRC</term>
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|
<listitem><para>Delayed Read Completion. A transaction that has completed
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on the destination bus and is now moving toward the originating bus to complete.</para>
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<para>DR Connector.</para></listitem>
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</varlistentry>
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<varlistentry>
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|
<term>DR entity</term>
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|
<listitem><para>An entity that can participate in DR operations. That is, an entity
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that can be added or removed from the platform while the platform power is on and the
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system remains operational.</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DRR</term>
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<listitem><para>Delayed Read Request. A transaction that must complete on the destination bus before completing on the originating bus.</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>DSISR</term>
|
|
<listitem><para>Data Storage Interrupt Status Register</para></listitem>
|
|
</varlistentry>
|
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<varlistentry>
|
|
<term>DWR</term>
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<listitem><para>Delayed Write Request. A transaction that must complete on the destination bus before completing on the originating bus.</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>EA</term>
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|
<listitem><para>Effective Address</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>EAR</term>
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|
<listitem><para>External Access Register</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>ECC</term>
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|
<listitem><para>Error Checking and Correction</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>EE</term>
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<listitem><para>External interrupt Enable bit in the MSR (MSR<subscript>EE</subscript>)</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>EEH</term>
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|
<listitem><para>Enhance I/O Error Handling</para></listitem>
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</varlistentry>
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<varlistentry>
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|
<term>EEPROM</term>
|
|
<listitem><para>Electrically Erasable Programmable Read Only Memory</para></listitem>
|
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</varlistentry>
|
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<varlistentry>
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<term>EPOW</term>
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|
<listitem><para>Environment and Power Warning</para></listitem>
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</varlistentry>
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<varlistentry>
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<term></term>
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|
<listitem><para>Error Log indicator An amber indicator that indicates that the user needs to
|
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look at the error log or problem determination procedures, in order to determine the cause.
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Previously called System Information (Attention).</para></listitem>
|
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</varlistentry>
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<varlistentry>
|
|
<term>FCode</term>
|
|
<listitem><para>A computer programming language defined by the OF standard which is semantically
|
|
similar to the Forth programming language, but is encoded as a sequence of binary byte codes
|
|
representing a defined set of Forth words.</para></listitem>
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</varlistentry>
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<varlistentry>
|
|
<term>FE0</term>
|
|
<listitem><para>Floating-point Exception mode 0 bit in the MSR (MSR<subscript>FE0</subscript>)</para></listitem>
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</varlistentry>
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<varlistentry>
|
|
<term>FE1</term>
|
|
<listitem><para>Floating-point Exception mode 1bit in the MSR (MSR<subscript>FE1</subscript>)</para></listitem>
|
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</varlistentry>
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<varlistentry>
|
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<term>FIR</term>
|
|
<listitem><para>Fault Isolation Registers</para></listitem>
|
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</varlistentry>
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<varlistentry>
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<term>FLR</term>
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<listitem><para>Function Level Reset (see PCI Express documentation). An optional reset for PCI Express
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functions that allows resetting a single function of a multi-function IOA.</para></listitem>
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</varlistentry>
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<varlistentry>
|
|
<term>FP</term>
|
|
<listitem><para>Floating-Point available bit in the MSR (MSR<subscript>FP</subscript>)</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>FPSCR</term>
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<listitem><para>Floating-Point Status And Control Register</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>FRU</term>
|
|
<listitem><para>Field Replaceable Unit</para></listitem>
|
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</varlistentry>
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<varlistentry>
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<term>FSM</term>
|
|
<listitem><para>Finite State Machine</para></listitem>
|
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</varlistentry>
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<varlistentry>
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<term>GB</term>
|
|
<listitem><para>Gigabytes - as used in this document it is 2 raised to the power of 30</para></listitem>
|
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</varlistentry>
|
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<varlistentry>
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<term>HB</term>
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<listitem><para>Host Bridge</para></listitem>
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</varlistentry>
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<varlistentry>
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<term>HMC</term>
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<listitem><para>Hardware Management Console - used generically to refer to the system
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component that performs platform administration function where ever physically located.
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The HMC is outside of this architecture and may be implemented in multiple ways.
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Examples include: a special HMC applications in another system, an external appliance,
|
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or in an LPAR partition using the Virtual Management Channel (VMC) interface to the
|
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hypervisor. </para></listitem>
|
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</varlistentry>
|
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<varlistentry>
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<term>Hz</term>
|
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<listitem><para>Hertz</para></listitem>
|
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</varlistentry>
|
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<varlistentry>
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<term>IBAT</term>
|
|
<listitem><para>Instruction block address translation</para></listitem>
|
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</varlistentry>
|
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<varlistentry>
|
|
<term>ID</term>
|
|
<listitem><para>Identification</para></listitem>
|
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</varlistentry>
|
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|
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<varlistentry>
|
|
<term>IDE</term>
|
|
<listitem><para>Integrated Device Electronics</para></listitem>
|
|
</varlistentry>
|
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|
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<varlistentry>
|
|
<term>IDU</term>
|
|
<listitem><para>Interrupt Delivery Unit</para></listitem>
|
|
</varlistentry>
|
|
|
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<varlistentry>
|
|
<term>IEEE</term>
|
|
<listitem><para>Institute of Electrical and Electronics Engineers</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>I<superscript>2</superscript>C</term>
|
|
<listitem><para>Inter Integrated-circuit Communications</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>I/O </term>
|
|
<listitem><para>nput/Output</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>I/O bus master</term>
|
|
<listitem><para>Any entity other than a processor, cache,
|
|
memory controller, or host bridge which supplies both address and data in
|
|
write transactions or supplies the address and is the sink for the data in
|
|
read transactions.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>I/O device</term>
|
|
<listitem><para>Generally refers to any entity that is connected
|
|
to an IOA (usually through a cable), but in some cases may refer to the IOA
|
|
itself (that is, a device in the device tree that happens to be used for I/O
|
|
operations).</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>I/O Drawer</term>
|
|
<listitem><para>An enclosure in a rack that holds at least one PHB and at
|
|
least one IOA.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>ILE</term>
|
|
<listitem><para>Interrupt Little-Endian bit in MSR (MSR<subscript>ILE</subscript>)</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Instr</term>
|
|
<listitem><para>Instruction</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Interrupt Number</term>
|
|
<listitem><para>See Interrupt Vector below.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Interrupt Vector</term>
|
|
<listitem><para>The identifier associated with a specific interrupt source.
|
|
The identifier’s value is loaded into the source’s Interrupt Vector Register and
|
|
is read from the Interrupt Delivery Unit’s Interrupt Acknowledge Register.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>IOA</term>
|
|
<listitem><para>I/O Adapter. A device which attaches to a physical bus which is capable
|
|
of supporting I/O (a physical IOA) or logical bus (a virtual IOA). The term “IOA”
|
|
without the usage of the qualifier “physical” or “virtual” will be
|
|
used to designate a physical IOA. Virtual IOAs are defined further in
|
|
<xref linkend="dbdoclet.50569348_71217"/>.
|
|
In PCI terms, an IOA may be defined by a unique combination of its assigned
|
|
bus number and device number, but not necessarily including its function number.
|
|
That is, an IOA may be a single or multi-function device, unless otherwise specified by
|
|
the context of the text. In the context of a PCIe I/O Virtualized (IOV) device (not to be
|
|
confused with a virtual IOA), an IOA is a single or multiple function device (for example, a
|
|
PCIe Virtual Function (VF) or multiple VFs). An IOA function may or may not have its own set of
|
|
resources, that is may or may not be in its own Partitionable Endpoint (PE) domain
|
|
(see also
|
|
<xref linkend="dbdoclet.50569330_34831"/>).</para>
|
|
</listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>IOA function</term>
|
|
<listitem><para>That part of an IOA that deals with a specific part of the
|
|
IOA as defined by the configuration space “Function” part of Bus/Device/Function.
|
|
For single-function IOAs, the IOA Function and the IOA are synonymous.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>IP</term>
|
|
<listitem><para>Interrupt Prefix bit in MSR (MSR<subscript>IP</subscript>)</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>IPI</term>
|
|
<listitem><para>Interprocessor Interrupt</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>IR</term>
|
|
<listitem><para>Instruction Relocate bit in MSR register (MSR<subscript>IR</subscript>) or infrared</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>ISF</term>
|
|
<listitem><para>Interrupt 64-bit processor mode bit in the MSR (MSR<subscript>ISF</subscript>)</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>ISO</term>
|
|
<listitem><para>International Standards Organization</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>ISR</term>
|
|
<listitem><para>Interrupt Source Register</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>ISU</term>
|
|
<listitem><para>Interrupt Source Unit</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>KB</term>
|
|
<listitem><para>Kilobytes - as used in this document it is 2 raised to the power of 10</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>KHz</term>
|
|
<listitem><para>Kilo Hertz</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LAN</term>
|
|
<listitem><para>Local Area Network</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LCD</term>
|
|
<listitem><para>Liquid Crystal Display</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LE</term>
|
|
<listitem><para>Little-Endian bit in MSR (MSR<subscript>LE</subscript>) or Little-Endian</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LED</term>
|
|
<listitem><para>Light Emitting Diode</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LMB</term>
|
|
<listitem><para>Logical Memory Block. The Block of logical memory addresses associated with a dynamically
|
|
reconfigurable memory node.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Load</term>
|
|
<listitem><para> A <emphasis>Load</emphasis> Request is the outbound (from the processor) operation
|
|
and the <emphasis> Load</emphasis> Reply is the inbound data coming back from a
|
|
<emphasis>Load</emphasis> Request. When it relates to I/O operations, this is an
|
|
MMIO <emphasis>Load</emphasis> . </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LR</term>
|
|
<listitem><para>Link Register</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LSb</term>
|
|
<listitem><para>Least Significant bit</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LSB</term>
|
|
<listitem><para>Least Significant Byte</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LSI</term>
|
|
<listitem><para>Level Sensitive Interrupt</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LUN</term>
|
|
<listitem><para>Logical Unit Number</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>L1</term>
|
|
<listitem><para>Primary cache</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>L2</term>
|
|
<listitem><para>Secondary cache</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MB</term>
|
|
<listitem><para>Megabytes - as used in this document it is 2 raised to the power of 20</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>ME</term>
|
|
<listitem><para>Machine check Enable</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MMIO</term>
|
|
<listitem><para>Memory Mapped I/O. This refers to the mapping of the address space required
|
|
by an I/O device for <emphasis>Load</emphasis> or <emphasis>Store</emphasis> operations into
|
|
the system’s address space.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MES</term>
|
|
<listitem><para>Miscellaneous Equipment Specification</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MFM</term>
|
|
<listitem><para>Modified frequency modulation</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MHz</term>
|
|
<listitem><para>Mega Hertz</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MOD</term>
|
|
<listitem><para>Address modification bit in the MSR
|
|
(MSR<subscript>MOD</subscript>)</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MP</term>
|
|
<listitem><para>Multiprocessor</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MSb</term>
|
|
<listitem><para>Most Significant bit</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MSB</term>
|
|
<listitem><para>Most Significant Byte</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MSI</term>
|
|
<listitem><para>Message Signalled Interrupt</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MSR</term>
|
|
<listitem><para>Machine State Register</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>MTT </term>
|
|
<listitem><para>Multi-TCE-Table option. See
|
|
<xref linkend="dbdoclet.50569344_50921"/>.</para>
|
|
</listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>N/A</term>
|
|
<listitem><para>Not Applicable</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Nibble</term>
|
|
<listitem><para>Refers to the first or last four bits in an 8 bit byte</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>NUMA</term>
|
|
<listitem><para>Non-Uniform Memory Access</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>NUMA fabric</term>
|
|
<listitem><para>Mechanism and method for connecting the multiple nodes of a NUMA system</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>NVRAM</term>
|
|
<listitem><para>Nonvolatile Random Access Memory</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>OF</term>
|
|
<listitem><para>Open Firmware</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>OP</term>
|
|
<listitem><para>Operator </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>OS</term>
|
|
<listitem><para>Operating System</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>OUI</term>
|
|
<listitem><para>Organizationally Unique Identifier</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PA</term>
|
|
<listitem><para>Processor Architecture</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PAP</term>
|
|
<listitem><para>Privileged Access Password</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>LoPAR</term>
|
|
<listitem><para> Used within the Linux on Power Architecture
|
|
Reference documents to denote: (1) the architectural requirements specified
|
|
by the Linux on Power Architecture Reference document, (2) the Linux on Power Architecture
|
|
Reference documents themself, and (3) as an adjective to qualify an entity as being
|
|
related to this architecture.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Partitionable Endpoint</term>
|
|
<listitem><para>This refers to the I/O granule that may be treated as one for
|
|
purposes of assignment to an OS (for example, to an LPAR partition). May be an
|
|
I/O adapter (IOA), or groups of IOAs and bridges, or portions of IOAs. PE granularity
|
|
supported by the hardware may be finer than is supported by the firmware. Grouping
|
|
of multiple PEs into one DR entity may limit assignment of a the separate PEs to different
|
|
LPAR partitions. See also DR entity.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PC</term>
|
|
<listitem><para>Personal Computer</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PCI</term>
|
|
<listitem><para>Peripheral Component Interconnect. An all-encompassing term referring to
|
|
conventional PCI, PCI-X, and PCI Express.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PCI bus</term>
|
|
<listitem><para>A general term referring to either the PCI Local Bus, as
|
|
specified in <xref linkend="dbdoclet.50569387_65468"/> and <xref linkend="dbdoclet.50569387_26550"/>
|
|
for conventional PCI and PCI-X, or a PCI Express link, as specified in
|
|
<xref linkend="dbdoclet.50569387_66784"/> for PCI Express.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PCI Express</term>
|
|
<listitem><para>Behavior or features that conform to
|
|
<xref linkend="dbdoclet.50569387_66784"/>.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PCI link</term>
|
|
<listitem><para>A PCI Express link, as specified in <xref linkend="dbdoclet.50569387_66784"/>.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PCI-X</term>
|
|
<listitem><para>Behavior or features that conform to <xref linkend="dbdoclet.50569387_26550"/>.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PD</term>
|
|
<listitem><para>Presence Detect</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PE</term>
|
|
<listitem><para>When referring to the body of the LoPAR, this refers to a Partitionable
|
|
Endpoint.</para>
|
|
<para>PE has a different meaning relative to
|
|
<xref linkend="dbdoclet.50569368_91814"/>
|
|
(see
|
|
<xref linkend="sec_papr_binding_terms"/> for that definition).</para>
|
|
</listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PEM</term>
|
|
<listitem><para>Partition Energy Management option. See
|
|
<xref linkend="dbdoclet.50569344_18587"/>.</para>
|
|
</listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Peripheral I/O Space</term>
|
|
<listitem><para>The range of real addresses which are assigned
|
|
to the I/O Space of a Host Bridge (HB) and which are sufficient to contain all of
|
|
the Load and Store address space requirements of all the devices in the I/O Space
|
|
of the I/O bus that is generated by the HB. A keyboard controller is an example of
|
|
a device which may require Peripheral I/O Space addresses. </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Peripheral Memory Space</term>
|
|
<listitem><para>The range of real addresses which are assigned to the Memory
|
|
Space of a Host Bridge (HB) and which are sufficient to contain all of the Load and
|
|
Store address space requirements of the devices in the Memory Space of the I/O bus
|
|
that is generated by the HB. The frame buffer of a graphics adapter is an example
|
|
of a device which may require Peripheral Memory Space addresses. </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Peripheral Space</term>
|
|
<listitem><para>Refers to the physical address space which may
|
|
be accessed by a processor, but which is controlled by a host bridge. At least one
|
|
peripheral space must be present and it is referred to by the suffix 0. A host bridge
|
|
will typically provide access to at least a memory space and possibly to an I/O
|
|
space.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PHB</term>
|
|
<listitem><para>PCI Host Bridge</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PIC</term>
|
|
<listitem><para>Programmable Interrupt Controller</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PIR</term>
|
|
<listitem><para>Processor Identification Register </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Platform</term>
|
|
<listitem><para>Refers to the hardware plus firmware portion of a system composed of hardware,
|
|
firmware, and OS.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Platform firmware</term>
|
|
<listitem><para>Refers to all firmware on a system including the software or firmware in a
|
|
support processor.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Plug-in I/O card</term>
|
|
<listitem><para>A card which can be plugged into an I/O
|
|
connector in a platform and which contains one or more IOAs and potentially
|
|
one or more I/O bridges or switches.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Plug-in Card</term>
|
|
<listitem><para>An entity that plugs into a physical slot.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PMW</term>
|
|
<listitem><para>Posted memory write. A transaction that has complete on the
|
|
originating bus before completing on the destination bus</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PnP</term>
|
|
<listitem><para>Plug and Play</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>POP</term>
|
|
<listitem><para>Power On Password</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>POST</term>
|
|
<listitem><para>Power-On Self Test</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PR</term>
|
|
<listitem><para>Privileged bit in the MSR (MSR<subscript>PR</subscript>)</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Processor Architecture</term>
|
|
<listitem><para>Used throughout this document to
|
|
mean compliance with the requirements specified in
|
|
<xref linkend="dbdoclet.50569387_99718"/>.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Processor revision number</term>
|
|
<listitem><para> A 16-bit number that distinguishes between various releases
|
|
of a particular processor version, for example different engineering change
|
|
levels.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PVN</term>
|
|
<listitem><para>Processor Version Number. Uniquely determines the particular
|
|
processor and PA version.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>PVR</term>
|
|
<listitem><para>Processor Version Register. A register in each processor
|
|
that identifies its type. The contents of the PVR include the processor
|
|
version number and processor revision number.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>RAID</term>
|
|
<listitem><para>Redundant Array of Independent Disks</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>RAM</term>
|
|
<listitem><para>Random Access Memory</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>RAS</term>
|
|
<listitem><para>Reliability, Availability, and Serviceability</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Real address</term>
|
|
<listitem><para>A real address results from doing address
|
|
translation on an effective address when address translation is enabled.
|
|
If address translation is not enabled, the real address is the same as the
|
|
effective address. An attempt to fetch from, load from, or store to a real
|
|
address that is not physically present in the machine may result in a
|
|
machine check interrupt.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Reserved</term>
|
|
<listitem><para>The term “reserved” is used within this
|
|
document to refer to bits in registers or areas in the address space
|
|
which should not be referenced by software except as described in this
|
|
document. </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Reserved for firmware use</term>
|
|
<listitem><para> Refers to a given location or bit which may not be used by
|
|
software, but are used by firmware.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Reserved for future use</term>
|
|
<listitem><para>Refers to areas of address space or bits in registers which may be
|
|
used by future versions of this architecture.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>RI</term>
|
|
<listitem><para>Recoverable interrupt bit in the MSR (MSR<subscript>RI</subscript>)</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>RISC</term>
|
|
<listitem><para>Reduced Instruction Set Computing</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>RMA</term>
|
|
<listitem><para>Real Mode Area. The first block of logical memory addresses
|
|
owned by a logical partition, containing the storage that may be accessed with
|
|
translate off.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>ROM</term>
|
|
<listitem><para>Read Only Memory</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Root Complex</term>
|
|
<listitem><para>A PCI Express root complex as specified in
|
|
<xref linkend="dbdoclet.50569387_66784"/>.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>RPN</term>
|
|
<listitem><para>Real Page Number</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>RTAS</term>
|
|
<listitem><para>Run-Time Abstraction Services</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>RTC</term>
|
|
<listitem><para>Real Time Clock</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SAE</term>
|
|
<listitem><para>Log Service Action Event log</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SCC</term>
|
|
<listitem><para>Serial Communications Controller</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SCSI</term>
|
|
<listitem><para>Small Computer System Interface</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SE</term>
|
|
<listitem><para>Single-step trace enabled bit in the MSR
|
|
(MSR<subscript>SE</subscript>)</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Service Focal Point</term>
|
|
<listitem><para>The common point of control in the system for handling all
|
|
service actions</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Serviceable Event</term>
|
|
<listitem><para>Serviceable Events are platform,
|
|
global, regional and local error events that require a service action
|
|
and possibly a call home when the serviceable event must be handled by a
|
|
service representative or at least reported to the service provider.
|
|
Activation of the Error Log indicator notifies the customer of the event
|
|
and the event indicates to the customer that there must be some intervention
|
|
to rectify the problem. The intervention may be a service action that the
|
|
customer can perform or it may require a service provider.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SES</term>
|
|
<listitem><para>Storage Enclosure Services (can also mean SCSI Enclosure
|
|
Services in relation to SCSI storage)</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SF</term>
|
|
<listitem><para>Processor 32-bit or 64-bit processor mode bit in the MSR
|
|
(MSR<subscript>SF</subscript>)</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SFP</term>
|
|
<listitem><para>Service Focal Point</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Shrink-wrap OS</term>
|
|
<listitem><para>A single version of an OS that runs on all
|
|
compliant platforms. </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Shrink-wrap Application</term>
|
|
<listitem><para> A single version of an application program
|
|
that runs on all compliant platforms with the applicable OS.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SMP</term>
|
|
<listitem><para>Symmetric multiprocessor</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SMS</term>
|
|
<listitem><para>System Management Services</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Snarf</term>
|
|
<listitem><para>An industry colloquialism for cache-to-cache
|
|
transfer. A typical scenario is as follows: (1) cache miss from cache A,
|
|
(2) line found modified in cache B, (3) cache B performs castout of modified
|
|
line, and (4) cache A allocates the modified line as it is being written back
|
|
to memory. </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Snoop</term>
|
|
<listitem><para>The act of interrogating a cache for the presence of a
|
|
line, usually in response to another party on a shared bus attempting to
|
|
allocate that line.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SPRG</term>
|
|
<listitem><para>Special Purpose Registers for General use</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SR</term>
|
|
<listitem><para>System Registers</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SRC</term>
|
|
<listitem><para>Service Reference Code</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>SRN</term>
|
|
<listitem><para>Service Request Number</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>Store</term>
|
|
<listitem><para>A <emphasis> Store</emphasis> Request is an
|
|
outbound (from the processor) operation. When it relates to I/O
|
|
operations, this is an MMIO <emphasis>Store</emphasis>. </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>System</term>
|
|
<listitem><para>Refers to the collection of hardware, system firmware,
|
|
and OS software which comprise a computer model.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>System address space</term>
|
|
<listitem><para>The total range of addressability as established by the
|
|
processor implementation.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>System Control Area</term>
|
|
<listitem><para>Refers to a range of addresses which
|
|
contains the system ROM(s) and an unarchitected, reserved, platform-dependent
|
|
area used by firmware and Run-Time Abstraction services for control of the
|
|
platform. The ROM areas are defined by the OF properties in the
|
|
<emphasis>openprom</emphasis> and <emphasis> os-rom</emphasis> nodes
|
|
of the OF device tree.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>System Information (Attention) indicator</term>
|
|
<listitem><para>See Error Log indicator.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>System firmware</term>
|
|
<listitem><para>Refers to the collection of all firmware on a system
|
|
including OF, RTAS and any legacy firmware.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>System Memory</term>
|
|
<listitem><para>Refers to those areas of memory which form
|
|
a coherency domain with respect to the PA processor or processors that
|
|
execute application software on a system.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>System software</term>
|
|
<listitem><para>Refers to the combination of OS software,
|
|
device driver software, and any hardware abstraction software, but
|
|
excludes the application software.</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>TB</term>
|
|
<listitem><para>Time Base</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>TCE</term>
|
|
<listitem><para>Translation Control Entry</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>TLB</term>
|
|
<listitem><para>Translation Look-aside Buffer</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>TOD</term>
|
|
<listitem><para>Time Of Day </para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>TOSM</term>
|
|
<listitem><para>Top of system memory</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>TPM</term>
|
|
<listitem><para>Top of Peripheral Memory</para>
|
|
<para>Trusted Platform Module</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>tty</term>
|
|
<listitem><para>Teletypewriter or ASCII character driven
|
|
terminal device</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>UI</term>
|
|
<listitem><para>User Interface</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>USB</term>
|
|
<listitem><para>Universal Serial Bus</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>v</term>
|
|
<listitem><para>Volt</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>VGA</term>
|
|
<listitem><para>Video Graphics Array</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>VMC</term>
|
|
<listitem><para>Virtual Management Channel</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>VPD</term>
|
|
<listitem><para>Vital Product Data</para></listitem>
|
|
</varlistentry>
|
|
|
|
<varlistentry>
|
|
<term>VPNH</term>
|
|
<listitem><para>Virtual Processor Home Node option. See
|
|
<xref linkend="dbdoclet.50569344_56450"/>.</para>
|
|
</listitem>
|
|
</varlistentry>
|
|
</variablelist>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</appendix>
|