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149 lines
8.6 KiB
XML
149 lines
8.6 KiB
XML
<?xml version="1.0"?>
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<chapter xmlns="http://docbook.org/ns/docbook"
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xmlns:xl="http://www.w3.org/1999/xlink"
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xml:id="dbdoclet.50569326_38341"
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version="5.0"
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xml:lang="en">
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<title>Introduction</title>
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<para>This architecture specification provides a comprehensive computer
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system platform-to-software interface definition, combined with minimum system
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requirements, that enables the development of and software porting to a range
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of compatible industry-standard computer systems from workstations through
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servers. These systems are based on the requirements defined in
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<xref linkend="dbdoclet.50569387_99718"/><footnote xml:id="pgfId-1000323"><para>The
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term “Processor Architecture” (PA) is used throughout this
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document to mean compliance with the requirements specified in
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<xref linkend="dbdoclet.50569387_99718"/>.</para></footnote>. The definition supports
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the development of both uniprocessor and multiprocessor system
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implementations.</para>
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<para>A key attribute and benefit of this architecture is the ability of
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platform developers to have degrees of freedom of implementation below the
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level of architected interfaces and therefore have the opportunity for adding
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unique value. This flexibility is achieved through architecture facilities
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including: (1) device drivers; (2) Open Firmware (OF); (3)
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Run-Time Abstraction Services (RTAS);
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and (4) hardware abstraction layers. The role of items 1
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and 4 are described in separate operating system (OS) documentation. The role
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that items 2 and 3 play in this architecture will be described in subsequent
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paragraphs and chapters.</para>
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<para>This architecture combines leading-edge technologies to create a
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superior computing platform. By design, it supports a wide range of computing
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needs including personal productivity, engineering design, data management,
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information analysis, education, desktop publishing, multimedia, entertainment,
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and database, file, and application servers. This architecture effectively
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leverages industry-standard I/O through the PCI bus. Systems based on this
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architecture are expected to offer price/performance advantages and to address
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the expected growth in computing performance and functionality.</para>
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<para><emphasis role="bold">Architecture Note:</emphasis> In modern platforms, designers may choose
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between various PCI topology standards. This architecture uses the term
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“PCI” as a general term to describe the most recent versions of
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all forms of PCI standards including any approved Engineering Change Requests
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(ECRs) against them. In cases where there are significant differences between
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individual PCI standards, the following terminology is used to differentiate
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between the PCI standards.</para>
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<itemizedlist>
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<listitem>
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<para>The term “conventional PCI” refers to behavior or
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features that conform to the most recent version of the
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<xref linkend="dbdoclet.50569387_65468"/>, including any approved ECRs against it.
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</para>
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</listitem>
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<listitem>
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<para>The term “PCI-X” refers to behavior or features that
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conform to the most recent version of the
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<xref linkend="dbdoclet.50569387_26550"/>, including any approved ECRs against it.</para>
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</listitem>
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<listitem>
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<para>The term “PCI Express” refers to behavior or features
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that conform to the most recent version of the
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<xref linkend="dbdoclet.50569387_66784"/> including any approved ECRs against it. In
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addition, the terms “bus,” “bridge” and “PCI
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Host Bridge (PHB)” used in relation to “PCI” throughout
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this architecture may refer to a PCI Express “link,”
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“switch,” and “root complex” respectively.</para>
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</listitem>
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</itemizedlist>
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<section>
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<title>Platform Topology</title>
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<para>To the experienced computer designer and system manufacturer, much of
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the content of this architecture will be familiar. A typical desktop topology
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is shown in <xref linkend="dbdoclet.50569326_34945"/>. This topology consists
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of a single PA processor, volatile System Memory, and a single Host Bridge
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providing a PCI Bus. The PCI Bus provides for connection of I/O adapters
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(IOAs). See <xref linkend="dbdoclet.50569388_37308"/> for the definition of an
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IOA.</para>
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<para>A more complex general topology is shown in
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<xref linkend="dbdoclet.50569326_34945"/>. All platforms consist of one or more PA
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processors, a volatile System Memory separate from other subsystems, and a
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number of IOAs, which may initiate transactions to System Memory. The
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processors are linked over the primary processor bus/switch to each other, to
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the System Memory, and to one or more Host Bridges. In general, IOAs do not
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connect to the primary processor bus/switch. The Host Bridges connect to
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secondary buses which have IOAs connected to them. In turn, one or more bus
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bridges may be employed to tertiary buses (and beyond) with additional IOAs
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connected to them. Typically, the bus speeds and throughput decrease and the
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number of supportable loads increases as one progresses from the primary
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processor bus to more remote buses. </para>
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<para>There are variations on these topologies, which are likely to occur
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and are therefore worth describing below. This architecture describes
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interfaces, not implementation. The logical software model must remain the
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same, even if the physical topology is different.</para>
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<itemizedlist>
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<listitem>
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<para>In a smaller platform, the Host Bridge and/or the memory and/or an
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IOA may be integrated into a single chip. In this case, the topology would not
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look like <xref linkend="dbdoclet.50569326_34945"/> from a chip point of view,
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but instead would be integrated onto the single chip.</para>
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</listitem>
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<listitem>
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<para>In a larger platform, secondary buses may be implemented, with two
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or more Host Bridges, as two or more parallel expansion buses for performance
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reasons. Similarly, tertiary buses may be two or more parallel expansion buses
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off each secondary bus. This is indicated by the ellipses near the Host Bridge
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and the Bus Bridge.</para>
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</listitem>
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<listitem>
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<para>In a high performance platform, with multiple processors and
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multiple memoriea switch may be employed to allow multiple parallel accesses
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by the processors to memory. The path through the switches would be decided by
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the addressing of ths, a switch may be employed to allow multiple parallel accesses
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by the processors to memory. The path through the switches would be decided by
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the addressing of the memory.</para>
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</listitem>
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</itemizedlist>
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<para>Each of the following chapters provides information necessary to
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successfully implement compliant systems. It is recommended that the reader
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become thoroughly familiar with the contents of these chapters and their
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references prior to beginning system or software development. It is anticipated
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that standard chip sets will simplify the development of compliant
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implementations consistent with the topologies shown below and will be
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available from third-party industry sources.</para>
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<figure xml:id="dbdoclet.50569326_34945">
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<title>Typical Desktop Topology</title>
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<mediaobject>
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<imageobject role="html"><imagedata fileref="figures/PAPR-3.gif" format="GIF" scalefit="1"/></imageobject>
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<imageobject role="fo"><imagedata contentdepth="100%" fileref="figures/PAPR-3.gif" format="GIF" scalefit="1" width="100%"/></imageobject>
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</mediaobject>
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</figure>
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<figure xml:id="dbdoclet.50569326_34945.1">
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<title>General Platform Topology</title>
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<mediaobject>
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<imageobject role="html"><imagedata fileref="figures/PAPR-4.gif" format="GIF" scalefit="1"/></imageobject>
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<imageobject role="fo"><imagedata contentdepth="100%" fileref="figures/PAPR-4.gif" format="GIF" scalefit="1" width="100%"/></imageobject>
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</mediaobject>
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</figure>
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<para><emphasis role="bold">Note:</emphasis> To enable the implementation of a large number of I/O adapters in a large
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system, the Host Bridge may be split into two pieces -- a Hub and a Bridge --
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with the two connected by a cable, thus enabling the I/O adapters to be housed
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at a distance from the main processor enclosure.</para>
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</section>
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</chapter>
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