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175 lines
7.0 KiB
XML
175 lines
7.0 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright (c) 2016 OpenPOWER Foundation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<section xmlns="http://docbook.org/ns/docbook"
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xmlns:xi="http://www.w3.org/2001/XInclude"
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xmlns:xlink="http://www.w3.org/1999/xlink"
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version="5.0"
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xml:id="sec_pa_processor_binding_terms">
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<title>Terms</title>
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<para>This standard uses technical terms as they are defined in the
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IEEE Std 1275-1994 Standard and other
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documents cited in “References”, plus the following
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terms:</para>
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<variablelist>
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<varlistentry>
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<term><emphasis role="bold">core, core specification, core document</emphasis></term>
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<listitem>
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<para>Refers to IEEE Std 1275-1994 Standard for Boot (Initialization,
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Configuration) Firmware, Core Practices and Requirements</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">core errata</emphasis></term>
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<listitem>
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<para>Refers to Core Errata, IEEE P1275.7</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">effective address</emphasis></term>
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<listitem>
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<para>The 64- or 32-bit address computed by the processor
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when executing a Storage Access or Branch instruction, or when fetching the
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next sequential instruction. If address translation is disabled, the real
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address is the same as the effective address. If address translation is
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enabled, the real address is determined by, but not necessarily identical
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to, the effective address.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">linkage area</emphasis></term>
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<listitem>
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<para>An area within the stack that is reserved for saving
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certain registers across procedure calls in PA run-time models. This area
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is reserved by the caller and is allocated above the current stack pointer
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(<literal>%r1</literal>).</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">Open Firmware (OF)</emphasis></term>
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<listitem>
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<para>The firmware architecture defined by
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<xref linkend="dbdoclet.50569387_45524" /> and
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<xref linkend="dbdoclet.50569387_14175" />, or, when used as an adjective,
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a software component compliant with the core specification and
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errata.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">procedure descriptor</emphasis></term>
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<listitem>
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<para>A data structure used by some PA run-time models
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to represent a C “pointer to procedure”. The first word of this
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structure contains the actual address of the procedure.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">processor bus</emphasis></term>
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<listitem>
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<para>The bus that connects the CPU chip to the system.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">real address</emphasis></term>
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<listitem>
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<para>An address that the processor presents on the processor
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bus.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">real-mode</emphasis></term>
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<listitem>
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<para>The mode in which OF and its client are running with
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translation disabled; all addresses passed between the client and OF are
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real (i.e., hardware) addresses.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">segmented address translation</emphasis></term>
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<listitem>
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<para>The process whereby an Effective Address (EA) is translated into a
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Virtual Address (VA) and the virtual address is translated into a Real
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Address (RA). (see
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<xref linkend="dbdoclet.50569374_41703" />and Book III of
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<xref linkend="dbdoclet.50569387_99718" />for more detail.)</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">suspend</emphasis></term>
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<listitem>
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<para>A form of Power Management characterized by a fast recovery
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to full operation. Typically, system memory will not be powered off while
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in the suspend state.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">Table of Contents (TOC)</emphasis></term>
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<listitem>
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<para>A data structure used by some PA run-time models that is used for
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access to global variables and for inter-module linkage. When a TOC is
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used,
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<emphasis>%r2</emphasis> contains its base address.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">Virtual Address</emphasis></term>
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<listitem>
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<para>In IEEE 1275 parlance, the address that a program uses to access
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a memory location or
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memory-mapped device register. Depending on the presence or absence of
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memory mapping hardware in the system, and whether or not that mapping
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hardware is enabled, a virtual address may or may not be the same as the
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physical (real) address that appears on an external bus. The IEEE 1275
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definition of “virtual address” corresponds to The PA's
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definition of “effective address.” Except as noted, this
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document uses the IEEE 1275 definition of virtual address.</para>
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<para>In PA parlance, an internal address within the PA address
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translation mechanism, used
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as in intermediate term in the translation of an effective address to the
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corresponding real address.</para>
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</listitem>
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</varlistentry>
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<varlistentry>
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<term><emphasis role="bold">virtual-mode</emphasis></term>
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<listitem>
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<para>The mode in which OF and its client share a single
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virtual address space, and address translation is enabled; all addresses
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passed between the client and OF are virtual (translated) addresses.</para>
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</listitem>
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</varlistentry>
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</variablelist>
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</section>
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