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@ -141,14 +141,6 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
@@ -141,14 +141,6 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
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linkend="VR-VSR" />, there are 64 vector-scalar registers; each |
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is 128 bits wide. |
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</para> |
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<para> |
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The vector-scalar registers can be addressed with VSX |
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instructions, for vector and scalar processing of all 64 |
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registers, or with the "classic" Power floating-point |
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instructions to refer to a 32-register subset of these, having |
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64 bits per register. They can also be addressed with VMX |
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instructions to refer to a 32-register subset of 128-bit registers. |
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</para> |
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<figure pgwide="1" xml:id="FPR-VSR"> |
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<title>Floating-Point Registers as Part of VSRs</title> |
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<mediaobject> |
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@ -167,6 +159,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
@@ -167,6 +159,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
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</imageobject> |
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</mediaobject> |
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</figure> |
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<para> |
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The vector-scalar registers can be addressed with VSX |
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instructions, for vector and scalar processing of all 64 |
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registers, or with the "classic" Power floating-point |
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instructions to refer to a 32-register subset of these, having |
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64 bits per register. They can also be addressed with VMX |
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instructions to refer to a 32-register subset of 128-bit registers. |
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</para> |
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</section> |
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<section xml:id="VIPR.intro.reporting"> |
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