Clearly define the ISA or split the list in sections #3

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opened 6 years ago by lu-zero · 1 comments
lu-zero commented 6 years ago (Migrated from github.com)

Ideally would be great having something along the lines of:

Intrinsics name Possible Arguments Instruction it maps to Description ISA introducing it
vec_xxpermdi (a: s16x8, b: s16x8, c: s8x16) -> s16x8 vperm Permutes the bytes in the vectors a and b according to c VSX
Ideally would be great having something along the lines of: | Intrinsics name | Possible Arguments | Instruction it maps to | Description | ISA introducing it| | -------------: |:-------------| :-----:| :---: | :---: | | vec_xxpermdi | (a: s16x8, b: s16x8, c: s8x16) -> s16x8 | vperm | Permutes the bytes in the vectors **a** and **b** according to *c* | VSX |
ThinkOpenly commented 4 years ago (Migrated from github.com)

For "ISA introducing it", does "it" refer to the ISA level that introduced the "Intruction it maps to"? (I presume so...)
If so, then "VSX" is not as helpful as "v2.03" (for vperm), and that information is found in the Power Instruction Set Architecture Specification itself. Whether that information should be duplicated (and maintained) in both places is a question.
Note also that there is not necessarily a one-to-one mapping from intrinsics to instructions, given the type-based overloading.
Also, many intrinsics that have a "single instruction" implementation a recent ISA may have a "multiple instruction" implementation on earlier ISAs (there is nothing to preclude this).
We would need to be reasonably careful about what information is presented, and how it is to be interpreted.

For "ISA introducing it", does "it" refer to the ISA level that introduced the "Intruction it maps to"? (I presume so...) If so, then "VSX" is not as helpful as "v2.03" (for `vperm`), and that information is found in the _Power Instruction Set Architecture Specification_ itself. Whether that information should be duplicated (and maintained) in both places is a question. Note also that there is not necessarily a one-to-one mapping from intrinsics to instructions, given the type-based overloading. Also, many intrinsics that have a "single instruction" implementation a recent ISA may have a "multiple instruction" implementation on earlier ISAs (there is nothing to preclude this). We would need to be reasonably careful about what information is presented, and how it is to be interpreted.
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Reference: systemsoftware/Programming-Guides#3
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