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97 lines
3.2 KiB
VHDL
97 lines
3.2 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee; use ieee.std_logic_1164.all ;
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library support;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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use support.power_logic_pkg.all;
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ENTITY c_prism_csa42 IS
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GENERIC ( btr : string := "CSA42_A2_A12TH" );
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PORT(
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A : IN std_ulogic;
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B : IN std_ulogic;
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C : IN std_ulogic;
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D : IN std_ulogic;
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KI : IN std_ulogic;
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KO : OUT std_ulogic;
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CAR : OUT std_ulogic;
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SUM : OUT std_ulogic;
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vd : inout power_logic;
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gd : inout power_logic
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);
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-- synopsys translate_off
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ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa42 : entity is
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(
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1 => (" ","A ","SAME","PIN_BIT_SCALAR"),
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2 => (" ","B ","SAME","PIN_BIT_SCALAR"),
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3 => (" ","C ","SAME","PIN_BIT_SCALAR"),
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4 => (" ","D ","SAME","PIN_BIT_SCALAR"),
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5 => (" ","KI ","SAME","PIN_BIT_SCALAR"),
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6 => (" ","KO ","SAME","PIN_BIT_SCALAR"),
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7 => (" ","CAR ","SAME","PIN_BIT_SCALAR"),
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8 => (" ","SUM ","SAME","PIN_BIT_SCALAR"),
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9 => (" ","VDD ","SAME","PIN_BIT_SCALAR"),
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10 => (" ","VSS ","SAME","PIN_BIT_SCALAR")
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);
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-- synopsys translate_on
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END c_prism_csa42;
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ARCHITECTURE c_prism_csa42 OF c_prism_csa42 IS
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signal s1 : std_ulogic;
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BEGIN
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s1 <= b XOR c XOR d ;
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sum <= s1 XOR a XOR ki;
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car <= (s1 AND a ) OR
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(s1 AND ki) OR
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(a AND ki);
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ko <= (b AND c ) OR
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(b AND d ) OR
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(c AND d );
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END;
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