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wtf 1 year ago
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  1. 20
      rel/build/a2x/a2x_impl_step.tcl
  2. 24
      rel/build/a2x/bd/hdl/a2x_axi_bd_wrapper.v
  3. 1975
      rel/build/a2x/create_a2x_project.tcl
  4. 50
      rel/build/a2x/fixup_a2x_bd.tcl
  5. 58
      rel/build/a2x/ila_axi.tcl
  6. 31
      rel/build/a2x/readme.md
  7. 1
      rel/build/a2x/xdc
  8. 5113
      rel/build/ip_user/a2x_axi/a2x_axi/component.xml
  9. 154
      rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux16.vhdl
  10. 184
      rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux32.vhdl
  11. 131
      rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux4.vhdl
  12. 139
      rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux8.vhdl
  13. 146
      rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_event_mux.vhdl
  14. 97
      rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_bthmx.vhdl
  15. 82
      rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa32.vhdl
  16. 96
      rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa42.vhdl
  17. 70
      rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_scom_addr_decode.vhdl
  18. 11616
      rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_ao_support.vhdl
  19. 5179
      rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_function_support.vhdl
  20. 1545
      rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_mux_support.vhdl
  21. 2694
      rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_support.vhdl
  22. 374
      rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_unsigned.vhdl
  23. 38
      rel/build/ip_user/a2x_axi/a2x_axi/src/support/power_logic_pkg.vhdl
  24. 360
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s18_s18.vhdl
  25. 364
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s36_s36.vhdl
  26. 360
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s9_s9.vhdl
  27. 338
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x168_1w_0.vhdl
  28. 466
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x16_1r1w_1.vhdl
  29. 411
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w.vhdl
  30. 412
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w_eco.vhdl
  31. 359
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_256x162_4w_0.vhdl
  32. 578
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_32x35_8w_1r1w.vhdl
  33. 762
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_512x288_9.vhdl
  34. 357
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x36_4w_1r1w.vhdl
  35. 381
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x42_4w_1r1w.vhdl
  36. 285
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x72_1r1w.vhdl
  37. 122
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats.vhdl
  38. 133
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats_wlcb.vhdl
  39. 501
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_bht.vhdl
  40. 191
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_boltreg_p.vhdl
  41. 145
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_caa_prism_abist.vhdl
  42. 2775
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c.vhdl
  43. 396
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c_matchline.vhdl
  44. 5047
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c.vhdl
  45. 398
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c_matchline.vhdl
  46. 178
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_parerr_mac.vhdl
  47. 66
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_direct_err_rpt.vhdl
  48. 132
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_err_rpt.vhdl
  49. 119
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats.vhdl
  50. 128
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats_wlcb.vhdl
  51. 511
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_latches_pkg.vhdl
  52. 86
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_array_mac.vhdl
  53. 86
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_mac.vhdl
  54. 85
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbnd.vhdl
  55. 71
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbor.vhdl
  56. 75
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbs.vhdl
  57. 120
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nand2_nlats.vhdl
  58. 118
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat.vhdl
  59. 117
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat_scan.vhdl
  60. 121
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nor2_nlats.vhdl
  61. 122
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_oai22_nlats.vhdl
  62. 99
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_plat.vhdl
  63. 56
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_psro_soft.vhdl
  64. 116
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regk.vhdl
  65. 127
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regs.vhdl
  66. 180
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmlatch_p.vhdl
  67. 191
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmreg_p.vhdl
  68. 100
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_ser_rlmreg_p.vhdl
  69. 973
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_serial_scom2.vhdl
  70. 80
      rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_slat_scan.vhdl
  71. 1424
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2l2_axi.vhdl
  72. 658
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_axi.vhdl
  73. 501
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_pkg.vhdl
  74. 4625
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/acq_soft.vhdl
  75. 6876
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/bxq.vhdl
  76. 1637
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq.vhdl
  77. 580
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add.vhdl
  78. 124
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_all1.vhdl
  79. 605
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_glbc.vhdl
  80. 958
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg.vhdl
  81. 670
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_add.vhdl
  82. 111
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_bypmux.vhdl
  83. 182
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_or16.vhdl
  84. 976
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh16.vhdl
  85. 708
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh4.vhdl
  86. 1807
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_byp.vhdl
  87. 751
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_cr2.vhdl
  88. 63
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_csa22_h2.vhdl
  89. 2636
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_dcd.vhdl
  90. 1570
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_dcd_uc_hooks.vhdl
  91. 599
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eie.vhdl
  92. 996
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eov.vhdl
  93. 1597
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_fmt.vhdl
  94. 1386
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_fpr.vhdl
  95. 1294
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst.vhdl
  96. 159
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_add11.vhdl
  97. 178
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_inc19.vhdl
  98. 153
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_loa.vhdl
  99. 482
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp.vhdl
  100. 325
      rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp_lsb.vhdl
  101. Some files were not shown because too many files have changed in this diff Show More

20
rel/build/a2x/a2x_impl_step.tcl

@ -0,0 +1,20 @@ @@ -0,0 +1,20 @@
#synth_design -top a2x_axi_bd_wrapper -part xcvu3p-ffvc1517-2-e -verbose
#source ila_axi.tcl
set version v0

write_checkpoint -force a2x_axi_synth_${version}.dcp

opt_design -retarget -propconst -bram_power_opt
place_design -directive Explore
phys_opt_design -directive Explore
route_design -directive Explore
phys_opt_design -directive Explore
write_checkpoint -force a2x_axi_routed_${version}.dcp

report_utilization -file utilization_route_design_${version}.rpt
report_timing_summary -max_paths 100 -file timing_routed_summary_${version}.rpt

write_bitstream -force -bin_file a2x_axi_${version}
write_debug_probes -force a2x_axi_${version}
write_cfgmem -force -format BIN -interface SPIx8 -size 256 -loadbit "up 0 a2x_axi_${version}.bit" a2x_axi_${version}

24
rel/build/a2x/bd/hdl/a2x_axi_bd_wrapper.v

@ -0,0 +1,24 @@ @@ -0,0 +1,24 @@
//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1.3_CR1055600 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
//Date : Wed Apr 8 10:49:50 2020
//Host : apdegl15aa.pok.ibm.com running 64-bit Red Hat Enterprise Linux Workstation release 7.5 (Maipo)
//Command : generate_target a2x_axi_bd_wrapper.bd
//Design : a2x_axi_bd_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module a2x_axi_bd_wrapper
(clk_in1_n_0,
clk_in1_p_0);
input clk_in1_n_0;
input clk_in1_p_0;

wire clk_in1_n_0;
wire clk_in1_p_0;

a2x_axi_bd a2x_axi_bd_i
(.clk_in1_n_0(clk_in1_n_0),
.clk_in1_p_0(clk_in1_p_0));
endmodule

1975
rel/build/a2x/create_a2x_project.tcl

File diff suppressed because it is too large Load Diff

50
rel/build/a2x/fixup_a2x_bd.tcl

@ -0,0 +1,50 @@ @@ -0,0 +1,50 @@
open_bd_design "[get_property DIRECTORY [current_project]]/proj_a2x_axi.srcs/sources_1/bd/a2x_axi_bd/a2x_axi_bd.bd"

set_property SCREENSIZE {1 1} [get_bd_cells /pain]
set_property location {5 1506 2372} [get_bd_cells pain]
set_property SCREENSIZE {1 1} [get_bd_cells /thold_0]
set_property SCREENSIZE {1 1} [get_bd_cells /xlconstant_0]
set_property location {6 2778 2069} [get_bd_cells xlconstant_0]
set_property SCREENSIZE {1 1} [get_bd_cells /xlconstant_1]
set_property location {6 2734 2210} [get_bd_cells xlconstant_1]

# so xil actually connects as bus
set_property SCREENSIZE {1 1} [get_bd_cells /mchk_rv]
set_property location {6 2767 2847} [get_bd_cells mchk_rv]
set_property SCREENSIZE {1 1} [get_bd_cells /rcov_rv]
set_property location {6 2777 2748} [get_bd_cells rcov_rv]
set_property SCREENSIZE {1 1} [get_bd_cells /checkstop_rv]
set_property location {7 2850 2630} [get_bd_cells rcov_rv]
set_property SCREENSIZE {1 1} [get_bd_cells /scomdata_rv]
set_property location {4 1355 2564} [get_bd_cells scomdata_rv]
set_property SCREENSIZE {1 1} [get_bd_cells /thread_running_rv]
set_property location {5 2152 2682} [get_bd_cells thread_running_rv]
set_property SCREENSIZE {1 1} [get_bd_cells /axi_reg00_rv]
set_property location {7 3176 2490} [get_bd_cells axi_reg00_rv]
set_property SCREENSIZE {1 1} [get_bd_cells /reverserator_4_0]
set_property location {7 2156 2797} [get_bd_cells reverserator_4_0]



set_property SCREENSIZE {600 600} [get_bd_cells /a2x_axi_1]
set_property location {5 2000 1000} [get_bd_cells /a2x_axi_1]
set_property location {4 1306 1980} [get_bd_cells a2x_dbug]

set_property location {4.5 1482 792} [get_bd_cells jtag_axi_0]

set_property location {4 1259 2326} [get_bd_cells vio_dbug] ;# no orientation, highlight, etc.
set_property location {5 1957 2377} [get_bd_cells vio_ctrl]
set_property location {6 2704 2401} [get_bd_cells vio_terror]
set_property location {7 3253 2629} [get_bd_cells vio_reg]

set_property location {10.5 4307 861} [get_bd_cells blk_mem_gen_1]
set_property location {11 4297 974} [get_bd_cells blk_mem_gen_2]

set_property location {6 2034 684} [get_bd_cells axi_smc]

set_property location {7 3129 422} [get_bd_cells ila_axi]
set_property location {9 3542 548} [get_bd_cells ila_axi_protocol]
set_property location {7 3173 580} [get_bd_cells axi_protocol_checker]

save_bd_design

58
rel/build/a2x/ila_axi.tcl

File diff suppressed because one or more lines are too long

31
rel/build/a2x/readme.md

@ -0,0 +1,31 @@ @@ -0,0 +1,31 @@
# create/build project

```
$VIVADO -mode tcl -source create_a2x_project.tcl

$VIVADO proj/proj_a2x_axi.xpr

source ./fixup_a2x_bd.tcl

>run synthesis (synth_2)
>open synthesized design

source ./ila_axi.tcl
>set up debug
> all clk
> 8192/3

source ./a2x_impl_step.tcl
```

```
a2x_axi_routed_v0.dcp
a2x_axi_synth_v0.dcp
a2x_axi_v0.bin
a2x_axi_v0.bit
a2x_axi_v0.ltx
a2x_axi_v0_primary.bin
a2x_axi_v0_primary.prm
a2x_axi_v0_secondary.bin
a2x_axi_v0_secondary.prm
```

1
rel/build/a2x/xdc

@ -0,0 +1 @@ @@ -0,0 +1 @@
../xdc

5113
rel/build/ip_user/a2x_axi/a2x_axi/component.xml

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154
rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux16.vhdl

@ -0,0 +1,154 @@ @@ -0,0 +1,154 @@
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.

library ieee; use ieee.std_logic_1164.all;
library support; use support.power_logic_pkg.all;

entity c_debug_mux16 is
generic( DBG_WIDTH : integer := 88
);
port(
vd : inout power_logic;
gd : inout power_logic;

select_bits : in std_ulogic_vector(0 to 15);
trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1);
trigger_data_in : in std_ulogic_vector(0 to 11);

dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group4 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group5 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group6 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group7 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group8 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group9 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group10 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group11 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group12 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group13 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group14 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group15 : in std_ulogic_vector(0 to DBG_WIDTH-1);

trg_group0 : in std_ulogic_vector(0 to 11);
trg_group1 : in std_ulogic_vector(0 to 11);
trg_group2 : in std_ulogic_vector(0 to 11);
trg_group3 : in std_ulogic_vector(0 to 11);

trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1);
trigger_data_out : out std_ulogic_vector(0 to 11)
);
-- synopsys translate_off

-- synopsys translate_on

end c_debug_mux16;


architecture c_debug_mux16 of c_debug_mux16 is

constant DBG_1FOURTH : positive := DBG_WIDTH/4;
constant DBG_2FOURTH : positive := DBG_WIDTH/2;
constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4;

signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1);
signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1);
signal trigg_grp_selected : std_ulogic_vector(0 to 11);
signal trigg_grp_rotated : std_ulogic_vector(0 to 11);

signal unused : std_ulogic;

begin

unused <= select_bits(4);

with select_bits(0 to 3) select debug_grp_selected <=
dbg_group0 when "0000",
dbg_group1 when "0001",
dbg_group2 when "0010",
dbg_group3 when "0011",
dbg_group4 when "0100",
dbg_group5 when "0101",
dbg_group6 when "0110",
dbg_group7 when "0111",
dbg_group8 when "1000",
dbg_group9 when "1001",
dbg_group10 when "1010",
dbg_group11 when "1011",
dbg_group12 when "1100",
dbg_group13 when "1101",
dbg_group14 when "1110",
dbg_group15 when others;

with select_bits(5 to 6) select
debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
debug_grp_selected(0 to DBG_WIDTH-1) when others;


with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <=
trace_data_in(0 to DBG_1FOURTH-1) when '0',
debug_grp_rotated(0 to DBG_1FOURTH-1) when others;

with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <=
trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0',
debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others;

with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <=
trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0',
debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others;

with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <=
trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0',
debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others;



with select_bits(11 to 12) select trigg_grp_selected <=
trg_group0 when "00",
trg_group1 when "01",
trg_group2 when "10",
trg_group3 when others;

with select_bits(13) select
trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
trigg_grp_selected(0 to 11) when others;

with select_bits(14) select trigger_data_out(0 to 5) <=
trigger_data_in(0 to 5) when '0',
trigg_grp_rotated(0 to 5) when others;

with select_bits(15) select trigger_data_out(6 to 11) <=
trigger_data_in(6 to 11) when '0',
trigg_grp_rotated(6 to 11) when others;


end c_debug_mux16;

184
rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux32.vhdl

@ -0,0 +1,184 @@ @@ -0,0 +1,184 @@
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.

library ieee; use ieee.std_logic_1164.all;
library support;
use support.power_logic_pkg.all;

entity c_debug_mux32 is
generic( DBG_WIDTH : integer := 88
);
port(
vd : inout power_logic;
gd : inout power_logic;

select_bits : in std_ulogic_vector(0 to 15);
trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1);
trigger_data_in : in std_ulogic_vector(0 to 11);

dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group4 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group5 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group6 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group7 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group8 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group9 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group10 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group11 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group12 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group13 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group14 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group15 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group16 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group17 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group18 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group19 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group20 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group21 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group22 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group23 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group24 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group25 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group26 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group27 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group28 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group29 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group30 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group31 : in std_ulogic_vector(0 to DBG_WIDTH-1);

trg_group0 : in std_ulogic_vector(0 to 11);
trg_group1 : in std_ulogic_vector(0 to 11);
trg_group2 : in std_ulogic_vector(0 to 11);
trg_group3 : in std_ulogic_vector(0 to 11);

trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1);
trigger_data_out : out std_ulogic_vector(0 to 11)
);
-- synopsys translate_off

-- synopsys translate_on

end c_debug_mux32;


architecture c_debug_mux32 of c_debug_mux32 is

constant DBG_1FOURTH : positive := DBG_WIDTH/4;
constant DBG_2FOURTH : positive := DBG_WIDTH/2;
constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4;

signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1);
signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1);
signal trigg_grp_selected : std_ulogic_vector(0 to 11);
signal trigg_grp_rotated : std_ulogic_vector(0 to 11);

begin


with select_bits(0 to 4) select debug_grp_selected <=
dbg_group0 when "00000",
dbg_group1 when "00001",
dbg_group2 when "00010",
dbg_group3 when "00011",
dbg_group4 when "00100",
dbg_group5 when "00101",
dbg_group6 when "00110",
dbg_group7 when "00111",
dbg_group8 when "01000",
dbg_group9 when "01001",
dbg_group10 when "01010",
dbg_group11 when "01011",
dbg_group12 when "01100",
dbg_group13 when "01101",
dbg_group14 when "01110",
dbg_group15 when "01111",
dbg_group16 when "10000",
dbg_group17 when "10001",
dbg_group18 when "10010",
dbg_group19 when "10011",
dbg_group20 when "10100",
dbg_group21 when "10101",
dbg_group22 when "10110",
dbg_group23 when "10111",
dbg_group24 when "11000",
dbg_group25 when "11001",
dbg_group26 when "11010",
dbg_group27 when "11011",
dbg_group28 when "11100",
dbg_group29 when "11101",
dbg_group30 when "11110",
dbg_group31 when others;

with select_bits(5 to 6) select
debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
debug_grp_selected(0 to DBG_WIDTH-1) when others;


with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <=
trace_data_in(0 to DBG_1FOURTH-1) when '0',
debug_grp_rotated(0 to DBG_1FOURTH-1) when others;

with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <=
trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0',
debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others;

with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <=
trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0',
debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others;

with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <=
trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0',
debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others;



with select_bits(11 to 12) select trigg_grp_selected <=
trg_group0 when "00",
trg_group1 when "01",
trg_group2 when "10",
trg_group3 when others;

with select_bits(13) select
trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
trigg_grp_selected(0 to 11) when others;

with select_bits(14) select trigger_data_out(0 to 5) <=
trigger_data_in(0 to 5) when '0',
trigg_grp_rotated(0 to 5) when others;

with select_bits(15) select trigger_data_out(6 to 11) <=
trigger_data_in(6 to 11) when '0',
trigg_grp_rotated(6 to 11) when others;


end c_debug_mux32;

131
rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux4.vhdl

@ -0,0 +1,131 @@ @@ -0,0 +1,131 @@
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.

library ieee; use ieee.std_logic_1164.all;
library support;
use support.power_logic_pkg.all;

entity c_debug_mux4 is
generic( DBG_WIDTH : integer := 88
);
port(
vd : inout power_logic;
gd : inout power_logic;

select_bits : in std_ulogic_vector(0 to 15);
trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1);
trigger_data_in : in std_ulogic_vector(0 to 11);

dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1);

trg_group0 : in std_ulogic_vector(0 to 11);
trg_group1 : in std_ulogic_vector(0 to 11);
trg_group2 : in std_ulogic_vector(0 to 11);
trg_group3 : in std_ulogic_vector(0 to 11);

trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1);
trigger_data_out : out std_ulogic_vector(0 to 11)
);
-- synopsys translate_off

-- synopsys translate_on

end c_debug_mux4;


architecture c_debug_mux4 of c_debug_mux4 is

constant DBG_1FOURTH : positive := DBG_WIDTH/4;
constant DBG_2FOURTH : positive := DBG_WIDTH/2;
constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4;

signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1);
signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1);
signal trigg_grp_selected : std_ulogic_vector(0 to 11);
signal trigg_grp_rotated : std_ulogic_vector(0 to 11);

signal unused : std_ulogic;

begin

unused <= select_bits(2) or select_bits(3) or select_bits(4);

with select_bits(0 to 1) select debug_grp_selected <=
dbg_group0 when "00",
dbg_group1 when "01",
dbg_group2 when "10",
dbg_group3 when others;

with select_bits(5 to 6) select
debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
debug_grp_selected(0 to DBG_WIDTH-1) when others;


with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <=
trace_data_in(0 to DBG_1FOURTH-1) when '0',
debug_grp_rotated(0 to DBG_1FOURTH-1) when others;

with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <=
trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0',
debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others;

with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <=
trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0',
debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others;

with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <=
trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0',
debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others;



with select_bits(11 to 12) select trigg_grp_selected <=
trg_group0 when "00",
trg_group1 when "01",
trg_group2 when "10",
trg_group3 when others;

with select_bits(13) select
trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
trigg_grp_selected(0 to 11) when others;

with select_bits(14) select trigger_data_out(0 to 5) <=
trigger_data_in(0 to 5) when '0',
trigg_grp_rotated(0 to 5) when others;

with select_bits(15) select trigger_data_out(6 to 11) <=
trigger_data_in(6 to 11) when '0',
trigg_grp_rotated(6 to 11) when others;


end c_debug_mux4;

139
rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux8.vhdl

@ -0,0 +1,139 @@ @@ -0,0 +1,139 @@
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.

library ieee; use ieee.std_logic_1164.all;
library support;
use support.power_logic_pkg.all;

entity c_debug_mux8 is
generic( DBG_WIDTH : integer := 88
);
port(
vd : inout power_logic;
gd : inout power_logic;

select_bits : in std_ulogic_vector(0 to 15);
trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1);
trigger_data_in : in std_ulogic_vector(0 to 11);

dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group4 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group5 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group6 : in std_ulogic_vector(0 to DBG_WIDTH-1);
dbg_group7 : in std_ulogic_vector(0 to DBG_WIDTH-1);

trg_group0 : in std_ulogic_vector(0 to 11);
trg_group1 : in std_ulogic_vector(0 to 11);
trg_group2 : in std_ulogic_vector(0 to 11);
trg_group3 : in std_ulogic_vector(0 to 11);

trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1);
trigger_data_out : out std_ulogic_vector(0 to 11)
);
-- synopsys translate_off

-- synopsys translate_on

end c_debug_mux8;


architecture c_debug_mux8 of c_debug_mux8 is

constant DBG_1FOURTH : positive := DBG_WIDTH/4;
constant DBG_2FOURTH : positive := DBG_WIDTH/2;
constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4;

signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1);
signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1);
signal trigg_grp_selected : std_ulogic_vector(0 to 11);
signal trigg_grp_rotated : std_ulogic_vector(0 to 11);

signal unused : std_ulogic;

begin

unused <= select_bits(3) or select_bits(4);

with select_bits(0 to 2) select debug_grp_selected <=
dbg_group0 when "000",
dbg_group1 when "001",
dbg_group2 when "010",
dbg_group3 when "011",
dbg_group4 when "100",
dbg_group5 when "101",
dbg_group6 when "110",
dbg_group7 when others;

with select_bits(5 to 6) select
debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
debug_grp_selected(0 to DBG_WIDTH-1) when others;


with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <=
trace_data_in(0 to DBG_1FOURTH-1) when '0',
debug_grp_rotated(0 to DBG_1FOURTH-1) when others;

with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <=
trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0',
debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others;

with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <=
trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0',
debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others;

with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <=
trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0',
debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others;



with select_bits(11 to 12) select trigg_grp_selected <=
trg_group0 when "00",
trg_group1 when "01",
trg_group2 when "10",
trg_group3 when others;

with select_bits(13) select
trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
trigg_grp_selected(0 to 11) when others;

with select_bits(14) select trigger_data_out(0 to 5) <=
trigger_data_in(0 to 5) when '0',
trigg_grp_rotated(0 to 5) when others;

with select_bits(15) select trigger_data_out(6 to 11) <=
trigger_data_in(6 to 11) when '0',
trigg_grp_rotated(6 to 11) when others;


end c_debug_mux8;

146
rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_event_mux.vhdl

@ -0,0 +1,146 @@ @@ -0,0 +1,146 @@
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.

library ieee,support,ibm;
use ieee.std_logic_1164.all;
use ibm.std_ulogic_function_support.all;
use support.power_logic_pkg.all;

entity c_event_mux is
generic( events_in : integer := 32;
events_out : integer := 8 );
port(
vd : inout power_logic;
gd : inout power_logic;
t0_events : in std_ulogic_vector(0 to events_in/4-1);
t1_events : in std_ulogic_vector(0 to events_in/4-1);
t2_events : in std_ulogic_vector(0 to events_in/4-1);
t3_events : in std_ulogic_vector(0 to events_in/4-1);

select_bits : in std_ulogic_vector(0 to ((events_in/64+4)*events_out)-1);

event_bits : out std_ulogic_vector(0 to events_out-1)
);
-- synopsys translate_off

-- synopsys translate_on

end c_event_mux;


architecture c_event_mux of c_event_mux is

constant INCR : natural := events_in/64+4;
constant SIZE : natural := events_in/64+1;


signal inMuxDec : std_ulogic_vector(0 to events_out*events_in/4-1);
signal inMuxOut : std_ulogic_vector(0 to events_out*events_in/4-1);

signal thrd_sel : std_ulogic_vector(0 to events_out-1);
signal inMux_sel : std_ulogic_vector(0 to ((events_in/64+3)*events_out)-1);


begin
thrd_sel <= select_bits(0*INCR) & select_bits(1*INCR) &
select_bits(2*INCR) & select_bits(3*INCR) &
select_bits(4*INCR) & select_bits(5*INCR) &
select_bits(6*INCR) & select_bits(7*INCR) ;

inMux_sel <= select_bits(0*INCR+1 to (0+1)*INCR-1) &
select_bits(1*INCR+1 to (1+1)*INCR-1) &
select_bits(2*INCR+1 to (2+1)*INCR-1) &
select_bits(3*INCR+1 to (3+1)*INCR-1) &
select_bits(4*INCR+1 to (4+1)*INCR-1) &
select_bits(5*INCR+1 to (5+1)*INCR-1) &
select_bits(6*INCR+1 to (6+1)*INCR-1) &
select_bits(7*INCR+1 to (7+1)*INCR-1) ;


decode: for X in 0 to events_out-1 generate
Mux32: if (events_in = 32) generate
inMuxDec(X*events_in/4 to X*events_in/4+7) <= decode_3to8(inMux_sel(X*3 to X*3+2));
end generate Mux32;

Mux64: if (events_in = 64) generate
inMuxDec(X*events_in/4 to X*events_in/4+15) <= decode_4to16(inMux_sel(X*4 to X*4+3));
end generate Mux64;

Mux128: if (events_in = 128) generate
inMuxDec(X*events_in/4 to X*events_in/4+31) <= decode_5to32(inMux_sel(X*5 to X*5+4));
end generate Mux128;
end generate decode;


inpMuxHi: for X in 0 to events_out/2-1 generate
eventSel: for I in 0 to events_in/4-1 generate
inMuxOut(X*events_in/4 + I) <=
((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t0_events(I)) or
(inMuxDec(X*events_in/4 + I) and thrd_sel(X) and t1_events(I)) );
end generate eventSel;
end generate inpMuxHi;

inpMuxLo: for X in events_out/2 to events_out-1 generate
eventSel: for I in 0 to events_in/4-1 generate
inMuxOut(X*events_in/4 + I) <=
((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t2_events(I)) or
(inMuxDec(X*events_in/4 + I) and thrd_sel(X) and t3_events(I)) );
end generate eventSel;
end generate inpMuxLo;


bitOutHi: for X in 0 to events_out/2-1 generate
Mux32: if (events_in = 32) generate
event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7));
end generate Mux32;

Mux64: if (events_in = 64) generate
event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15));
end generate Mux64;

Mux128: if (events_in = 128) generate
event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31));
end generate Mux128;
end generate bitOutHi;

bitOutLo: for X in events_out/2 to events_out-1 generate
Mux32: if (events_in = 32) generate
event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7));
end generate Mux32;

Mux64: if (events_in = 64) generate
event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15));
end generate Mux64;

Mux128: if (events_in = 128) generate
event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31));
end generate Mux128;
end generate bitOutLo;

end c_event_mux;

97
rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_bthmx.vhdl

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-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.

library ieee; use ieee.std_logic_1164.all ;
library ibm;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
use ibm.std_ulogic_ao_support.all;
use ibm.std_ulogic_mux_support.all;
library support; use support.power_logic_pkg.all;

ENTITY c_prism_bthmx IS
GENERIC ( btr : string := "BTHMX_X1_A12TH" );
PORT(
X : IN STD_ULOGIC;
SNEG : IN STD_ULOGIC;
SX : IN STD_ULOGIC;
SX2 : IN STD_ULOGIC;
RIGHT : IN STD_ULOGIC;
LEFT : OUT STD_ULOGIC;
Q : OUT STD_ULOGIC;
vd : inout power_logic;
gd : inout power_logic
);

-- synopsys translate_off


ATTRIBUTE PIN_BIT_INFORMATION of c_prism_bthmx : entity is
(
1 => (" ","X ","SAME","PIN_BIT_SCALAR"),
2 => (" ","SNEG ","SAME","PIN_BIT_SCALAR"),
3 => (" ","SX ","SAME","PIN_BIT_SCALAR"),
4 => (" ","SX2 ","SAME","PIN_BIT_SCALAR"),
5 => (" ","RIGHT ","SAME","PIN_BIT_SCALAR"),
6 => (" ","LEFT ","SAME","PIN_BIT_SCALAR"),
7 => (" ","Q ","SAME","PIN_BIT_SCALAR"),
8 => (" ","VDD ","SAME","PIN_BIT_SCALAR"),
9 => (" ","VSS ","SAME","PIN_BIT_SCALAR")
);
-- synopsys translate_on
END c_prism_bthmx;

ARCHITECTURE c_prism_bthmx OF c_prism_bthmx IS

SIGNAL CENTER :STD_ULOGIC;
SIGNAL XN :STD_ULOGIC;
SIGNAL SPOS :STD_ULOGIC;


BEGIN

XN <= NOT X;

SPOS <= NOT SNEG;

CENTER <= NOT( ( XN AND SPOS ) OR
( X AND SNEG ) );

LEFT <= CENTER;


Q <= ( CENTER AND SX ) OR
( RIGHT AND SX2 ) ;


END;





82
rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa32.vhdl

@ -0,0 +1,82 @@ @@ -0,0 +1,82 @@
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.

library ieee; use ieee.std_logic_1164.all ;
library ibm;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
use ibm.std_ulogic_ao_support.all;
use ibm.std_ulogic_mux_support.all;
library support; use support.power_logic_pkg.all;

ENTITY c_prism_csa32 IS
GENERIC ( btr : string := "CSA32_A2_A12TH" );
PORT(
A : IN std_ulogic;
B : IN std_ulogic;
C : IN std_ulogic;
CAR : OUT std_ulogic;
SUM : OUT std_ulogic;
vd : inout power_logic;
gd : inout power_logic
);

-- synopsys translate_off


ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa32 : entity is
(
1 => (" ","A ","SAME","PIN_BIT_SCALAR"),
2 => (" ","B ","SAME","PIN_BIT_SCALAR"),
3 => (" ","C ","SAME","PIN_BIT_SCALAR"),
4 => (" ","CAR ","SAME","PIN_BIT_SCALAR"),
5 => (" ","SUM ","SAME","PIN_BIT_SCALAR"),
6 => (" ","VDD ","SAME","PIN_BIT_SCALAR"),
7 => (" ","VSS ","SAME","PIN_BIT_SCALAR")
);
-- synopsys translate_on
END c_prism_csa32;

ARCHITECTURE c_prism_csa32 OF c_prism_csa32 IS


BEGIN

sum <= a XOR b XOR c ;

car <= (a AND b ) OR
(a AND c ) OR
(b AND c );


END;





96
rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa42.vhdl

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-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.


library ieee; use ieee.std_logic_1164.all ;
library support;
library ibm;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
use ibm.std_ulogic_ao_support.all;
use ibm.std_ulogic_mux_support.all;
use support.power_logic_pkg.all;

ENTITY c_prism_csa42 IS
GENERIC ( btr : string := "CSA42_A2_A12TH" );
PORT(
A : IN std_ulogic;
B : IN std_ulogic;
C : IN std_ulogic;
D : IN std_ulogic;
KI : IN std_ulogic;
KO : OUT std_ulogic;
CAR : OUT std_ulogic;
SUM : OUT std_ulogic;
vd : inout power_logic;
gd : inout power_logic
);

-- synopsys translate_off


ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa42 : entity is
(
1 => (" ","A ","SAME","PIN_BIT_SCALAR"),
2 => (" ","B ","SAME","PIN_BIT_SCALAR"),
3 => (" ","C ","SAME","PIN_BIT_SCALAR"),
4 => (" ","D ","SAME","PIN_BIT_SCALAR"),
5 => (" ","KI ","SAME","PIN_BIT_SCALAR"),
6 => (" ","KO ","SAME","PIN_BIT_SCALAR"),
7 => (" ","CAR ","SAME","PIN_BIT_SCALAR"),
8 => (" ","SUM ","SAME","PIN_BIT_SCALAR"),
9 => (" ","VDD ","SAME","PIN_BIT_SCALAR"),
10 => (" ","VSS ","SAME","PIN_BIT_SCALAR")
);
-- synopsys translate_on
END c_prism_csa42;

ARCHITECTURE c_prism_csa42 OF c_prism_csa42 IS

signal s1 : std_ulogic;

BEGIN

s1 <= b XOR c XOR d ;
sum <= s1 XOR a XOR ki;

car <= (s1 AND a ) OR
(s1 AND ki) OR
(a AND ki);

ko <= (b AND c ) OR
(b AND d ) OR
(c AND d );


END;





70
rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_scom_addr_decode.vhdl

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-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.



library ieee,ibm,latches,clib, support;
use ieee.std_logic_1164.all;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
use support.power_logic_pkg.all;

entity c_scom_addr_decode is
generic( satid_nobits : positive := 5
; use_addr : std_ulogic_vector := "1"
; addr_is_rdable : std_ulogic_vector := "1"
; addr_is_wrable : std_ulogic_vector := "1"
);
port( sc_addr : in std_ulogic_vector(0 to 11-satid_nobits-1)
; scaddr_dec : out std_ulogic_vector(0 to use_addr'length-1)
; sc_req : in std_ulogic
; sc_r_nw : in std_ulogic
; scaddr_nvld : out std_ulogic
; sc_wr_nvld : out std_ulogic
; sc_rd_nvld : out std_ulogic
; vd : inout power_logic
; gd : inout power_logic
);

end c_scom_addr_decode;



architecture c_scom_addr_decode of c_scom_addr_decode is
signal address : std_ulogic_vector(0 to use_addr'length-1);
begin
decode_it : for i in 0 to use_addr'length-1 generate
address(i) <= ((sc_addr = tconv(i,sc_addr'length)) and (use_addr(i)='1'));
end generate decode_it;

scaddr_dec <= address;
scaddr_nvld <= sc_req and not or_reduce(address);
sc_wr_nvld <= not or_reduce(address and addr_is_wrable) and sc_req and not sc_r_nw;
sc_rd_nvld <= not or_reduce(address and addr_is_rdable) and sc_req and sc_r_nw;
end c_scom_addr_decode;

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374
rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_unsigned.vhdl

@ -0,0 +1,374 @@ @@ -0,0 +1,374 @@
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.

--***************************************************************************
-- Copyright 2020 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the “License”);
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- The patent license granted to you in Section 3 of the License, as applied
-- to the “Work,” hereby includes implementations of the Work in physical form.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an “AS IS” BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
--***************************************************************************
library IEEE, IBM;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IBM.std_ulogic_support.all;

package std_ulogic_unsigned is

function "+"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector;
function "+"(l: std_ulogic_vector; r: integer) return std_ulogic_vector;
function "+"(l: integer; r: std_ulogic_vector) return std_ulogic_vector;
function "+"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector;
function "+"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector;

function "-"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector;
function "-"(l: std_ulogic_vector; r: integer) return std_ulogic_vector;
function "-"(l: integer; r: std_ulogic_vector) return std_ulogic_vector;
function "-"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector;
function "-"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector;

function "+"(l: std_ulogic_vector) return std_ulogic_vector;

function "*"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector;

function "=" ( l : natural; r : std_ulogic_vector) return boolean;
function "/="( l : natural; r : std_ulogic_vector) return boolean;
function "<" ( l : natural; r : std_ulogic_vector) return boolean;
function "<="( l : natural; r : std_ulogic_vector) return boolean;
function ">" ( l : natural; r : std_ulogic_vector) return boolean;
function ">="( l : natural; r : std_ulogic_vector) return boolean;

function "=" ( l : std_ulogic_vector; r : natural) return boolean;
function "/="( l : std_ulogic_vector; r : natural) return boolean;
function "<" ( l : std_ulogic_vector; r : natural) return boolean;
function "<="( l : std_ulogic_vector; r : natural) return boolean;
function ">" ( l : std_ulogic_vector; r : natural) return boolean;
function ">="( l : std_ulogic_vector; r : natural) return boolean;
function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic;
function "/="( l : natural; r : std_ulogic_vector) return std_ulogic;
function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic;
function "<="( l : natural; r : std_ulogic_vector) return std_ulogic;
function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic;
function ">="( l : natural; r : std_ulogic_vector) return std_ulogic;

function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic;
function "/="( l : std_ulogic_vector; r : natural) return std_ulogic;
function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic;
function "<="( l : std_ulogic_vector; r : natural) return std_ulogic;
function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic;
function ">="( l : std_ulogic_vector; r : natural) return std_ulogic;

function to_integer( d : std_ulogic_vector ) return natural;
-- synopsys translate_off
attribute type_convert of to_integer : function is true;
attribute btr_name of to_integer : function is "PASS";
attribute pin_bit_information of to_integer : function is
(1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"),
2 => (" ","10 ","INCR","PIN_BIT_SCALAR"));
-- synopsys translate_on
-- synopsys translate_off
function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector;
attribute type_convert of to_std_ulogic_vector : function is true;
attribute btr_name of to_std_ulogic_vector : function is "PASS";
attribute pin_bit_information of to_std_ulogic_vector : function is
(1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"),
2 => (" ","10 ","INCR","PIN_BIT_SCALAR"));
-- synopsys translate_on
end std_ulogic_unsigned;

package body std_ulogic_unsigned is

function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;

function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
constant length : INTEGER := maximum(L'length, R'length);
variable result : UNSIGNED(length-1 downto 0);
-- pragma label_applies_to plus
begin
result := UNSIGNED(L) + UNSIGNED(R); -- pragma label plus
return std_ulogic_vector(result);
end;

function "+"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (L'range);
-- pragma label_applies_to plus
begin
result := std_ulogic_vector( UNSIGNED(L) + R ); -- pragma label plus
return result ;
end;

function "+"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (R'range);
-- pragma label_applies_to plus
begin
result := std_ulogic_vector( L + UNSIGNED(R) ); -- pragma label plus
return result;
end;

function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (L'range);
-- pragma label_applies_to plus
begin
if R = '1' then
result := std_ulogic_vector( UNSIGNED(L) + 1 );
else
result := L;
end if;
return result ;
end;

function "+"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (R'range);
-- pragma label_applies_to plus
begin
if L = '1' then
result := std_ulogic_vector( UNSIGNED(R) + 1 );
else
result := R;
end if;
return result ;
end;

function "+"(L: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (L'range);
-- pragma label_applies_to plus
begin
result := L;
return result ;
end;

function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_ULOGIC_VECTOR (length-1 downto 0);
-- pragma label_applies_to minus
begin
result := std_ulogic_vector( UNSIGNED(L) - UNSIGNED(R) ); -- pragma label minus
return result ;
end;

function "-"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (L'range);
-- pragma label_applies_to minus
begin
result := std_ulogic_vector( UNSIGNED(L) - R ); -- pragma label minus
return result ;
end;

function "-"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (R'range);
-- pragma label_applies_to minus
begin
result := std_ulogic_vector( L - UNSIGNED(R) ); -- pragma label minus
return result ;
end;

function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (L'range);
-- pragma label_applies_to minus
begin
if R = '1' then
result := std_ulogic_vector( UNSIGNED(L) - 1 );
else
result := L;
end if;
return result ;
end;

function "-"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (R'range);
-- pragma label_applies_to minus
begin
if L = '1' then
result := std_ulogic_vector( 1 - UNSIGNED(R) );
else
result := std_ulogic_vector( 0 - UNSIGNED(R) );
end if;
return result ;
end;

function "*"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_ULOGIC_VECTOR ((L'length+R'length-1) downto 0);
-- pragma label_applies_to mult
begin
result := std_ulogic_vector( UNSIGNED(L) * UNSIGNED(R) ); -- pragma label mult
return result ;
end;

function "=" ( l : natural; r : std_ulogic_vector) return boolean is
begin
return l = unsigned(r);
end "=";
function "/="( l : natural; r : std_ulogic_vector) return boolean is
begin
return l /= unsigned(r);
end "/=";
function "<" ( l : natural; r : std_ulogic_vector) return boolean is
begin
return l < unsigned(r);
end "<";
function "<="( l : natural; r : std_ulogic_vector) return boolean is
begin
return l <= unsigned(r);
end "<=";
function ">" ( l : natural; r : std_ulogic_vector) return boolean is
begin
return l > unsigned(r);
end ">";
function ">="( l : natural; r : std_ulogic_vector) return boolean is
begin
return l >= unsigned(r);
end ">=";
function "=" ( l : std_ulogic_vector; r : natural) return boolean is
begin
return unsigned(l) = r;
end "=";
function "/="( l : std_ulogic_vector; r : natural) return boolean is
begin
return unsigned(l) /= r;
end "/=";
function "<" ( l : std_ulogic_vector; r : natural) return boolean is
begin
return unsigned(l) < r;
end "<";
function "<="( l : std_ulogic_vector; r : natural) return boolean is
begin
return unsigned(l) <= r;
end "<=";
function ">" ( l : std_ulogic_vector; r : natural) return boolean is
begin
return unsigned(l) > r;
end ">";
function ">="( l : std_ulogic_vector; r : natural) return boolean is
begin
return unsigned(l) >= r;
end ">=";
function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic is
begin
return tconv( l = unsigned(r) );
end "=";
function "/="( l : natural; r : std_ulogic_vector) return std_ulogic is
begin
return tconv( l /= unsigned(r) );
end "/=";
function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic is
begin
return tconv( l < unsigned(r) );
end "<";
function "<="( l : natural; r : std_ulogic_vector) return std_ulogic is
begin
return tconv( l <= unsigned(r) );
end "<=";
function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic is
begin
return tconv( l > unsigned(r) );
end ">";
function ">="( l : natural; r : std_ulogic_vector) return std_ulogic is
begin
return tconv( l >= unsigned(r) );
end ">=";
function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic is
begin
return tconv( unsigned(l) = r );
end "=";
function "/="( l : std_ulogic_vector; r : natural) return std_ulogic is
begin
return tconv( unsigned(l) /= r );
end "/=";
function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic is
begin
return tconv( unsigned(l) < r );
end "<";
function "<="( l : std_ulogic_vector; r : natural) return std_ulogic is
begin
return tconv( unsigned(l) <= r );
end "<=";
function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic is
begin
return tconv( unsigned(l) > r );
end ">";
function ">="( l : std_ulogic_vector; r : natural) return std_ulogic is
begin
return tconv( unsigned(l) >= r );
end ">=";
function to_integer( d : std_ulogic_vector ) return natural is
begin
return tconv( d );
end to_integer;
function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector is
begin
return tconv( d, w );
end to_std_ulogic_vector;
end std_ulogic_unsigned;

38
rel/build/ip_user/a2x_axi/a2x_axi/src/support/power_logic_pkg.vhdl

@ -0,0 +1,38 @@ @@ -0,0 +1,38 @@
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.

library ieee;
use ieee.std_logic_1164.all;

package power_logic_pkg is

subtype power_logic is std_logic;
subtype power_logic_vector is std_logic_vector;
end package power_logic_pkg;

360
rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s18_s18.vhdl

@ -0,0 +1,360 @@ @@ -0,0 +1,360 @@
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship