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71 lines
3.1 KiB
VHDL
71 lines
3.1 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,latches,clib, support;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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entity c_scom_addr_decode is
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generic( satid_nobits : positive := 5
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; use_addr : std_ulogic_vector := "1"
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; addr_is_rdable : std_ulogic_vector := "1"
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; addr_is_wrable : std_ulogic_vector := "1"
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);
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port( sc_addr : in std_ulogic_vector(0 to 11-satid_nobits-1)
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; scaddr_dec : out std_ulogic_vector(0 to use_addr'length-1)
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; sc_req : in std_ulogic
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; sc_r_nw : in std_ulogic
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; scaddr_nvld : out std_ulogic
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; sc_wr_nvld : out std_ulogic
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; sc_rd_nvld : out std_ulogic
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; vd : inout power_logic
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; gd : inout power_logic
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);
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end c_scom_addr_decode;
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architecture c_scom_addr_decode of c_scom_addr_decode is
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signal address : std_ulogic_vector(0 to use_addr'length-1);
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begin
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decode_it : for i in 0 to use_addr'length-1 generate
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address(i) <= ((sc_addr = tconv(i,sc_addr'length)) and (use_addr(i)='1'));
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end generate decode_it;
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scaddr_dec <= address;
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scaddr_nvld <= sc_req and not or_reduce(address);
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sc_wr_nvld <= not or_reduce(address and addr_is_wrable) and sc_req and not sc_r_nw;
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sc_rd_nvld <= not or_reduce(address and addr_is_rdable) and sc_req and sc_r_nw;
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end c_scom_addr_decode;
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