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75 lines
2.3 KiB
VHDL
75 lines
2.3 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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entity fuq_mul_bthmux is port(
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X : IN STD_ULOGIC;
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SNEG : IN STD_ULOGIC;
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SX : IN STD_ULOGIC;
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SX2 : IN STD_ULOGIC;
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RIGHT : IN STD_ULOGIC;
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LEFT : OUT STD_ULOGIC;
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Q : OUT STD_ULOGIC
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);
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end fuq_mul_bthmux;
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architecture fuq_mul_bthmux of fuq_mul_bthmux is
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signal center, q_b :std_ulogic ;
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begin
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u_bmx_xor: center <= x xor sneg ;
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left <= center ;
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u_bmx_aoi: q_b <= not( ( sx and center ) or
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( sx2 and right ) );
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u_bmx_inv: q <= not q_b ;
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end;
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