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72 lines
2.6 KiB
VHDL
72 lines
2.6 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- *!****************************************************************
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-- *! FILENAME : tri_lcbs.vhdl
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-- *! DESCRIPTION : Wrapper for slat LCB
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-- *!****************************************************************
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library ieee; use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library support;
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use support.power_logic_pkg.all;
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library tri; use tri.tri_latches_pkg.all;
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entity tri_lcbs is
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generic ( expand_type : integer := 1 ); -- 1 = non-ibm, 2 = ibm (MPG)
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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delay_lclkr : in std_ulogic;
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nclk : in clk_logic;
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forcee : in std_ulogic;
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thold_b : in std_ulogic;
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dclk : out std_ulogic;
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lclk : out clk_logic
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);
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end entity tri_lcbs;
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architecture tri_lcbs of tri_lcbs is
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begin
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a: if expand_type = 1 generate
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signal unused : std_ulogic;
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begin
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-- No scan chain in this methodology
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dclk <= thold_b;
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lclk <= nclk;
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unused <= delay_lclkr or forcee;
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end generate a;
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end tri_lcbs;
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