a2o/dev/verilog/trilib/tri_slat_scan.v

// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
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//
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//
//    1) For the purpose of the patent license granted to you in Section 3 of the
//    License, the "Work" hereby includes implementations of the work of authorship
//    in physical form.
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//    2) Notwithstanding any terms to the contrary in the License, any licenses
//    necessary for implementation of the Work that are available from OpenPOWER
//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
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`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME    : tri_slat_scan.v
// *! DESCRIPTION : n-bit scan-only latch without scan_connect
// *!
// *!****************************************************************

`include "tri_a2o.vh"

module tri_slat_scan(
   vd,
   gd,
   dclk,
   lclk,
   scan_in,
   scan_out,
   q,
   q_b
);
   parameter                      WIDTH = 1;
   parameter                      OFFSET = 0;
   parameter                      INIT = 0;
   parameter                      SYNTHCLONEDLATCH = "";
   parameter                      BTR = "c_slat_scan";
   parameter                      RESET_INVERTS_SCAN = 1'b1;

   inout                          vd;
   inout                          gd;
   input                          dclk;
   //input [0:`NCLK_WIDTH-1]        lclk;
   input                          lclk;
   input [OFFSET:OFFSET+WIDTH-1]  scan_in;
   output [OFFSET:OFFSET+WIDTH-1] scan_out;
   output [OFFSET:OFFSET+WIDTH-1] q;
   output [OFFSET:OFFSET+WIDTH-1] q_b;

   // tri_slat_scan

   parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};
   parameter [0:WIDTH-1]          initv = INIT;

   (* analysis_not_referenced="true" *)
   wire                           unused;

   assign unused = | {dclk, lclk, scan_in};

   assign scan_out = ZEROS;
   assign q = initv;
   assign q_b = (~initv);
endmodule