vdd,gnd

dev/verilog/trilib/tri_aoi22_nlats_wlcb.v

@@ -139,6 +139,6 @@ module tri_aoi22_nlats_wlcb (
 
       assign scout = ZEROS;
 
-      assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|scin);
+      assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b (|scin);
    endgenerate
 endmodule

dev/verilog/trilib/tri_direct_err_rpt.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -48,10 +48,5 @@ module tri_direct_err_rpt(
 
    // tri_direct_err_rpt
 
-    (* analysis_not_referenced="true" *)
-   wire               unused;
-
-   assign unused = vd | gd;
-
    assign err_out = err_in;
 endmodule

dev/verilog/trilib/tri_inv_nlats.v

@@ -116,7 +116,7 @@ module tri_inv_nlats(
       assign qb = (~int_dout);
       assign scanout = ZEROS;
 
-      assign unused = | {vd, gd, scanin};
+      assign unused = | {scanin};
    end
    endgenerate
 endmodule

dev/verilog/trilib/tri_lcbcntl_array_mac.v

@@ -81,5 +81,5 @@ module tri_lcbcntl_array_mac (
    assign mpw2_dc_b = 1'b1;
    assign scan_out = 1'b0;
 
-   assign unused = vdd | gnd | sg | scan_in | scan_diag_dc | thold;
+   assign unused = sg | scan_in | scan_diag_dc | thold;
 endmodule

dev/verilog/trilib/tri_lcbcntl_mac.v

@@ -81,5 +81,5 @@ module tri_lcbcntl_mac (
    assign mpw2_dc_b = 1'b1;
    assign scan_out = 1'b0;
 
-   assign unused = vdd | gnd | sg | scan_in | scan_diag_dc | thold;
+   assign unused = sg | scan_in | scan_diag_dc | thold;
 endmodule

dev/verilog/trilib/tri_lcbnd.v

@@ -73,7 +73,7 @@ module tri_lcbnd (
     (* analysis_not_referenced="true" *)
    wire       unused;
 
-   assign unused = vd | gd | delay_lclkr | mpw1_b | mpw2_b | sg;
+   assign unused = delay_lclkr | mpw1_b | mpw2_b | sg;
 
    assign gate_b = force_t | act;
 

dev/verilog/trilib/tri_lcbs_UNUSED.v

@@ -1,69 +0,0 @@
-// © IBM Corp. 2022
-// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-// the terms below; you may not use the files in this repository except in
-// compliance with the License as modified.
-// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
-//
-// Modified Terms:
-//
-//    1) For the purpose of the patent license granted to you in Section 3 of the
-//    License, the "Work" hereby includes implementations of the work of authorship
-//    in physical form.
-//
-//    2) Notwithstanding any terms to the contrary in the License, any licenses
-//    necessary for implementation of the Work that are available from OpenPOWER
-//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
-//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.
-//
-// Unless required by applicable law or agreed to in writing, the reference design
-// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-// for the specific language governing permissions and limitations under the License.
-//
-// Additional rights, including the ability to physically implement a softcore that
-// is compliant with the required sections of the Power ISA Specification, are
-// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
-
-`timescale 1 ns / 1 ns
-
-// *!****************************************************************
-// *! FILENAME    : tri_lcbs.v
-// *! DESCRIPTION : Wrapper for slat LCB
-// *!****************************************************************
-
-`include "tri_a2o.vh"
-
-module tri_lcbs (
-   vd,
-   gd,
-   delay_lclkr,
-   clk,
-   rst,
-   force_t,
-   thold_b,
-   dclk,
-   lclk
-);
-   inout      vd;
-   inout      gd;
-   input      delay_lclkr;
-   input      clk;
-   input      rst;
-   input      force_t;
-   input      thold_b;
-   output     dclk;
-   output[0:`NCLK_WIDTH-1]  lclk;
-
-   //  tri_lcbs
-
-   (* analysis_not_referenced="true" *)
-   wire       unused;
-
-   assign unused = vd | gd | delay_lclkr | force_t;
-
-   // No scan chain in this methodology
-   assign dclk = thold_b;
-   assign lclk = {clk, rst, {`NCLK_WIDTH-2{1'b0}}};
-endmodule

dev/verilog/trilib/tri_nand2_nlats.v

@@ -116,6 +116,6 @@ module tri_nand2_nlats(
       assign qb = (~int_dout);
       assign scanout = ZEROS;
 
-      assign unused = | {vd, gd, scanin};
+      assign unused = | {scanin};
    endgenerate
 endmodule

dev/verilog/trilib/tri_nlat.v

@@ -118,7 +118,7 @@ module tri_nlat(
       assign q_b = (~int_dout);
       assign scan_out = 1'b0;
 
-      assign unused = | {vd, gd, scan_in};
+      assign unused = | {scan_in};
    end
    endgenerate
 endmodule

dev/verilog/trilib/tri_nlat_scan.v

@@ -117,7 +117,7 @@ module tri_nlat_scan(
       assign q_b = (~int_dout);
       assign scan_out = ZEROS;
 
-      assign unused = | {vd, gd, scan_in};
+      assign unused = | {scan_in};
    end
    endgenerate
 endmodule

dev/verilog/trilib/tri_plat.v

@@ -52,11 +52,6 @@ module tri_plat (vd, gd, clk, rst, flush, din, q);
    // tri_plat
    reg  [OFFSET:OFFSET+WIDTH-1]  int_dout;
 
-   (* analysis_not_referenced="true" *)
-   wire                          unused;
-   assign unused = | {vd, gd};
-
-
    always @ (posedge clk)
      begin
  	int_dout <= din;

dev/verilog/trilib/tri_regk.v

@@ -100,7 +100,7 @@ module tri_regk (
 
      assign scout = {WIDTH{1'b0}};
 
-     assign unused = | {vd, gd, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin};
+     assign unused = | {d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin};
 
    endgenerate
 

dev/verilog/trilib/tri_regs.v

@@ -86,7 +86,7 @@ module tri_regs (
 
       assign scout = {WIDTH{1'b0}};
 
-      assign unused = |{vd, gd, delay_lclkr, scin};
+      assign unused = | {delay_lclkr, scin};
 
    endgenerate
 

dev/verilog/trilib/tri_rlmlatch_p.v

@@ -85,7 +85,7 @@ module tri_rlmlatch_p (vd, gd, clk, rst, act, force_t, thold_b, d_mode, sg, dela
 
      assign scout = 0;
 
-     assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd;
+     assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin;
 
    endgenerate
 endmodule

dev/verilog/trilib/tri_rlmreg_p.v

@@ -92,7 +92,7 @@ module tri_rlmreg_p (vd, gd, clk, rst, act, force_t, thold_b, d_mode, sg, delay_
 
      assign scout = {WIDTH{1'b0}};
 
-     assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd;
+     assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b;
      assign unused[1:WIDTH] = scin;
 
    endgenerate

dev/verilog/trilib/tri_scom_addr_decode.v

@@ -81,13 +81,6 @@ module tri_scom_addr_decode(
 //=====================================================================
    wire   [0:ADDR_SIZE-1]       	address;
 
-
-// Don't reference unused inputs:
-(* analysis_not_referenced="true" *)
-   wire                   		unused;
-   assign unused = vd | gd;
-
-
 //=====================================================================
    generate
      begin : decode_it

dev/verilog/trilib/tri_slat_scan.v

@@ -71,7 +71,7 @@ module tri_slat_scan(
    (* analysis_not_referenced="true" *)
    wire                           unused;
 
-   assign unused = | {vd, gd, dclk, lclk, scan_in};
+   assign unused = | {dclk, lclk, scan_in};
 
    assign scan_out = ZEROS;
    assign q = initv;

dev/verilog/work/xu.v

@@ -666,8 +666,8 @@ module xu(
    // Power signals
    wire 			   vdd;
    wire 			   gnd;
-   assign vdd = 1'b1;
-   assign gnd = 1'b0;
+   //assign vdd = 1'b1;
+   //assign gnd = 1'b0;
 
    localparam                                              AXU_TARGET_ENC = `AXU_SPARE_ENC + `GPR_POOL_ENC + `THREADS_POOL_ENC;