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1 # © IBM Corp. 2022
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2 # Licensed under and subject to the terms of the CC-BY 4.0
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3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
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4 # Additional rights, including the right to physically implement a softcore
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5 # that is compliant with the required sections of the Power ISA
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6 # Specification, will be available at no cost via the OpenPOWER Foundation.
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7 # This README will be updated with additional information when OpenPOWER's
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8 # license is available.
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9
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10 # boot kernel
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11 # resets to 32BE
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12 # set up translations for starting bios (inc. BE/LE)
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13 # copy modifiable rom data to ram - or do in bios?
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14 # set up msr for running bios (inc. 32/64)
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15 # jump to bios
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16
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17
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18 .include "defines.s"
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1 # © IBM Corp. 2020
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2 # Licensed under and subject to the terms of the CC-BY 4.0
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3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
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4 # Additional rights, including the right to physically implement a softcore
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5 # that is compliant with the required sections of the Power ISA
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6 # Specification, will be available at no cost via the OpenPOWER Foundation.
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7 # This README will be updated with additional information when OpenPOWER's
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8 # license is available.
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9
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10 #-----------------------------------------
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11 # Defines
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12 #-----------------------------------------
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13
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14 # Regs
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15
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16 .set r0, 0
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17 .set r1, 1
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18 .set r2, 2
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19 .set r3, 3
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20 .set r4, 4
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21 .set r5, 5
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22 .set r6, 6
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23 .set r7, 7
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24 .set r8, 8
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25 .set r9, 9
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26 .set r10,10
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27 .set r11,11
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28 .set r12,12
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29 .set r13,13
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30 .set r14,14
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31 .set r15,15
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32 .set r16,16
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33 .set r17,17
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34 .set r18,18
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35 .set r19,19
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36 .set r20,20
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37 .set r21,21
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38 .set r22,22
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39 .set r23,23
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40 .set r24,24
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41 .set r25,25
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42 .set r26,26
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43 .set r27,27
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44 .set r28,28
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45 .set r29,29
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46 .set r30,30
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47 .set r31,31
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48
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49 .set f0, 0
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50 .set f1, 1
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51 .set f2, 2
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52 .set f3, 3
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53 .set f4, 4
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54 .set f5, 5
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55 .set f6, 6
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56 .set f7, 7
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57 .set f8, 8
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58 .set f9, 9
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59 .set f10,10
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60 .set f11,11
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61 .set f12,12
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62 .set f13,13
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63 .set f14,14
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64 .set f15,15
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65 .set f16,16
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66 .set f17,17
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67 .set f18,18
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68 .set f19,19
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69 .set f20,20
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70 .set f21,21
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71 .set f22,22
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72 .set f23,23
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73 .set f24,24
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74 .set f25,25
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75 .set f26,26
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76 .set f27,27
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77 .set f28,28
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78 .set f29,29
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79 .set f30,30
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80 .set f31,31
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81
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82 .set cr0, 0
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83 .set cr1, 1
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84 .set cr2, 2
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85 .set cr3, 3
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86 .set cr4, 4
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87 .set cr5, 5
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88 .set cr6, 6
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89 .set cr7, 7
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90
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91 # SPR numbers
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92
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93 .set srr0, 26
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94 .set srr1, 27
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95 .set dar, 19
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96 .set dsisr, 18
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97 .set epcr, 307
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98 .set tar, 815
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99
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100 .set dbsr, 304
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101 .set dbcr0, 308
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102 .set dbcr1, 309
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103 .set dbcr2, 310
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104 .set dbcr3, 848
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105
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106 .set ivpr, 63
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107
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108 .set iucr0, 1011
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109 .set iucr1, 883
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110 .set iucr2, 884
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111
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112 .set iudbg0, 888
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113 .set iudbg1, 889
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114 .set iudbg2, 890
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115 .set iulfsr, 891
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116 .set iullcr, 892
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117
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118 .set mmucr0, 1020
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119 .set mmucr1, 1021
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120 .set mmucr2, 1022
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121 .set mmucr3, 1023
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122
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123 .set tb, 268
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124 .set tbl, 284
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125 .set tbh, 285
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126
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127 .set dec, 22
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128 .set udec, 550
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129 .set tsr, 336
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130 .set tcr, 340
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131
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132 .set xucr0, 1014
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133 .set xucr1, 851
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134 .set xucr2, 1016
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135 .set xucr3, 852
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136 .set xucr4, 853
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137
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138 .set tens, 438
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139 .set tenc, 439
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140 .set tensr, 437
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141
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142 .set pid, 48
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143 .set pir, 286
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144 .set pvr, 287
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145 .set tir, 446
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146
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147 #.set sprg0,
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148 #.set sprg1,
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149 #.set sprg2,
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150 .set sprg3, 259
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19
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20 .macro load32 rx,v
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21 li \rx,0
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22 oris \rx,\rx,\v>>16
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23 ori \rx,\rx,\v&0x0000FFFF
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24 .endm
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25
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26 .macro load16swiz rx,v
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27 li \rx,0
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28 ori \rx,\rx,(\v<<8)&0xFF00
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29 ori \rx,\rx,(\v>>8)&0x00FF
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30 .endm
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31
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32 # constants from linker script, or defsym
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33
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34 .ifdef BIOS_32
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35 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
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36 .set BIOS_MSR,0x0002B000
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37 .else
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38 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
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39 .set BIOS_MSR,0x8002B000
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40 .endif
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41
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42 #wtf this should to be done in bios based on the tst
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43 # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw
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44 .ifdef BIOS_LE
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45 .set BIOS_ERATW2,0x000000BF
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46 .else
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47 .set BIOS_ERATW2,0x0000003F
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48 .endif
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49
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50 # bios might be able to use one stack during thread startup if careful
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51 .ifndef BIOS_STACK_0
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52 .set BIOS_STACK_0,_stack_0
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53 .endif
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54
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55 .ifndef BIOS_STACK_1
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56 .set BIOS_STACK_1,_stack_1
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57 .endif
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58
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59 #wtf get rid of this and just make the low 1G a single erat entry - it can be fixed up by bios late
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60 .ifndef BIOS_START
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61 .set BIOS_START,0x00010000
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62 .endif
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63
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64 .section .text
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65
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66 .global _start
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67
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68 .org 0x000
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69 _start:
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70 int_000:
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71 0000 48000400 b boot_start
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72
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73 .ifdef TST_END
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74 # tst ends with ba here, which switches to priv and jumps to tst_end
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75 0004 44000002 sc
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76 .endif
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77
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78 # critical input
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79 0008 00000000 .org 0x020
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79 00000000
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79 00000000
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79 00000000
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79 00000000
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80 int_020:
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81 .ifdef INT_UNHANDLED
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82 0020 48000000 b int_unhandled
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83 .else
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84 b .
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85 .endif
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86
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87 # debug
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88 0024 00000000 .org 0x040
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88 00000000
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88 00000000
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88 00000000
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88 00000000
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89 int_040:
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90 0040 48000000 b .
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91
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92 # dsi
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93 0044 00000000 .org 0x060
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93 00000000
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93 00000000
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93 00000000
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93 00000000
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94 int_060:
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95 0060 48000000 b .
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96
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97 # isi
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98 0064 00000000 .org 0x080
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98 00000000
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98 00000000
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98 00000000
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98 00000000
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99 int_080:
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100 0080 48000000 b .
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101
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102 # external
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103 0084 00000000 .org 0x0A0
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103 00000000
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103 00000000
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103 00000000
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103 00000000
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104 int_0A0:
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105 00a0 48000000 b .
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106
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107 # alignment
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108 00a4 00000000 .org 0x0C0
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108 00000000
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108 00000000
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108 00000000
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108 00000000
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109 int_0C0:
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110 00c0 48000000 b .
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111
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112 # program
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113 00c4 00000000 .org 0x0E0
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113 00000000
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113 00000000
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113 00000000
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113 00000000
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114 int_0E0:
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115 00e0 48000000 b .
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116
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117 # fp unavailable
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118 00e4 00000000 .org 0x100
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118 00000000
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118 00000000
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118 00000000
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118 00000000
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119 int_100:
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120 0100 48000000 b .
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121
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122 # sc
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123 0104 00000000 .org 0x120
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123 00000000
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123 00000000
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123 00000000
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123 00000000
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124 int_120:
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125 .ifdef TST_END
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126 # tst results haven't been saved yet; if want to call bios, need to save r1, then restore or set st
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127 0120 48000000 b tst_end
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128 .else
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129 .ifdef INT_SC
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130 # lev is in 20:26, but supposed to use scv now
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131 li r3,0
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132 mfsrr0 r4
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133 b int_sc
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134 .else
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135 .ifdef INT_UNHANDLED
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136 b int_unhandled
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137 .else
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138 b .
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139 .endif
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140 .endif
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141 .endif
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142
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143 # apu unavailable
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144 0124 00000000 .org 0x140
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144 00000000
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144 00000000
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144 00000000
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144 00000000
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145 int_140:
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146 0140 48000000 b .
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147
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148 # decrementer
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149 0144 00000000 .org 0x160
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149 00000000
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149 00000000
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149 00000000
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149 00000000
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150 int_160:
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151 0160 48000000 b .
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152
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153 # fit
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154 0164 00000000 .org 0x180
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154 00000000
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154 00000000
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154 00000000
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154 00000000
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155 int_180:
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156 0180 48000000 b .
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157
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158 # watchdog
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159 0184 00000000 .org 0x1A0
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159 00000000
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159 00000000
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159 00000000
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159 00000000
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160 int_1A0:
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161 01a0 48000000 b .
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162
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163 # dtlb
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164 01a4 00000000 .org 0x1C0
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164 00000000
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164 00000000
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164 00000000
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164 00000000
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165 int_1C0:
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166 01c0 48000000 b .
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167
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168 # itlb
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169 01c4 00000000 .org 0x1E0
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169 00000000
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169 00000000
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169 00000000
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169 00000000
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170 int_1E0:
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171 01e0 48000000 b .
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172
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173 # vector unavailable
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174 01e4 00000000 .org 0x200
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174 00000000
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174 00000000
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174 00000000
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174 00000000
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175 int_200:
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176 0200 48000000 b .
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177
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178 #
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179 0204 00000000 .org 0x220
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179 00000000
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179 00000000
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179 00000000
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179 00000000
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180 int_220:
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181 0220 48000000 b .
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182
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183 #
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184 0224 00000000 .org 0x240
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184 00000000
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184 00000000
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184 00000000
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184 00000000
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185 int_240:
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186 0240 48000000 b .
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187
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188 #
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189 0244 00000000 .org 0x260
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189 00000000
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189 00000000
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189 00000000
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189 00000000
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190 int_260:
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191 0260 48000000 b .
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192
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193 # doorbell
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194 0264 00000000 .org 0x280
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194 00000000
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194 00000000
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194 00000000
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194 00000000
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195 int_280:
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196 0280 48000000 b .
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197
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198 # doorbell critical
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199 0284 00000000 .org 0x2A0
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199 00000000
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199 00000000
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199 00000000
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199 00000000
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200 int_2A0:
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201 02a0 48000000 b .
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202
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203 # doorbell guest
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204 02a4 00000000 .org 0x2C0
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204 00000000
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204 00000000
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204 00000000
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204 00000000
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205 int_2C0:
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206 02c0 48000000 b .
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207
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208 # doorbell guest critical
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209 02c4 00000000 .org 0x2E0
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209 00000000
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209 00000000
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209 00000000
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209 00000000
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210 int_2E0:
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211 02e0 48000000 b .
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212
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213 # hvsc
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214 02e4 00000000 .org 0x300
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214 00000000
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214 00000000
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214 00000000
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214 00000000
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215 int_300:
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216 0300 48000000 b .
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217
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218 # hvpriv
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219 0304 00000000 .org 0x320
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219 00000000
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219 00000000
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219 00000000
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219 00000000
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220 int_320:
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221 0320 48000000 b .
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222
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223 # lrat
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224 0324 00000000 .org 0x340
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224 00000000
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224 00000000
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224 00000000
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224 00000000
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225 int_340:
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226 0340 48000000 b .
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227
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228 # -------------------------------------------------------------------------------------------------
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229 # initial translation
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230 # both erats:
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231 # 00000000 64K: (rom, BE)
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232 # 00010000 64K: (ram, BE or LE)
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233 #
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234 0344 00000000 .org 0x400
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234 00000000
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234 00000000
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234 00000000
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234 00000000
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235 boot_start:
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236
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237 0400 7CBE6AA6 mfspr r5,tir # who am i?
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238 0404 2C250000 cmpdi r5,0x00 # skip unless T0
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239 0408 408200E0 bne init_t123
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240
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241 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
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242
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243 # derat 31 @00000000
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244 0410 3800001F li r0,0x001F # entry #31
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245 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
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246 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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247 041c 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
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248
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249 0420 7C7CFBA6 mtspr mmucr0,r3
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250 0424 7C4011A6 eratwe r2,r0,2
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251 0428 7C8009A6 eratwe r4,r0,1
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252 042c 7D0001A6 eratwe r8,r0,0
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253 0430 4C00012C isync
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254
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255 0434 39400000 load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
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255 654A0000
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255 614A003F
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256
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257 # derat 30 @<BIOS_START>
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258 0440 3800001E li r0,0x001E # entry #30
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259 0444 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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259 64840001
|
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259 60840000
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260 0450 39000000 load32 r8,BIOS_START
|
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260 65080001
|
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260 61080000
|
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261 045c 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
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262
|
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263 0460 7D4011A6 eratwe r10,r0,2
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264 0464 7C8009A6 eratwe r4,r0,1
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265 0468 7D0001A6 eratwe r8,r0,0
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266 046c 4C00012C isync
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267
|
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268 0470 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
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269
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270 # ierat 15 @00000000
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271 0474 3800000F li r0,0x000F # entry #15
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272 0478 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
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273 047c 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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274 0480 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
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275
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276 0484 7C7CFBA6 mtspr mmucr0,r3
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277 0488 7C4011A6 eratwe r2,r0,2
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278 048c 7C8009A6 eratwe r4,r0,1
|
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279 0490 7D0001A6 eratwe r8,r0,0
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280 0494 4C00012C isync
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281
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282 # *** leave the init'd entry 14 for MT access to FFFFFFC0
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283 # ierat 13 @<BIOS_START>
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284 0498 3800000D li r0,0x000D # entry #13
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285 049c 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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285 64840001
|
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285 60840000
|
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286 04a8 39000000 load32 r8,BIOS_START
|
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286 65080001
|
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286 61080000
|
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287 04b4 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
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288
|
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289 04b8 7D4011A6 eratwe r10,r0,2
|
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290 04bc 7C8009A6 eratwe r4,r0,1
|
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291 04c0 7D0001A6 eratwe r8,r0,0
|
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292 04c4 4C00012C isync
|
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293
|
|
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294 04c8 48000004 b init_t0
|
|
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|
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295
|
|
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|
|
296 # -------------------------------------------------------------------------------------------------
|
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|
|
297 # init
|
|
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|
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298 #
|
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299
|
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300 # T0
|
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301
|
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302 init_t0:
|
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303
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304 # set up BIOS msr
|
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305
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306 04cc 39400000 load32 r10,BIOS_MSR
|
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306 654A8002
|
|
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|
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306 614AB000
|
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307 04d8 7D400124 mtmsr r10
|
|
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|
|
308 04dc 4C00012C isync
|
|
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|
|
309 # can't use load32 unless you can .set BIOS_STACK_0 to the linked value
|
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|
|
310 # load32 r1,BIOS_STACK_0 # @stack_0
|
|
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|
|
311 # this ignores def
|
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|
312 # lis r1,_stack_0@h
|
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313 # ori r1,r1,_stack_0@l
|
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|
|
314 # this requires data load
|
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|
315 04e0 80200000 lwz r1,stack_0(r0)
|
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|
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316
|
|
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|
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317 04e4 48000020 b boot_complete
|
|
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|
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318
|
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319 # except T0
|
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320
|
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|
321 init_t123:
|
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|
|
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322
|
|
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|
|
323 # set up BIOS msr
|
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|
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324
|
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325 04e8 39400000 load32 r10,BIOS_MSR
|
|
|
|
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325 654A8002
|
|
|
|
|
325 614AB000
|
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326 04f4 7D400124 mtmsr r10
|
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327 04f8 4C00012C isync
|
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|
|
328 # check tir if more than 2 threads possible
|
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|
|
329 04fc 80200000 lwz r1,stack_1(r0)
|
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|
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330
|
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|
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331 0500 48000004 b boot_complete
|
|
|
|
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332
|
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|
|
333 # -------------------------------------------------------------------------------------------------
|
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|
|
334 boot_complete:
|
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|
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335
|
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|
|
336 # set up thread and hop to it
|
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337
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338 0504 3C600000 lis r3,main@h
|
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339 0508 60630000 ori r3,r3,main@l
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|
340 050c 7C6903A6 mtctr r3
|
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341 0510 7C7E6AA6 mfspr r3,tir # who am i?
|
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|
|
342 0514 4E800421 bctrl
|
|
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|
|
343 0518 480002E4 b kernel_return
|
|
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|
|
344
|
|
|
|
|
345 # -------------------------------------------------------------------------------------------------
|
|
|
|
|
346
|
|
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|
|
347 .ifdef TST_PASSFAIL
|
|
|
|
|
348 .global tst_pass
|
|
|
|
|
349 .global tst_fail
|
|
|
|
|
350
|
|
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|
|
351 051c 00000000 .org 0x7F0
|
|
|
|
|
351 00000000
|
|
|
|
|
351 00000000
|
|
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|
|
351 00000000
|
|
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|
|
351 00000000
|
|
|
|
|
352 tst_pass:
|
|
|
|
|
353 07f0 48000000 b .
|
|
|
|
|
354
|
|
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|
|
355 .org 0x7F4
|
|
|
|
|
356 tst_fail:
|
|
|
|
|
357 07f4 48000000 b .
|
|
|
|
|
358 .endif
|
|
|
|
|
359
|
|
|
|
|
360 07f8 00000000 .org 0x7FC
|
|
|
|
|
361 kernel_return:
|
|
|
|
|
362 07fc 48000000 b .
|
|
|
|
|
363
|
|
|
|
|
364 # dec
|
|
|
|
|
365 .org 0x800
|
|
|
|
|
366 int_800:
|
|
|
|
|
367 0800 48000000 b .
|
|
|
|
|
368
|
|
|
|
|
369 # perf
|
|
|
|
|
370 0804 00000000 .org 0x820
|
|
|
|
|
370 00000000
|
|
|
|
|
370 00000000
|
|
|
|
|
370 00000000
|
|
|
|
|
370 00000000
|
|
|
|
|
371 int_820:
|
|
|
|
|
372 0820 48000000 b .
|
|
|
|
|
373
|
|
|
|
|
374 0824 00000000 .org 0x8F0
|
|
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|
|
374 00000000
|
|
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|
|
374 00000000
|
|
|
|
|
374 00000000
|
|
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|
|
374 00000000
|
|
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|
|
375 .section .rodata
|
|
|
|
|
376 0000 00000000 stack_0: .long BIOS_STACK_0
|
|
|
|
|
377 0004 00000000 stack_1: .long BIOS_STACK_1
|
