get rid of some gen begin/end msgs

dev/verilog/trilib/tri_128x168_1w_0.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -184,7 +184,6 @@ module tri_128x168_1w_0(
 
 
    generate
-   begin
      assign tidn = 1'b0;
 
      if (addressbus_width < ramb_base_addr)
@@ -244,7 +243,6 @@ module tri_128x168_1w_0(
        end  //ax
        assign data_out[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
      end  //aw
-   end
    endgenerate
 
    assign abst_scan_out = abst_scan_in;

dev/verilog/trilib/tri_256x144_8w_1r1w.v

@@ -233,7 +233,7 @@ wire [0:scan_right]                        sov;
 (* analysis_not_referenced="true" *)
 wire                                       unused;
 
-generate begin
+generate
   // Read/Write Port Address Generate
   assign ramb_rd_addr[11:15] = 5'b0;
   assign ramb_wr_addr[11:15] = 5'b0;
@@ -385,7 +385,6 @@ generate begin
   assign repr_scan_out = 1'b0;
   assign bo_pc_failout = 4'h0;
   assign bo_pc_diagloop = 4'h0;
-end
 endgenerate
 
 assign unused = |({
@@ -461,8 +460,8 @@ tri_rlmreg_p #(.WIDTH(ways), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
    .dout(rd_act_q)
 );
 
-generate begin : wayReg
-  genvar way;
+generate
+  //genvar way;
   for (way=0; way<ways; way=way+1) begin : wayReg
     // ###############################################################
     // ## LCB
@@ -498,7 +497,6 @@ generate begin : wayReg
        .qb(data_out_b_q[(way*port_bitwidth):((way+1)*port_bitwidth)-1])
     );
   end
-end
 endgenerate
 
 assign siv[0:(2*port_bitwidth)-1]                 = {sov[1:(2*port_bitwidth)-1], func_scan_in[0]};

dev/verilog/trilib/tri_64x72_1r1w.v

@@ -196,7 +196,6 @@ module tri_64x72_1r1w(
    wire                                unused;
 
    generate
-   begin
      assign tidn = 72'b0;
      assign clk = nclk[0];
      assign clk2x = nclk[2];
@@ -312,6 +311,6 @@ module tri_64x72_1r1w(
      assign bo_pc_diagloop = 1'b0;
 
      assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});
-  end
+
   endgenerate
 endmodule

dev/verilog/trilib/tri_aoi22.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -57,17 +57,11 @@ module tri_aoi22(
    wire [0:WIDTH-1]    outB;
 
    generate
-      begin : t
 	 for (i = 0; i < WIDTH; i = i + 1)
 	   begin : w
-
 	      and I0(outA[i], a0[i], a1[i]);
 	      and I1(outB[i], b0[i], b1[i]);
 	      nor I2(y[i], outA[i], outB[i]);
-
-
-	   end // block: w
       end
-
    endgenerate
 endmodule

dev/verilog/trilib/tri_aoi22_nlats_wlcb.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -94,7 +94,6 @@ module tri_aoi22_nlats_wlcb(
    parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};
 
    generate
-   begin
       wire                        sreset;
       wire [0:WIDTH-1]            int_din;
       wire [0:WIDTH-1]            din;
@@ -140,6 +139,5 @@ module tri_aoi22_nlats_wlcb(
       assign scout = ZEROS;
 
       assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk) | (|scin);
-   end
    endgenerate
 endmodule

dev/verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -155,7 +155,6 @@ module tri_cam_32x143_1r1w1c_matchline(
                                 {addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]}));
 
    generate
-   begin
      if (NUM_PGSIZES == 8)
      begin : numpgsz8
        // tie off unused signals
@@ -466,6 +465,5 @@ module tri_cam_32x143_1r1w1c_matchline(
                     thdid_match &       //  ThdID compare
                     pid_match &         //  PID compare
                     entry_v;            //  Valid
-   end
    endgenerate
 endmodule

dev/verilog/trilib/tri_nand2.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -50,14 +50,8 @@ module tri_nand2(
    genvar 	       i;
 
    generate
-      begin : t
-	 for (i = 0; i < WIDTH; i = i + 1)
-	   begin : w
-
+	   for (i = 0; i < WIDTH; i = i + 1) begin : w
 	      nand I0(y[i], a[i], b[i]);
-
-	   end // block: w
-      end
-
+	   end
    endgenerate
 endmodule

dev/verilog/trilib/tri_nand2_nlats.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -73,7 +73,6 @@ module tri_nand2_nlats(
    parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};
 
    generate
-   begin
       wire                          sreset;
       wire [0:WIDTH-1]              int_din;
       reg [0:WIDTH-1]               int_dout;
@@ -107,7 +106,6 @@ module tri_nand2_nlats(
       assign vthold_b = {WIDTH{d2clk}};
       assign vthold = {WIDTH{~d2clk}};
 
-
       always @(posedge lclk[0])
       begin: l
         int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
@@ -116,6 +114,5 @@ module tri_nand2_nlats(
       assign scanout = ZEROS;
 
       assign unused = | {vd, gd, lclk, scanin};
-   end
    endgenerate
 endmodule

dev/verilog/trilib/tri_nand3.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -52,15 +52,8 @@ module tri_nand3(
    genvar 	       i;
 
    generate
-      begin : t
-	 for (i = 0; i < WIDTH; i = i + 1)
-	   begin : w
-
-      	      nand I0(y[i], a[i], b[i], c[i]);
-
-
-	   end // block: w
-      end
-
+	   for (i = 0; i < WIDTH; i = i + 1) begin : w
+         nand I0(y[i], a[i], b[i], c[i]);
+	   end
    endgenerate
 endmodule

dev/verilog/trilib/tri_nand4.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -49,19 +49,11 @@ module tri_nand4(
    input [0:WIDTH-1]   b;
    input [0:WIDTH-1]   c;
    input [0:WIDTH-1]   d;
-   // tri_nand3
    genvar 	       i;
 
    generate
-      begin : t
-	 for (i = 0; i < WIDTH; i = i + 1)
-	   begin : w
-
+	   for (i = 0; i < WIDTH; i = i + 1) begin : w
       	      nand I0(y[i], a[i], b[i], c[i], d[i]);
-
-
-	   end // block: w
-      end
-
+	   end
    endgenerate
 endmodule

dev/verilog/trilib/tri_nor3.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -52,14 +52,8 @@ module tri_nor3(
    genvar 	       i;
 
    generate
-      begin : t
-	 for (i = 0; i < WIDTH; i = i + 1)
-	   begin : w
-
+	   for (i = 0; i < WIDTH; i = i + 1) begin : w
 	      nor I0(y[i], a[i], b[i], c[i]);
-
-	   end // block: w
-      end
-
+	   end
    endgenerate
 endmodule

dev/verilog/trilib/tri_oai21.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -53,15 +53,12 @@ module tri_oai21(
    wire [0:WIDTH-1]    outA;
 
    generate
-      begin : t
-	 for (i = 0; i < WIDTH; i = i + 1)
-	   begin : w
+	   for (i = 0; i < WIDTH; i = i + 1) begin : w
 
 	      or   I0(outA[i], a0[i], a1[i]);
 	      nand I2(y[i], outA[i], b0[i]);
 
-	   end // block: w
-      end
+	   end
 
    endgenerate
 endmodule

dev/verilog/trilib/tri_rlmlatch_p.v

@@ -14,17 +14,17 @@
 //    necessary for implementation of the Work that are available from OpenPOWER
 //    via the Power ISA End User License Agreement (EULA) are explicitly excluded
 //    hereunder, and may be obtained from OpenPOWER under the terms and conditions
-//    of the EULA.  
+//    of the EULA.
 //
 // Unless required by applicable law or agreed to in writing, the reference design
 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
 // for the specific language governing permissions and limitations under the License.
-// 
+//
 // Additional rights, including the ability to physically implement a softcore that
 // is compliant with the required sections of the Power ISA Specification, are
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
 `timescale 1 ns / 1 ns
 
@@ -65,7 +65,6 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl
    // tri_rlmlatch_p
 
    generate
-   begin
      wire                  sreset;
      wire                  int_din;
      reg                   int_dout;
@@ -108,6 +107,6 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl
      assign scout = 1'b0;
 
      assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk);
-   end
+
    endgenerate
 endmodule

dev/verilog/trilib/tri_rlmreg_p.v

@@ -72,7 +72,6 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr
    // tri_rlmreg_p
 
    generate
-   begin
      wire                       sreset;
      wire [0:WIDTH-1]           int_din;
      reg [0:WIDTH-1]            int_dout;
@@ -131,6 +130,6 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr
 
      assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk);
      assign unused[1:WIDTH] = scin;
-   end
+
    endgenerate
 endmodule