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@ -14,17 +14,17 @@
@@ -14,17 +14,17 @@
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// necessary for implementation of the Work that are available from OpenPOWER |
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded |
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions |
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// of the EULA. |
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// of the EULA. |
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// |
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// Unless required by applicable law or agreed to in writing, the reference design |
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License |
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// for the specific language governing permissions and limitations under the License. |
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// |
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// |
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// Additional rights, including the ability to physically implement a softcore that |
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// is compliant with the required sections of the Power ISA Specification, are |
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be |
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org. |
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org. |
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`timescale 1 ns / 1 ns |
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@ -65,7 +65,6 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl
@@ -65,7 +65,6 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl
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// tri_rlmlatch_p |
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generate |
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begin |
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wire sreset; |
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wire int_din; |
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reg int_dout; |
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@ -108,6 +107,6 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl
@@ -108,6 +107,6 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl
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assign scout = 1'b0; |
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assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk); |
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end |
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endgenerate |
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endmodule |
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