openpowerwtf 4 months ago
parent
commit
1d003f8822
  1. 18
      dev/verilog/a2node/a2l2wb.v
  2. 25
      dev/verilog/a2node/a2owb.v

18
dev/verilog/a2node/a2l2wb.v

@ -153,8 +153,8 @@ module a2l2wb #( @@ -153,8 +153,8 @@ module a2l2wb #(
reg [0:7] err_q;

wire new_req;
wire ld_req_val;
wire st_req_val;
wire req_ld_val;
wire req_st_val;
wire req_ieq1;
wire req_le;
wire [64-`REAL_IFAR_WIDTH:63] req_adr;
@ -167,10 +167,8 @@ module a2l2wb #( @@ -167,10 +167,8 @@ module a2l2wb #(
wire idle;
wire ld_ready;
wire st_ready;

generate if (MEM_MODE == 1)
reg [0:127] mem[MEM_QW];
endgenerate
wire do_store;
wire inc_qw;

// FF
always @(posedge clk) begin
@ -215,12 +213,16 @@ endgenerate @@ -215,12 +213,16 @@ endgenerate

// internal memory
generate if (MEM_MODE == 1) begin
reg [0:127] mem[MEM_QW];
wire [0:127] mem_dat_int;


always @(posedge clk) begin
if (mem_wr_val) begin
mem[req_adr] = mem_wr_data;
mem[req_adr] = mem_wr_dat;
end
end
assign mem_dat = mem[req_adr];
assign mem_dat_int = mem[req_adr];
end
endgenerate


25
dev/verilog/a2node/a2owb.v

@ -136,8 +136,33 @@ module a2owb ( @@ -136,8 +136,33 @@ module a2owb (

wire [0:`THREADS-1] an_ac_stcx_complete;
wire [0:`THREADS-1] an_ac_stcx_pass;
wire an_ac_icbi_ack;
wire [0:1] an_ac_icbi_ack_thread;
wire an_ac_back_inv_lbit;
wire an_ac_back_inv_gs;
wire an_ac_back_inv_ind;
wire ac_an_back_inv_reject;
wire an_ac_reld_data_vld;
wire an_ac_reld_ecc_err;
wire an_ac_reld_ecc_err_ue;
wire an_ac_reld_data_coming;
wire an_ac_reld_ditc;
wire an_ac_reld_crit_qw;
wire an_ac_reld_l1_dump;
wire an_ac_req_ld_pop;
wire an_ac_req_st_pop;
wire an_ac_req_st_gather;
wire ac_an_req_pwr_token;
wire ac_an_req;
wire ac_an_req_wimg_w;
wire ac_an_req_wimg_i;
wire ac_an_req_wimg_m;
wire ac_an_req_wimg_g;
wire ac_an_req_endian;
wire ac_an_st_data_pwr_token;
wire [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra;
wire an_ac_back_inv;
wire an_ac_back_inv_local;
wire [0:4] an_ac_back_inv_target;
wire [0:7] an_ac_back_inv_lpar_id;
wire [0:7] ac_an_lpar_id;

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