openpowerwtf 4 months ago
parent
commit
200551679c
  1. 1
      dev/verilog/trilib_clk1x/tri_144x78_2r4w.v
  2. 2
      dev/verilog/unisims/bram_model.v

1
dev/verilog/trilib_clk1x/tri_144x78_2r4w.v

@ -86,6 +86,7 @@ module tri_144x78_2r4w( @@ -86,6 +86,7 @@ module tri_144x78_2r4w(
input [64-`GPR_WIDTH:77] w_data_in_4
);

wire unused;
// sim array
reg [64-`GPR_WIDTH:77] mem[0:143];


2
dev/verilog/unisims/bram_model.v

@ -27,7 +27,7 @@ module bram_model (DIA, DIB, ENA, ENB, WEA, WEB, SSRA, SSRB, CLKA, CLKB, ADDRA, @@ -27,7 +27,7 @@ module bram_model (DIA, DIB, ENA, ENB, WEA, WEB, SSRA, SSRB, CLKA, CLKB, ADDRA,
initial begin
integer i;
for (i = 0; i < 2**addr_w; i = i + 1)
MEM[i] <= 0;
MEM[i] = 0;
end

always @(posedge CLKA, posedge CLKB) begin: BRAM_MODEL

Loading…
Cancel
Save