%Warning-PINMISSING: verilog/a2o_litex/a2owb.v:253:3: Cell has missing pin: 'ac_an_event_bus1'
253 | c c0(
| ^~
... For warning description see https://verilator.org/warn/PINMISSING?v=4.225
... For warning description see https://verilator.org/warn/PINMISSING?v=4.224
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Warning-PINMISSING: verilog/work/c.v:1815:4: Cell has missing pin: 'iu_rv_iu6_t0_i0_s1_a'
1815 | iuq0(
@ -1956,6 +1956,14 @@
verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v
verilog/work/c.v:4463:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
%Warning-IMPLICIT: verilog/trilib_clk1x/tri_64x72_1r1w.v:214:11: Signal definition not found, creating implicitly: 'clk'
: ... Suggested alternative: 'nclk'
214 | assign clk = nclk[0];
| ^~~
verilog/work/iuq_btb.v:170:1: ... note: In file included from iuq_btb.v
verilog/work/iuq.v:1375:1: ... note: In file included from iuq.v
verilog/work/c.v:1817:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
%Warning-WIDTH: verilog/trilib/tri_slat_scan.v:68:35: Operator VAR 'initv' expects 16 bits on the Initial value, but Initial value's VARREF 'INIT' generates 32 bits.
: ... In instance a2owb.c0.lq0.ctl.derat.bcfg_epn_32to47_latch
68 | parameter [0:WIDTH-1] initv = INIT;
@ -2851,6 +2859,66 @@
verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v
verilog/work/c.v:1817:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
%Warning-WIDTH: verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v:2537:13: Bit extraction of array[15:0] requires 4 bit index, not 9 bits.
: ... In instance a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_ierat0.ierat_cam
%Warning-MULTIDRIVEN: verilog/unisims/bram_model.v:22:24: Signal has multiple driving blocks with different clocking: 'unnamedblk1.ra[3].bram_model.MEM'
: ... In instance a2owb.c0.lq0.ctl.dc32Kdir64B.arr.arr0_A
verilog/unisims/bram_model.v:44:13: ... Location of first driving block
44 | MEM[ADDRB] <= DIB;
| ^~~
verilog/unisims/RAMB16_S36_S36.v:72:1: ... note: In file included from RAMB16_S36_S36.v
verilog/trilib/tri_128x168_1w_0.v:225:1: ... note: In file included from tri_128x168_1w_0.v
verilog/work/mmq.v:3813:1: ... note: In file included from mmq.v
verilog/work/c.v:4173:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/unisims/bram_model.v:36:13: ... Location of other driving block
36 | MEM[ADDRA] <= DIA;
| ^~~
%Warning-MULTIDRIVEN: verilog/unisims/bram_model.v:22:24: Signal has multiple driving blocks with different clocking: 'unnamedblk1.ra[2].bram_model.MEM'
: ... In instance a2owb.c0.lq0.ctl.dc32Kdir64B.arr.arr0_A
verilog/unisims/bram_model.v:44:13: ... Location of first driving block
44 | MEM[ADDRB] <= DIB;
| ^~~
verilog/unisims/RAMB16_S36_S36.v:72:1: ... note: In file included from RAMB16_S36_S36.v
verilog/trilib/tri_128x168_1w_0.v:225:1: ... note: In file included from tri_128x168_1w_0.v
verilog/work/mmq.v:3813:1: ... note: In file included from mmq.v
verilog/work/c.v:4173:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/unisims/bram_model.v:36:13: ... Location of other driving block
36 | MEM[ADDRA] <= DIA;
| ^~~
%Warning-MULTIDRIVEN: verilog/unisims/bram_model.v:22:24: Signal has multiple driving blocks with different clocking: 'unnamedblk1.ra[1].bram_model.MEM'
: ... In instance a2owb.c0.lq0.ctl.dc32Kdir64B.arr.arr0_A
verilog/unisims/bram_model.v:44:13: ... Location of first driving block
44 | MEM[ADDRB] <= DIB;
| ^~~
verilog/unisims/RAMB16_S36_S36.v:72:1: ... note: In file included from RAMB16_S36_S36.v
verilog/trilib/tri_128x168_1w_0.v:225:1: ... note: In file included from tri_128x168_1w_0.v
verilog/work/mmq.v:3813:1: ... note: In file included from mmq.v
verilog/work/c.v:4173:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/unisims/bram_model.v:36:13: ... Location of other driving block
36 | MEM[ADDRA] <= DIA;
| ^~~
%Warning-MULTIDRIVEN: verilog/unisims/bram_model.v:22:24: Signal has multiple driving blocks with different clocking: 'unnamedblk1.ra[0].bram_model.MEM'
: ... In instance a2owb.c0.lq0.ctl.dc32Kdir64B.arr.arr0_A
verilog/unisims/bram_model.v:44:13: ... Location of first driving block
44 | MEM[ADDRB] <= DIB;
| ^~~
verilog/unisims/RAMB16_S36_S36.v:72:1: ... note: In file included from RAMB16_S36_S36.v
verilog/trilib/tri_128x168_1w_0.v:225:1: ... note: In file included from tri_128x168_1w_0.v
verilog/work/mmq.v:3813:1: ... note: In file included from mmq.v
verilog/work/c.v:4173:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/unisims/bram_model.v:36:13: ... Location of other driving block
36 | MEM[ADDRA] <= DIA;
| ^~~
%Warning-UNOPTFLAT: verilog/work/iuq_ic_ierat.v:93:38: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.__Vcellout__iuq_ic_ierat0__time_scan_out'
: ... In instance a2owb.c0.iuq0
93 | output time_scan_out,
| ^~~~~~~~~~~~~
verilog/work/iuq_ic.v:527:1: ... note: In file included from iuq_ic.v
verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v
verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v
verilog/work/c.v:1817:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/work/iuq_ic_ierat.v:93:38: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.__Vcellout__iuq_ic_ierat0__time_scan_out
verilog/work/iuq_ic.v:566:8: Example path: ASSIGNW
verilog/work/iuq_ic_ierat.v:91:38: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.__Vcellinp__iuq_ic_ierat0__time_scan_in
verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v:2684:25: Example path: ASSIGNW
verilog/work/iuq_ic_ierat.v:93:38: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.__Vcellout__iuq_ic_ierat0__time_scan_out
%Warning-UNOPTFLAT: verilog/work/xu_spr.v:458:34: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.xu0.spr.siv_repr'
verilog/work/pcq.v:393:1: ... note: In file included from pcq.v
verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v
verilog/work/c.v:4463:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/work/pcq_regs.v:338:26: Example path: a2owb.c0.fupc.pc0.pcq_regs.func_siv
verilog/work/pcq_regs.v:2277:87: Example path: ASSIGNW
verilog/work/pcq_regs.v:339:26: Example path: a2owb.c0.fupc.pc0.pcq_regs.func_sov[194:201]
verilog/work/pcq_regs.v:2402:34: Example path: ASSIGNW
verilog/work/pcq_regs.v:338:26: Example path: a2owb.c0.fupc.pc0.pcq_regs.func_siv
%Warning-UNOPTFLAT: verilog/trilib_clk1x/tri_512x16_1r1w_1.v:126:51: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.bht0.__Vcellinp__bht0__func_scan_in'
: ... In instance a2owb.c0.iuq0.bht0
126 | input func_scan_in;
| ^~~~~~~~~~~~
verilog/trilib/tri_bht_1024x8_1r1w.v:332:1: ... note: In file included from tri_bht_1024x8_1r1w.v
verilog/work/iuq.v:1831:1: ... note: In file included from iuq.v
verilog/work/c.v:1817:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/trilib_clk1x/tri_512x16_1r1w_1.v:126:51: Example path: a2owb.c0.iuq0.bht0.__Vcellinp__bht0__func_scan_in
verilog/trilib/tri_bht_1024x8_1r1w.v:348:17: Example path: ASSIGNW
verilog/trilib/tri_bht_1024x8_1r1w.v:220:27: Example path: a2owb.c0.iuq0.bht0.sov
verilog/trilib/tri_bht_1024x8_1r1w.v:347:17: Example path: ASSIGNW
verilog/trilib_clk1x/tri_512x16_1r1w_1.v:126:51: Example path: a2owb.c0.iuq0.bht0.__Vcellinp__bht0__func_scan_in
%Warning-UNOPTFLAT: verilog/work/iuq_ibuf.v:176:42: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.valid_out'
: ... In instance a2owb.c0.iuq0
176 | wire [0:1] valid_out;
| ^~~~~~~~~
verilog/work/iuq_slice.v:471:1: ... note: In file included from iuq_slice.v
verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v
verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v
verilog/work/c.v:1817:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/work/iuq_ibuf.v:176:42: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.valid_out
verilog/work/iuq_ibuf.v:682:22: Example path: ASSIGNW
verilog/work/iuq_ibuf.v:261:42: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.error_hole
verilog/work/iuq_ibuf.v:596:21: Example path: ASSIGNW
verilog/work/iuq_ibuf.v:176:42: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.valid_out
%Warning-UNOPTFLAT: verilog/work/iuq_ic_dir.v:566:35: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_dir0.siv'
verilog/work/rv_fx0_rvs.v:533:1: ... note: In file included from rv_fx0_rvs.v
verilog/work/rv.v:1551:1: ... note: In file included from rv.v
verilog/work/c.v:3163:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/work/rv_station.v:661:35: Example path: a2owb.c0.rv0.fx0_rvs.rvs.siv
verilog/work/rv_station.v:1827:63: Example path: ASSIGNW
verilog/work/rv_station.v:662:35: Example path: a2owb.c0.rv0.fx0_rvs.rvs.sov
verilog/work/rv_fx0_rvs.v:651:9: Example path: ASSIGNW
verilog/work/rv_fx0_rvs.v:443:30: Example path: a2owb.c0.rv0.fx0_rvs.sov
verilog/work/rv_station.v:3329:31: Example path: ASSIGNW
verilog/work/rv_station.v:661:35: Example path: a2owb.c0.rv0.fx0_rvs.rvs.siv
%Warning-UNOPTFLAT: verilog/work/iuq_bp.v:798:13: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_data_new'
verilog/work/iuq_ifetch.v:1062:1: ... note: In file included from iuq_ifetch.v
verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v
verilog/work/c.v:1817:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/work/iuq_bp.v:798:13: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_data_new
verilog/work/iuq_bp.v:1049:28: Example path: ASSIGNW
verilog/work/iuq_bp.v:815:12: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_hit
verilog/work/iuq_bp.v:1013:27: Example path: ASSIGNW
verilog/work/iuq_bp.v:791:12: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.ex5_bh0_hist
verilog/work/iuq_bp.v:996:38: Example path: ASSIGNW
verilog/work/iuq_bp.v:795:12: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_bh0_wr_data
verilog/work/iuq_bp.v:1022:36: Example path: ASSIGNW
verilog/work/iuq_bp.v:798:13: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_data_new
%Warning-UNOPTFLAT: verilog/work/iuq_ibuf.v:130:41: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q(0)'
verilog/work/iuq_slice.v:471:1: ... note: In file included from iuq_slice.v
verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v
verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v
verilog/work/c.v:1817:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/work/iuq_ibuf.v:130:41: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q(0)
verilog/work/iuq_ibuf.v:433:8: Example path: ALWAYS
verilog/work/iuq_ibuf.v:130:41: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q(0)
%Warning-UNOPTFLAT: verilog/work/iuq_ic_select.v:408:30: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_select0.thread_ready'
: ... In instance a2owb.c0.iuq0
408 | wire [0:1-1] thread_ready;
| ^~~~~~~~~~~~
verilog/work/iuq_ic.v:699:1: ... note: In file included from iuq_ic.v
verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v
verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v
verilog/work/c.v:1817:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/work/iuq_ic_select.v:408:30: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_select0.thread_ready
verilog/work/iuq_ic_select.v:572:4: Example path: ALWAYS
verilog/work/iuq_ic_select.v:400:27: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_select0.need_fetch
verilog/work/iuq_ic_select.v:686:24: Example path: ASSIGNW
verilog/work/iuq_ic_select.v:408:30: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_select0.thread_ready
%Warning-UNOPTFLAT: verilog/work/iuq_ic_miss.v:428:35: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_miss0.release_sm'
: ... In instance a2owb.c0.iuq0
428 | wire release_sm;
| ^~~~~~~~~~
verilog/work/iuq_ic.v:1019:1: ... note: In file included from iuq_ic.v
verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v
verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v
verilog/work/c.v:1817:1: ... note: In file included from c.v
verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v
verilog/work/iuq_ic_miss.v:428:35: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_miss0.release_sm
verilog/work/iuq_ic_miss_table.v:159:22: Example path: ASSIGNW
verilog/work/iuq_ic_miss_table.v:68:25: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_miss0.unnamedblk1.miss_sm_loop[0].miss_sm.miss_sm_pt
verilog/work/iuq_ic_miss.v:802:24: Example path: ASSIGNW
verilog/work/iuq_ic_miss.v:428:35: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_miss0.release_sm
%Warning-UNOPTFLAT: verilog/a2o_litex/a2owb.v:86:24: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.nclk'
: ... In instance a2owb
86 | wire [0:6-1] nclk;
| ^~~~
verilog/a2o_litex/a2owb.v:86:24: Example path: a2owb.nclk
verilog/trilib_clk1x/tri_512x16_1r1w_1.v:213:17: Example path: ASSIGNW
verilog/trilib_clk1x/tri_512x16_1r1w_1.v:178:51: Example path: a2owb.c0.iuq0.bht2.bht0.clk
verilog/trilib_clk1x/tri_512x16_1r1w_1.v:217:8: Example path: ACTIVE
verilog/trilib_clk1x/tri_512x16_1r1w_1.v:217:8: Example path: ASSIGNPRE
verilog/trilib_clk1x/tri_512x16_1r1w_1.v:188:51: Example path: a2owb.c0.iuq0.bht2.bht0.__Vdly__reset_q
verilog/trilib_clk1x/tri_512x16_1r1w_1.v:215:6: Example path: ALWAYS
verilog/a2o_litex/a2owb.v:86:24: Example path: a2owb.nclk
verilog/a2o_litex/a2owb.v:209:13: Example path: ASSIGNW
verilog/a2o_litex/a2owb.v:86:24: Example path: a2owb.nclk
openpowerwtf
2 years ago