convert clk2x arrays to clk1x
parent
7fd72767b8
commit
5c201c0027
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# RTL
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## fpga/sim arrays
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* created sim-only (not fpga?) clk1x versions in trilib_clk1x to eliminate any possible problems with iverilog
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and verilator dealing with multiple clocks
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```
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trilib/tri_144x78_2r4w.v
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trilib/tri_64x72_1r1w.v
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trilib/tri_cam_16x143_1r1w1c.v
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trilib/tri_cam_32x143_1r1w1c.v
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# these two should be checked with cycle counts, etc. vs originals - might not cause errors if wrong...
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# at least one matches!
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# BHT...test3: orig= [00014100] Passing IAR detected: 000007F0 new= [00014100] Passing IAR detected: 000007F0
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# LRU won't be checked until doing TLB translates, and that logic will be rewritten for radix before that
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trilib/tri_512x16_1r1w_1.v
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trilib/tri_128x16_1r1w_1.v
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```
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### arrays using clk4x
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* 4W was done with clk4x
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* should be built for fpga with 4 arrays and a 'valid' array pointing to last write per entry
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```
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grep "nclk\[3\]" trilib/*
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trilib/tri_144x78_2r4w.v: .WCLK(nclk[3]), // Port A write clock input : clk4x
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trilib/tri_144x78_2r4w.v: .WCLK(nclk[3]), // Port A write clock input : clk4x
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```
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### arrays using clk2x
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```
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grep "nclk\[2\]" trilib/*
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trilib/tri_128x16_1r1w_1.v: assign clk2x = nclk[2];
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trilib/tri_128x16_1r1w_1.v: always @(posedge nclk[2])
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trilib/tri_144x78_2r4w.v: assign wr_mux_ctrl = {nclk[0], nclk[2]};
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trilib/tri_512x16_1r1w_1.v: assign clk2x = nclk[2];
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trilib/tri_64x72_1r1w.v: assign clk2x = nclk[2];
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trilib/tri_cam_16x143_1r1w1c.v: assign clk2x = nclk[2];
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trilib/tri_cam_16x143_1r1w1c.v: always @(posedge nclk[2])
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trilib/tri_cam_32x143_1r1w1c.v: assign clk2x = nclk[2];
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trilib/tri_cam_32x143_1r1w1c.v: always @(posedge nclk[2])
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```
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* IERAT, DERAT (cams)
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* BTB, SPR (1R,1W,read-before-write??)
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```
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grep tri_64x72 work/*
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work/iuq_btb.v: tri_64x72_1r1w btb0(
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work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr(
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```
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* BHT (bitwrite)
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```
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grep tri_512x16_1r1w_1 trilib/*
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trilib/tri_512x16_1r1w_1.v:module tri_512x16_1r1w_1(
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trilib/tri_bht_1024x8_1r1w.v: tri_512x16_1r1w_1 bht0(
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trilib/tri_bht_512x4_1r1w.v: tri_512x16_1r1w_1 bht0(
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```
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* MMU LRU (bitwrite)
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```
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grep tri_128x16_1r1w_1 work/*
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work/mmq.v: //tri.tri_128x16_1r1w_1 #(.`EXPAND_TYPE(`EXPAND_TYPE)) lru_array0(
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work/mmq.v: tri_128x16_1r1w_1 lru_array0(
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```
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@ -0,0 +1,281 @@
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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: Tri Array Wrapper
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//
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//*****************************************************************************
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// sim version, clk1x
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`include "tri_a2o.vh"
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module tri_128x16_1r1w_1(
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vdd,
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vcs,
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gnd,
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nclk,
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rd_act,
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wr_act,
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lcb_d_mode_dc,
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lcb_clkoff_dc_b,
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lcb_mpw1_dc_b,
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lcb_mpw2_dc_b,
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lcb_delay_lclkr_dc,
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ccflush_dc,
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scan_dis_dc_b,
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scan_diag_dc,
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func_scan_in,
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func_scan_out,
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lcb_sg_0,
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lcb_sl_thold_0_b,
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lcb_time_sl_thold_0,
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lcb_abst_sl_thold_0,
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lcb_ary_nsl_thold_0,
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lcb_repr_sl_thold_0,
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time_scan_in,
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time_scan_out,
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abst_scan_in,
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abst_scan_out,
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repr_scan_in,
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repr_scan_out,
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abist_di,
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abist_bw_odd,
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abist_bw_even,
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abist_wr_adr,
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wr_abst_act,
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abist_rd0_adr,
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rd0_abst_act,
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tc_lbist_ary_wrt_thru_dc,
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abist_ena_1,
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abist_g8t_rd0_comp_ena,
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abist_raw_dc_b,
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obs0_abist_cmp,
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lcb_bolt_sl_thold_0,
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pc_bo_enable_2,
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pc_bo_reset,
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pc_bo_unload,
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pc_bo_repair,
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pc_bo_shdata,
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pc_bo_select,
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bo_pc_failout,
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bo_pc_diagloop,
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tri_lcb_mpw1_dc_b,
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tri_lcb_mpw2_dc_b,
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tri_lcb_delay_lclkr_dc,
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tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc,
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bw,
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wr_adr,
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rd_adr,
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di,
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dout
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);
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parameter addressable_ports = 128; // number of addressable register in this array
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parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
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parameter port_bitwidth = 16; // bitwidth of ports
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parameter ways = 1; // number of ways
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// POWER PINS
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inout vdd;
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inout vcs;
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inout gnd;
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input [0:`NCLK_WIDTH-1] nclk;
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input rd_act;
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input wr_act;
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// DC TEST PINS
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input lcb_d_mode_dc;
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input lcb_clkoff_dc_b;
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input [0:4] lcb_mpw1_dc_b;
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input lcb_mpw2_dc_b;
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input [0:4] lcb_delay_lclkr_dc;
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input ccflush_dc;
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input scan_dis_dc_b;
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input scan_diag_dc;
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input func_scan_in;
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output func_scan_out;
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input lcb_sg_0;
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input lcb_sl_thold_0_b;
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input lcb_time_sl_thold_0;
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input lcb_abst_sl_thold_0;
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input lcb_ary_nsl_thold_0;
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input lcb_repr_sl_thold_0;
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input time_scan_in;
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output time_scan_out;
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input abst_scan_in;
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output abst_scan_out;
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input repr_scan_in;
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output repr_scan_out;
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input [0:3] abist_di;
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input abist_bw_odd;
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input abist_bw_even;
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input [0:6] abist_wr_adr;
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input wr_abst_act;
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input [0:6] abist_rd0_adr;
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input rd0_abst_act;
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input tc_lbist_ary_wrt_thru_dc;
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input abist_ena_1;
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input abist_g8t_rd0_comp_ena;
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input abist_raw_dc_b;
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input [0:3] obs0_abist_cmp;
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// BOLT-ON
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input lcb_bolt_sl_thold_0;
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input pc_bo_enable_2; // general bolt-on enable
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input pc_bo_reset; // reset
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input pc_bo_unload; // unload sticky bits
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input pc_bo_repair; // execute sticky bit decode
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input pc_bo_shdata; // shift data for timing write and diag loop
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input pc_bo_select; // select for mask and hier writes
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output bo_pc_failout; // fail/no-fix reg
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output bo_pc_diagloop;
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input tri_lcb_mpw1_dc_b;
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input tri_lcb_mpw2_dc_b;
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input tri_lcb_delay_lclkr_dc;
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input tri_lcb_clkoff_dc_b;
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input tri_lcb_act_dis_dc;
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input [0:15] bw;
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input [0:6] wr_adr;
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input [0:6] rd_adr;
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input [0:15] di;
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output [0:15] dout;
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// tri_128x16_1r1w_1
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// Configuration Statement for NCsim
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//for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36;
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wire clk;
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wire [0:8] b0addra;
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wire [0:8] b0addrb;
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wire wea;
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wire web;
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wire wren_a;
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wire [0:15] w_data_in_0;
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wire [0:15] r_data_out_0_bram;
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// Latches
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reg reset_q;
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reg [0:15] r_data_out_1_q;
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(* analysis_not_referenced="true" *)
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wire unused;
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// sim array
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reg [0:15] mem[0:127];
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integer i;
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initial begin
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for (i = 0; i < 128; i = i + 1)
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mem[i] = 0;
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end
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//wtf:icarus $dumpvars cannot dump a vpiMemory
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generate
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genvar j;
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for (j = 0; j < 128; j=j+1) begin: loc
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wire [0:15] dat;
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assign dat = mem[j][0:15];
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end
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endgenerate
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assign clk = nclk[0];
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always @(posedge clk)
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begin: rlatch
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reset_q <= nclk[1];
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end
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assign b0addra[2:8] = wr_adr;
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assign b0addrb[2:8] = rd_adr;
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// Unused Address Bits
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assign b0addra[0:1] = 2'b00;
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assign b0addrb[0:1] = 2'b00;
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// port a is a read-modify-write port
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assign wren_a = (bw != 0) & wr_act;
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assign wea = wren_a;
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assign web = 1'b0;
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assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
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assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
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assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
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assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
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assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
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assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
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assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
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assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
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assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
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assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
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assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
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assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
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assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
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assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
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assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
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assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
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always @(posedge clk) begin
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r_data_out_1_q <= mem[b0addrb];
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if (wea) begin
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mem[b0addra] <= w_data_in_0;
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end
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end
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assign r_data_out_0_bram = mem[b0addra];
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assign dout = r_data_out_1_q[0:15];
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assign func_scan_out = func_scan_in;
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assign time_scan_out = time_scan_in;
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assign abst_scan_out = abst_scan_in;
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assign repr_scan_out = repr_scan_in;
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assign bo_pc_failout = 1'b0;
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assign bo_pc_diagloop = 1'b0;
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assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
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lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
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lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
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abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
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tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
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lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
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pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc, rd_act};
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endmodule
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@ -0,0 +1,273 @@
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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
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||||
// Modified Terms:
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//
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||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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||||
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: Tri Array Wrapper
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//
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//*****************************************************************************
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// sim version, clk1x
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`include "tri_a2o.vh"
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module tri_512x16_1r1w_1(
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vdd,
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vcs,
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gnd,
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nclk,
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rd_act,
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wr_act,
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lcb_d_mode_dc,
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lcb_clkoff_dc_b,
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lcb_mpw1_dc_b,
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lcb_mpw2_dc_b,
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lcb_delay_lclkr_dc,
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ccflush_dc,
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scan_dis_dc_b,
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scan_diag_dc,
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func_scan_in,
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func_scan_out,
|
||||
lcb_sg_0,
|
||||
lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0,
|
||||
lcb_abst_sl_thold_0,
|
||||
lcb_ary_nsl_thold_0,
|
||||
lcb_repr_sl_thold_0,
|
||||
time_scan_in,
|
||||
time_scan_out,
|
||||
abst_scan_in,
|
||||
abst_scan_out,
|
||||
repr_scan_in,
|
||||
repr_scan_out,
|
||||
abist_di,
|
||||
abist_bw_odd,
|
||||
abist_bw_even,
|
||||
abist_wr_adr,
|
||||
wr_abst_act,
|
||||
abist_rd0_adr,
|
||||
rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc,
|
||||
abist_ena_1,
|
||||
abist_g8t_rd0_comp_ena,
|
||||
abist_raw_dc_b,
|
||||
obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0,
|
||||
pc_bo_enable_2,
|
||||
pc_bo_reset,
|
||||
pc_bo_unload,
|
||||
pc_bo_repair,
|
||||
pc_bo_shdata,
|
||||
pc_bo_select,
|
||||
bo_pc_failout,
|
||||
bo_pc_diagloop,
|
||||
tri_lcb_mpw1_dc_b,
|
||||
tri_lcb_mpw2_dc_b,
|
||||
tri_lcb_delay_lclkr_dc,
|
||||
tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc,
|
||||
bw,
|
||||
wr_adr,
|
||||
rd_adr,
|
||||
di,
|
||||
dout
|
||||
);
|
||||
parameter addressable_ports = 128; // number of addressable register in this array
|
||||
parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
|
||||
parameter port_bitwidth = 16; // bitwidth of ports
|
||||
parameter ways = 1; // number of ways
|
||||
|
||||
// POWER PINS
|
||||
inout vdd;
|
||||
inout vcs;
|
||||
inout gnd;
|
||||
|
||||
input [0:`NCLK_WIDTH-1] nclk;
|
||||
|
||||
input rd_act;
|
||||
input wr_act;
|
||||
|
||||
// DC TEST PINS
|
||||
input lcb_d_mode_dc;
|
||||
input lcb_clkoff_dc_b;
|
||||
input [0:4] lcb_mpw1_dc_b;
|
||||
input lcb_mpw2_dc_b;
|
||||
input [0:4] lcb_delay_lclkr_dc;
|
||||
|
||||
input ccflush_dc;
|
||||
input scan_dis_dc_b;
|
||||
input scan_diag_dc;
|
||||
input func_scan_in;
|
||||
output func_scan_out;
|
||||
|
||||
input lcb_sg_0;
|
||||
input lcb_sl_thold_0_b;
|
||||
input lcb_time_sl_thold_0;
|
||||
input lcb_abst_sl_thold_0;
|
||||
input lcb_ary_nsl_thold_0;
|
||||
input lcb_repr_sl_thold_0;
|
||||
input time_scan_in;
|
||||
output time_scan_out;
|
||||
input abst_scan_in;
|
||||
output abst_scan_out;
|
||||
input repr_scan_in;
|
||||
output repr_scan_out;
|
||||
|
||||
input [0:3] abist_di;
|
||||
input abist_bw_odd;
|
||||
input abist_bw_even;
|
||||
input [0:6] abist_wr_adr;
|
||||
input wr_abst_act;
|
||||
input [0:6] abist_rd0_adr;
|
||||
input rd0_abst_act;
|
||||
input tc_lbist_ary_wrt_thru_dc;
|
||||
input abist_ena_1;
|
||||
input abist_g8t_rd0_comp_ena;
|
||||
input abist_raw_dc_b;
|
||||
input [0:3] obs0_abist_cmp;
|
||||
|
||||
// BOLT-ON
|
||||
input lcb_bolt_sl_thold_0;
|
||||
input pc_bo_enable_2; // general bolt-on enable
|
||||
input pc_bo_reset; // reset
|
||||
input pc_bo_unload; // unload sticky bits
|
||||
input pc_bo_repair; // execute sticky bit decode
|
||||
input pc_bo_shdata; // shift data for timing write and diag loop
|
||||
input pc_bo_select; // select for mask and hier writes
|
||||
output bo_pc_failout; // fail/no-fix reg
|
||||
output bo_pc_diagloop;
|
||||
input tri_lcb_mpw1_dc_b;
|
||||
input tri_lcb_mpw2_dc_b;
|
||||
input tri_lcb_delay_lclkr_dc;
|
||||
input tri_lcb_clkoff_dc_b;
|
||||
input tri_lcb_act_dis_dc;
|
||||
|
||||
input [0:15] bw;
|
||||
input [0:8] wr_adr;
|
||||
input [0:8] rd_adr;
|
||||
input [0:15] di;
|
||||
|
||||
output [0:15] dout;
|
||||
|
||||
wire clk;
|
||||
wire [0:8] b0addra;
|
||||
wire [0:8] b0addrb;
|
||||
wire wea;
|
||||
wire web;
|
||||
wire wren_a;
|
||||
wire [0:15] w_data_in_0;
|
||||
wire [0:15] r_data_out_0_bram;
|
||||
|
||||
// Latches
|
||||
reg reset_q;
|
||||
reg [0:15] r_data_out_1_q;
|
||||
|
||||
|
||||
(* analysis_not_referenced="true" *)
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [0:15] mem[0:511];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 512; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 512; j=j+1) begin: loc
|
||||
wire [0:15] dat;
|
||||
assign dat = mem[j][0:15];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign clk = nclk[0];
|
||||
|
||||
always @(posedge clk)
|
||||
begin: rlatch
|
||||
reset_q <= nclk[1];
|
||||
end
|
||||
|
||||
//wtf do they use diff addresses?
|
||||
assign b0addra[0:8] = wr_adr;
|
||||
assign b0addrb[0:8] = rd_adr;
|
||||
|
||||
// port a is a read-modify-write port
|
||||
assign wren_a = (bw != 0) & wr_act;
|
||||
assign wea = wren_a;
|
||||
assign web = 1'b0;
|
||||
assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
|
||||
assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
|
||||
assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
|
||||
assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
|
||||
assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
|
||||
assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
|
||||
assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
|
||||
assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
|
||||
assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
|
||||
assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
|
||||
assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
|
||||
assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
|
||||
assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
|
||||
assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
|
||||
assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
|
||||
assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
r_data_out_1_q <= mem[b0addrb];
|
||||
if (wea) begin
|
||||
mem[b0addra] <= w_data_in_0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign r_data_out_0_bram = mem[b0addra];
|
||||
assign dout = r_data_out_1_q[0:15];
|
||||
|
||||
assign func_scan_out = func_scan_in;
|
||||
assign time_scan_out = time_scan_in;
|
||||
assign abst_scan_out = abst_scan_in;
|
||||
assign repr_scan_out = repr_scan_in;
|
||||
|
||||
assign bo_pc_failout = 1'b0;
|
||||
assign bo_pc_diagloop = 1'b0;
|
||||
|
||||
assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
|
||||
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
|
||||
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc, rd_act};
|
||||
endmodule
|
@ -0,0 +1,245 @@
|
||||
// © IBM Corp. 2022
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
//*****************************************************************************
|
||||
// Description: Tri-Lam Array Wrapper
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
// sim version, clk1x
|
||||
|
||||
`include "tri_a2o.vh"
|
||||
|
||||
module tri_64x72_1r1w(
|
||||
vdd,
|
||||
vcs,
|
||||
gnd,
|
||||
nclk,
|
||||
sg_0,
|
||||
abst_sl_thold_0,
|
||||
ary_nsl_thold_0,
|
||||
time_sl_thold_0,
|
||||
repr_sl_thold_0,
|
||||
rd0_act,
|
||||
rd0_adr,
|
||||
do0,
|
||||
wr_act,
|
||||
wr_adr,
|
||||
di,
|
||||
abst_scan_in,
|
||||
abst_scan_out,
|
||||
time_scan_in,
|
||||
time_scan_out,
|
||||
repr_scan_in,
|
||||
repr_scan_out,
|
||||
scan_dis_dc_b,
|
||||
scan_diag_dc,
|
||||
ccflush_dc,
|
||||
clkoff_dc_b,
|
||||
d_mode_dc,
|
||||
mpw1_dc_b,
|
||||
mpw2_dc_b,
|
||||
delay_lclkr_dc,
|
||||
lcb_bolt_sl_thold_0,
|
||||
pc_bo_enable_2,
|
||||
pc_bo_reset,
|
||||
pc_bo_unload,
|
||||
pc_bo_repair,
|
||||
pc_bo_shdata,
|
||||
pc_bo_select,
|
||||
bo_pc_failout,
|
||||
bo_pc_diagloop,
|
||||
tri_lcb_mpw1_dc_b,
|
||||
tri_lcb_mpw2_dc_b,
|
||||
tri_lcb_delay_lclkr_dc,
|
||||
tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc,
|
||||
abist_di,
|
||||
abist_bw_odd,
|
||||
abist_bw_even,
|
||||
abist_wr_adr,
|
||||
wr_abst_act,
|
||||
abist_rd0_adr,
|
||||
rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc,
|
||||
abist_ena_1,
|
||||
abist_g8t_rd0_comp_ena,
|
||||
abist_raw_dc_b,
|
||||
obs0_abist_cmp
|
||||
);
|
||||
|
||||
// Power
|
||||
(* analysis_not_referenced="true" *)
|
||||
inout vdd;
|
||||
(* analysis_not_referenced="true" *)
|
||||
inout vcs;
|
||||
(* analysis_not_referenced="true" *)
|
||||
inout gnd;
|
||||
|
||||
// Clock Pervasive
|
||||
input [0:`NCLK_WIDTH-1] nclk;
|
||||
input sg_0;
|
||||
input abst_sl_thold_0;
|
||||
input ary_nsl_thold_0;
|
||||
input time_sl_thold_0;
|
||||
input repr_sl_thold_0;
|
||||
|
||||
// Reads
|
||||
input rd0_act;
|
||||
input [0:5] rd0_adr;
|
||||
output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0;
|
||||
|
||||
// Writes
|
||||
input wr_act;
|
||||
input [0:5] wr_adr;
|
||||
input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] di;
|
||||
|
||||
// Scan
|
||||
input abst_scan_in;
|
||||
output abst_scan_out;
|
||||
input time_scan_in;
|
||||
output time_scan_out;
|
||||
input repr_scan_in;
|
||||
output repr_scan_out;
|
||||
|
||||
// Misc Pervasive
|
||||
input scan_dis_dc_b;
|
||||
input scan_diag_dc;
|
||||
input ccflush_dc;
|
||||
input clkoff_dc_b;
|
||||
input d_mode_dc;
|
||||
input [0:4] mpw1_dc_b;
|
||||
input mpw2_dc_b;
|
||||
input [0:4] delay_lclkr_dc;
|
||||
|
||||
// BOLT-ON
|
||||
input lcb_bolt_sl_thold_0;
|
||||
input pc_bo_enable_2; // general bolt-on enable
|
||||
input pc_bo_reset; // reset
|
||||
input pc_bo_unload; // unload sticky bits
|
||||
input pc_bo_repair; // execute sticky bit decode
|
||||
input pc_bo_shdata; // shift data for timing write and diag loop
|
||||
input pc_bo_select; // select for mask and hier writes
|
||||
output bo_pc_failout; // fail/no-fix reg
|
||||
output bo_pc_diagloop;
|
||||
input tri_lcb_mpw1_dc_b;
|
||||
input tri_lcb_mpw2_dc_b;
|
||||
input tri_lcb_delay_lclkr_dc;
|
||||
input tri_lcb_clkoff_dc_b;
|
||||
input tri_lcb_act_dis_dc;
|
||||
|
||||
// ABIST
|
||||
input [0:3] abist_di;
|
||||
input abist_bw_odd;
|
||||
input abist_bw_even;
|
||||
input [0:5] abist_wr_adr;
|
||||
input wr_abst_act;
|
||||
input [0:5] abist_rd0_adr;
|
||||
input rd0_abst_act;
|
||||
input tc_lbist_ary_wrt_thru_dc;
|
||||
input abist_ena_1;
|
||||
input abist_g8t_rd0_comp_ena;
|
||||
input abist_raw_dc_b;
|
||||
input [0:3] obs0_abist_cmp;
|
||||
|
||||
wire sreset;
|
||||
wire [0:71] tidn;
|
||||
|
||||
(* analysis_not_referenced="true" *)
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [0:63] mem[0:71];
|
||||
|
||||
reg r0_e_q;
|
||||
wire r0_e_d;
|
||||
reg [0:5] r0_a_q;
|
||||
wire [0:5] r0_a_d;
|
||||
reg [0:71] r0_d_q;
|
||||
wire [0:71] r0_d_d;
|
||||
|
||||
reg w0_e_q;
|
||||
wire w0_e_d;
|
||||
reg [0:5] w0_a_q;
|
||||
wire [0:5] w0_a_d;
|
||||
reg [0:71] w0_d_q;
|
||||
wire [0:71] w0_d_d;
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 64; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 63; j=j+1) begin: loc
|
||||
wire [0:63] dat;
|
||||
wire [0:7] par;
|
||||
assign dat = mem[j][0:63];
|
||||
assign par = mem[j][0:7];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
|
||||
assign clk = nclk[0];
|
||||
assign sreset = nclk[1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
r0_e_q <= rd0_act;
|
||||
r0_a_q <= rd0_adr;
|
||||
r0_d_q <= r0_e_q ? mem[r0_a_q] : 0;
|
||||
|
||||
if (w0_e_q) begin
|
||||
mem[w0_a_q] <= w0_d_q;
|
||||
end
|
||||
w0_e_q <= wr_act;
|
||||
w0_a_q <= wr_adr;
|
||||
w0_d_q <= di;
|
||||
|
||||
end
|
||||
|
||||
assign do0 = r0_d_q;
|
||||
|
||||
assign abst_scan_out = abst_scan_in;
|
||||
assign time_scan_out = time_scan_in;
|
||||
assign repr_scan_out = repr_scan_in;
|
||||
|
||||
assign bo_pc_failout = 1'b0;
|
||||
assign bo_pc_diagloop = 1'b0;
|
||||
|
||||
assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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Reference in New Issue