convert clk2x arrays to clk1x

dev/verilog/readme.md

@@ -0,0 +1,73 @@
+# RTL
+
+
+## fpga/sim arrays
+
+* created sim-only (not fpga?) clk1x versions in trilib_clk1x to eliminate any possible problems with iverilog
+and verilator dealing with multiple clocks
+
+```
+trilib/tri_144x78_2r4w.v
+trilib/tri_64x72_1r1w.v
+trilib/tri_cam_16x143_1r1w1c.v
+trilib/tri_cam_32x143_1r1w1c.v
+# these two should be checked with cycle counts, etc. vs originals - might not cause errors if wrong...
+# at least one matches!
+# BHT...test3: orig= [00014100] Passing IAR detected: 000007F0   new= [00014100] Passing IAR detected: 000007F0
+# LRU won't be checked until doing TLB translates, and that logic will be rewritten for radix before that
+trilib/tri_512x16_1r1w_1.v
+trilib/tri_128x16_1r1w_1.v
+```
+
+### arrays using clk4x
+
+* 4W was done with clk4x
+* should be built for fpga with 4 arrays and a 'valid' array pointing to last write per entry
+
+```
+grep "nclk\[3\]" trilib/*
+trilib/tri_144x78_2r4w.v:                  .WCLK(nclk[3]),                       // Port A write clock input : clk4x
+trilib/tri_144x78_2r4w.v:                  .WCLK(nclk[3]),		// Port A write clock input : clk4x
+```
+
+### arrays using clk2x
+
+```
+grep "nclk\[2\]" trilib/*
+trilib/tri_128x16_1r1w_1.v:     assign clk2x = nclk[2];
+trilib/tri_128x16_1r1w_1.v:     always @(posedge nclk[2])
+trilib/tri_144x78_2r4w.v:     assign wr_mux_ctrl = {nclk[0], nclk[2]};
+trilib/tri_512x16_1r1w_1.v:     assign clk2x = nclk[2];
+trilib/tri_64x72_1r1w.v:     assign clk2x = nclk[2];
+trilib/tri_cam_16x143_1r1w1c.v:   assign clk2x = nclk[2];
+trilib/tri_cam_16x143_1r1w1c.v:   always @(posedge nclk[2])
+trilib/tri_cam_32x143_1r1w1c.v:   assign clk2x = nclk[2];
+trilib/tri_cam_32x143_1r1w1c.v:   always @(posedge nclk[2])
+```
+
+* IERAT, DERAT (cams)
+
+* BTB, SPR (1R,1W,read-before-write??)
+
+   ```
+   grep tri_64x72 work/*
+   work/iuq_btb.v:      tri_64x72_1r1w  btb0(
+   work/xu_spr.v:   tri_64x72_1r1w xu_spr_aspr(
+   ```
+
+* BHT (bitwrite)
+
+   ```
+   grep tri_512x16_1r1w_1 trilib/*
+   trilib/tri_512x16_1r1w_1.v:module tri_512x16_1r1w_1(
+   trilib/tri_bht_1024x8_1r1w.v:            tri_512x16_1r1w_1  bht0(
+   trilib/tri_bht_512x4_1r1w.v:            tri_512x16_1r1w_1  bht0(
+   ```
+
+* MMU LRU (bitwrite)
+
+   ```
+   grep tri_128x16_1r1w_1 work/*
+   work/mmq.v:         //tri.tri_128x16_1r1w_1 #(.`EXPAND_TYPE(`EXPAND_TYPE)) lru_array0(
+   work/mmq.v:         tri_128x16_1r1w_1  lru_array0(
+   ```

dev/verilog/trilib_clk1x/tri_128x16_1r1w_1.v

@@ -0,0 +1,281 @@
+// © IBM Corp. 2022
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+//
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
+
+`timescale 1 ns / 1 ns
+
+//*****************************************************************************
+//  Description:  Tri Array Wrapper
+//
+//*****************************************************************************
+
+// sim version, clk1x
+
+`include "tri_a2o.vh"
+
+module tri_128x16_1r1w_1(
+   vdd,
+   vcs,
+   gnd,
+   nclk,
+   rd_act,
+   wr_act,
+   lcb_d_mode_dc,
+   lcb_clkoff_dc_b,
+   lcb_mpw1_dc_b,
+   lcb_mpw2_dc_b,
+   lcb_delay_lclkr_dc,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   func_scan_in,
+   func_scan_out,
+   lcb_sg_0,
+   lcb_sl_thold_0_b,
+   lcb_time_sl_thold_0,
+   lcb_abst_sl_thold_0,
+   lcb_ary_nsl_thold_0,
+   lcb_repr_sl_thold_0,
+   time_scan_in,
+   time_scan_out,
+   abst_scan_in,
+   abst_scan_out,
+   repr_scan_in,
+   repr_scan_out,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   wr_abst_act,
+   abist_rd0_adr,
+   rd0_abst_act,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   bw,
+   wr_adr,
+   rd_adr,
+   di,
+   dout
+);
+   parameter                                      addressable_ports = 128;	// number of addressable register in this array
+   parameter                                      addressbus_width = 7;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+   parameter                                      port_bitwidth = 16;		// bitwidth of ports
+   parameter                                      ways = 1;                     // number of ways
+
+   // POWER PINS
+   inout                                          vdd;
+   inout                                          vcs;
+   inout                                          gnd;
+
+   input [0:`NCLK_WIDTH-1]                        nclk;
+
+   input                                          rd_act;
+   input                                          wr_act;
+
+   // DC TEST PINS
+   input                                          lcb_d_mode_dc;
+   input                                          lcb_clkoff_dc_b;
+   input [0:4]                                    lcb_mpw1_dc_b;
+   input                                          lcb_mpw2_dc_b;
+   input [0:4]                                    lcb_delay_lclkr_dc;
+
+   input                                          ccflush_dc;
+   input                                          scan_dis_dc_b;
+   input                                          scan_diag_dc;
+   input                                          func_scan_in;
+   output                                         func_scan_out;
+
+   input                                          lcb_sg_0;
+   input                                          lcb_sl_thold_0_b;
+   input                                          lcb_time_sl_thold_0;
+   input                                          lcb_abst_sl_thold_0;
+   input                                          lcb_ary_nsl_thold_0;
+   input                                          lcb_repr_sl_thold_0;
+   input                                          time_scan_in;
+   output                                         time_scan_out;
+   input                                          abst_scan_in;
+   output                                         abst_scan_out;
+   input                                          repr_scan_in;
+   output                                         repr_scan_out;
+
+   input [0:3]                                    abist_di;
+   input                                          abist_bw_odd;
+   input                                          abist_bw_even;
+   input [0:6]                                    abist_wr_adr;
+   input                                          wr_abst_act;
+   input [0:6]                                    abist_rd0_adr;
+   input                                          rd0_abst_act;
+   input                                          tc_lbist_ary_wrt_thru_dc;
+   input                                          abist_ena_1;
+   input                                          abist_g8t_rd0_comp_ena;
+   input                                          abist_raw_dc_b;
+   input [0:3]                                    obs0_abist_cmp;
+
+   // BOLT-ON
+   input                                          lcb_bolt_sl_thold_0;
+   input                                          pc_bo_enable_2;	// general bolt-on enable
+   input                                          pc_bo_reset;		// reset
+   input                                          pc_bo_unload;		// unload sticky bits
+   input                                          pc_bo_repair;		// execute sticky bit decode
+   input                                          pc_bo_shdata;		// shift data for timing write and diag loop
+   input                                          pc_bo_select;		// select for mask and hier writes
+   output                                         bo_pc_failout;	// fail/no-fix reg
+   output                                         bo_pc_diagloop;
+   input                                          tri_lcb_mpw1_dc_b;
+   input                                          tri_lcb_mpw2_dc_b;
+   input                                          tri_lcb_delay_lclkr_dc;
+   input                                          tri_lcb_clkoff_dc_b;
+   input                                          tri_lcb_act_dis_dc;
+
+   input [0:15]                                   bw;
+   input [0:6]                                    wr_adr;
+   input [0:6]                                    rd_adr;
+   input [0:15]                                   di;
+
+   output [0:15]                                  dout;
+
+   // tri_128x16_1r1w_1
+
+   // Configuration Statement for NCsim
+   //for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36;
+
+   wire                                           clk;
+   wire [0:8]                                     b0addra;
+   wire [0:8]                                     b0addrb;
+   wire                                           wea;
+   wire                                           web;
+   wire                                           wren_a;
+   wire [0:15]                                    w_data_in_0;
+   wire [0:15]                                    r_data_out_0_bram;
+
+   // Latches
+   reg                                            reset_q;
+   reg [0:15]                                     r_data_out_1_q;
+
+
+   (* analysis_not_referenced="true" *)
+   wire                                           unused;
+
+  // sim array
+   reg   [0:15]                  mem[0:127];
+
+   integer i;
+   initial begin
+      for (i = 0; i < 128; i = i + 1)
+         mem[i] = 0;
+   end
+
+   //wtf:icarus $dumpvars cannot dump a vpiMemory
+   generate
+       genvar j;
+       for (j = 0; j < 128; j=j+1) begin: loc
+          wire [0:15] dat;
+          assign dat = mem[j][0:15];
+       end
+   endgenerate
+
+     assign clk = nclk[0];
+
+     always @(posedge clk)
+     begin: rlatch
+       reset_q <= nclk[1];
+     end
+
+     assign b0addra[2:8] = wr_adr;
+     assign b0addrb[2:8] = rd_adr;
+
+     // Unused Address Bits
+     assign b0addra[0:1] = 2'b00;
+     assign b0addrb[0:1] = 2'b00;
+
+     // port a is a read-modify-write port
+     assign wren_a = (bw != 0) & wr_act;
+     assign wea = wren_a;
+     assign web = 1'b0;
+     assign w_data_in_0[0]  = bw[0]  ? di[0]  : r_data_out_0_bram[0];
+     assign w_data_in_0[1]  = bw[1]  ? di[1]  : r_data_out_0_bram[1];
+     assign w_data_in_0[2]  = bw[2]  ? di[2]  : r_data_out_0_bram[2];
+     assign w_data_in_0[3]  = bw[3]  ? di[3]  : r_data_out_0_bram[3];
+     assign w_data_in_0[4]  = bw[4]  ? di[4]  : r_data_out_0_bram[4];
+     assign w_data_in_0[5]  = bw[5]  ? di[5]  : r_data_out_0_bram[5];
+     assign w_data_in_0[6]  = bw[6]  ? di[6]  : r_data_out_0_bram[6];
+     assign w_data_in_0[7]  = bw[7]  ? di[7]  : r_data_out_0_bram[7];
+     assign w_data_in_0[8]  = bw[8]  ? di[8]  : r_data_out_0_bram[8];
+     assign w_data_in_0[9]  = bw[9]  ? di[9]  : r_data_out_0_bram[9];
+     assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
+     assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
+     assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
+     assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
+     assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
+     assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
+
+     always @(posedge clk) begin
+
+       r_data_out_1_q <= mem[b0addrb];
+       if (wea) begin
+         mem[b0addra] <= w_data_in_0;
+       end
+
+     end
+
+     assign r_data_out_0_bram = mem[b0addra];
+     assign dout = r_data_out_1_q[0:15];
+
+     assign func_scan_out = func_scan_in;
+     assign time_scan_out = time_scan_in;
+     assign abst_scan_out = abst_scan_in;
+     assign repr_scan_out = repr_scan_in;
+
+     assign bo_pc_failout = 1'b0;
+     assign bo_pc_diagloop = 1'b0;
+
+     assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
+                       lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
+                       lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
+                       abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
+                       tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
+                       lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
+                       pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
+                       tri_lcb_act_dis_dc, rd_act};
+endmodule

dev/verilog/trilib_clk1x/tri_144x78_2r4w.v

@@ -1,6 +1,4 @@
-//wtf rewrite as sim-only using only clk1x
+// © IBM Corp. 2022
-
-// © IBM Corp. 2020
 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
 // the terms below; you may not use the files in this repository except in
 // compliance with the License as modified.
@@ -28,13 +26,15 @@
 // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
 // obtained (along with the Power ISA) here: https://openpowerfoundation.org.
 
-`timescale 1 ps / 1 ps
+`timescale 1 ns / 1 ns
 
 //*****************************************************************************
 //  Description:  Tri-Lam Array Wrapper
 //
 //*****************************************************************************
 
+// sim version, clk1x
+
 `include "tri_a2o.vh"
 
 module tri_144x78_2r4w(
@@ -87,6 +87,7 @@ module tri_144x78_2r4w(
 );
 
    wire unused;
+
    // sim array
    reg   [64-`GPR_WIDTH:77]   mem[0:143];
 

dev/verilog/trilib_clk1x/tri_512x16_1r1w_1.v

@@ -0,0 +1,273 @@
+// © IBM Corp. 2022
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+//
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
+
+`timescale 1 ns / 1 ns
+
+//*****************************************************************************
+//  Description:  Tri Array Wrapper
+//
+//*****************************************************************************
+
+// sim version, clk1x
+
+`include "tri_a2o.vh"
+
+module tri_512x16_1r1w_1(
+   vdd,
+   vcs,
+   gnd,
+   nclk,
+   rd_act,
+   wr_act,
+   lcb_d_mode_dc,
+   lcb_clkoff_dc_b,
+   lcb_mpw1_dc_b,
+   lcb_mpw2_dc_b,
+   lcb_delay_lclkr_dc,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   func_scan_in,
+   func_scan_out,
+   lcb_sg_0,
+   lcb_sl_thold_0_b,
+   lcb_time_sl_thold_0,
+   lcb_abst_sl_thold_0,
+   lcb_ary_nsl_thold_0,
+   lcb_repr_sl_thold_0,
+   time_scan_in,
+   time_scan_out,
+   abst_scan_in,
+   abst_scan_out,
+   repr_scan_in,
+   repr_scan_out,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   wr_abst_act,
+   abist_rd0_adr,
+   rd0_abst_act,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   bw,
+   wr_adr,
+   rd_adr,
+   di,
+   dout
+);
+   parameter                                      addressable_ports = 128;	// number of addressable register in this array
+   parameter                                      addressbus_width = 9;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+   parameter                                      port_bitwidth = 16;		// bitwidth of ports
+   parameter                                      ways = 1;		// number of ways
+
+   // POWER PINS
+   inout                                          vdd;
+   inout                                          vcs;
+   inout                                          gnd;
+
+   input [0:`NCLK_WIDTH-1]                        nclk;
+
+   input                                          rd_act;
+   input                                          wr_act;
+
+   // DC TEST PINS
+   input                                          lcb_d_mode_dc;
+   input                                          lcb_clkoff_dc_b;
+   input [0:4]                                    lcb_mpw1_dc_b;
+   input                                          lcb_mpw2_dc_b;
+   input [0:4]                                    lcb_delay_lclkr_dc;
+
+   input                                          ccflush_dc;
+   input                                          scan_dis_dc_b;
+   input                                          scan_diag_dc;
+   input                                          func_scan_in;
+   output                                         func_scan_out;
+
+   input                                          lcb_sg_0;
+   input                                          lcb_sl_thold_0_b;
+   input                                          lcb_time_sl_thold_0;
+   input                                          lcb_abst_sl_thold_0;
+   input                                          lcb_ary_nsl_thold_0;
+   input                                          lcb_repr_sl_thold_0;
+   input                                          time_scan_in;
+   output                                         time_scan_out;
+   input                                          abst_scan_in;
+   output                                         abst_scan_out;
+   input                                          repr_scan_in;
+   output                                         repr_scan_out;
+
+   input [0:3]                                    abist_di;
+   input                                          abist_bw_odd;
+   input                                          abist_bw_even;
+   input [0:6]                                    abist_wr_adr;
+   input                                          wr_abst_act;
+   input [0:6]                                    abist_rd0_adr;
+   input                                          rd0_abst_act;
+   input                                          tc_lbist_ary_wrt_thru_dc;
+   input                                          abist_ena_1;
+   input                                          abist_g8t_rd0_comp_ena;
+   input                                          abist_raw_dc_b;
+   input [0:3]                                    obs0_abist_cmp;
+
+   // BOLT-ON
+   input                                          lcb_bolt_sl_thold_0;
+   input                                          pc_bo_enable_2;		// general bolt-on enable
+   input                                          pc_bo_reset;		// reset
+   input                                          pc_bo_unload;		// unload sticky bits
+   input                                          pc_bo_repair;		// execute sticky bit decode
+   input                                          pc_bo_shdata;		// shift data for timing write and diag loop
+   input                                          pc_bo_select;		// select for mask and hier writes
+   output                                         bo_pc_failout;		// fail/no-fix reg
+   output                                         bo_pc_diagloop;
+   input                                          tri_lcb_mpw1_dc_b;
+   input                                          tri_lcb_mpw2_dc_b;
+   input                                          tri_lcb_delay_lclkr_dc;
+   input                                          tri_lcb_clkoff_dc_b;
+   input                                          tri_lcb_act_dis_dc;
+
+   input [0:15]                                   bw;
+   input [0:8]                                    wr_adr;
+   input [0:8]                                    rd_adr;
+   input [0:15]                                   di;
+
+   output [0:15]                                  dout;
+
+   wire                                           clk;
+   wire [0:8]                                     b0addra;
+   wire [0:8]                                     b0addrb;
+   wire                                           wea;
+   wire                                           web;
+   wire                                           wren_a;
+   wire [0:15]                                    w_data_in_0;
+   wire [0:15]                                    r_data_out_0_bram;
+
+   // Latches
+   reg                                            reset_q;
+   reg  [0:15]                                    r_data_out_1_q;
+
+
+   (* analysis_not_referenced="true" *)
+   wire                                           unused;
+
+   // sim array
+   reg   [0:15]                  mem[0:511];
+
+   integer i;
+   initial begin
+      for (i = 0; i < 512; i = i + 1)
+         mem[i] = 0;
+   end
+
+   //wtf:icarus $dumpvars cannot dump a vpiMemory
+   generate
+       genvar j;
+       for (j = 0; j < 512; j=j+1) begin: loc
+          wire [0:15] dat;
+          assign dat = mem[j][0:15];
+       end
+   endgenerate
+
+     assign clk = nclk[0];
+
+     always @(posedge clk)
+     begin: rlatch
+       reset_q <= nclk[1];
+     end
+
+     //wtf do they use diff addresses?
+     assign b0addra[0:8] = wr_adr;
+     assign b0addrb[0:8] = rd_adr;
+
+     // port a is a read-modify-write port
+     assign wren_a = (bw != 0) & wr_act;
+     assign wea = wren_a;
+     assign web = 1'b0;
+     assign w_data_in_0[0]  = bw[0]  ? di[0]  : r_data_out_0_bram[0];
+     assign w_data_in_0[1]  = bw[1]  ? di[1]  : r_data_out_0_bram[1];
+     assign w_data_in_0[2]  = bw[2]  ? di[2]  : r_data_out_0_bram[2];
+     assign w_data_in_0[3]  = bw[3]  ? di[3]  : r_data_out_0_bram[3];
+     assign w_data_in_0[4]  = bw[4]  ? di[4]  : r_data_out_0_bram[4];
+     assign w_data_in_0[5]  = bw[5]  ? di[5]  : r_data_out_0_bram[5];
+     assign w_data_in_0[6]  = bw[6]  ? di[6]  : r_data_out_0_bram[6];
+     assign w_data_in_0[7]  = bw[7]  ? di[7]  : r_data_out_0_bram[7];
+     assign w_data_in_0[8]  = bw[8]  ? di[8]  : r_data_out_0_bram[8];
+     assign w_data_in_0[9]  = bw[9]  ? di[9]  : r_data_out_0_bram[9];
+     assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
+     assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
+     assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
+     assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
+     assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
+     assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
+
+     always @(posedge clk) begin
+
+       r_data_out_1_q <= mem[b0addrb];
+       if (wea) begin
+         mem[b0addra] <= w_data_in_0;
+       end
+
+     end
+
+     assign r_data_out_0_bram = mem[b0addra];
+     assign dout = r_data_out_1_q[0:15];
+
+     assign func_scan_out = func_scan_in;
+     assign time_scan_out = time_scan_in;
+     assign abst_scan_out = abst_scan_in;
+     assign repr_scan_out = repr_scan_in;
+
+     assign bo_pc_failout = 1'b0;
+     assign bo_pc_diagloop = 1'b0;
+
+     assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
+                       lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
+                       lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
+                       abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
+                       tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
+                       lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
+                       pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
+                       tri_lcb_act_dis_dc, rd_act};
+endmodule

dev/verilog/trilib_clk1x/tri_64x72_1r1w.v

@@ -0,0 +1,245 @@
+// © IBM Corp. 2022
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+//
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
+
+`timescale 1 ns / 1 ns
+
+//*****************************************************************************
+//  Description:  Tri-Lam Array Wrapper
+//
+//*****************************************************************************
+
+// sim version, clk1x
+
+`include "tri_a2o.vh"
+
+module tri_64x72_1r1w(
+   vdd,
+   vcs,
+   gnd,
+   nclk,
+   sg_0,
+   abst_sl_thold_0,
+   ary_nsl_thold_0,
+   time_sl_thold_0,
+   repr_sl_thold_0,
+   rd0_act,
+   rd0_adr,
+   do0,
+   wr_act,
+   wr_adr,
+   di,
+   abst_scan_in,
+   abst_scan_out,
+   time_scan_in,
+   time_scan_out,
+   repr_scan_in,
+   repr_scan_out,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   ccflush_dc,
+   clkoff_dc_b,
+   d_mode_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   delay_lclkr_dc,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   wr_abst_act,
+   abist_rd0_adr,
+   rd0_abst_act,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp
+);
+
+   // Power
+   (* analysis_not_referenced="true" *)
+   inout                               vdd;
+   (* analysis_not_referenced="true" *)
+   inout                               vcs;
+   (* analysis_not_referenced="true" *)
+   inout                               gnd;
+
+   // Clock Pervasive
+   input [0:`NCLK_WIDTH-1]             nclk;
+   input                               sg_0;
+   input                               abst_sl_thold_0;
+   input                               ary_nsl_thold_0;
+   input                               time_sl_thold_0;
+   input                               repr_sl_thold_0;
+
+   // Reads
+   input                               rd0_act;
+   input [0:5]                         rd0_adr;
+   output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0;
+
+   // Writes
+   input                               wr_act;
+   input [0:5]                         wr_adr;
+   input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)]  di;
+
+   // Scan
+   input                               abst_scan_in;
+   output                              abst_scan_out;
+   input                               time_scan_in;
+   output                              time_scan_out;
+   input                               repr_scan_in;
+   output                              repr_scan_out;
+
+   // Misc Pervasive
+   input                               scan_dis_dc_b;
+   input                               scan_diag_dc;
+   input                               ccflush_dc;
+   input                               clkoff_dc_b;
+   input                               d_mode_dc;
+   input [0:4]                         mpw1_dc_b;
+   input                               mpw2_dc_b;
+   input [0:4]                         delay_lclkr_dc;
+
+   // BOLT-ON
+   input                               lcb_bolt_sl_thold_0;
+   input                               pc_bo_enable_2;		// general bolt-on enable
+   input                               pc_bo_reset;		// reset
+   input                               pc_bo_unload;		// unload sticky bits
+   input                               pc_bo_repair;		// execute sticky bit decode
+   input                               pc_bo_shdata;		// shift data for timing write and diag loop
+   input                               pc_bo_select;		// select for mask and hier writes
+   output                              bo_pc_failout;		// fail/no-fix reg
+   output                              bo_pc_diagloop;
+   input                               tri_lcb_mpw1_dc_b;
+   input                               tri_lcb_mpw2_dc_b;
+   input                               tri_lcb_delay_lclkr_dc;
+   input                               tri_lcb_clkoff_dc_b;
+   input                               tri_lcb_act_dis_dc;
+
+   // ABIST
+   input [0:3]                         abist_di;
+   input                               abist_bw_odd;
+   input                               abist_bw_even;
+   input [0:5]                         abist_wr_adr;
+   input                               wr_abst_act;
+   input [0:5]                         abist_rd0_adr;
+   input                               rd0_abst_act;
+   input                               tc_lbist_ary_wrt_thru_dc;
+   input                               abist_ena_1;
+   input                               abist_g8t_rd0_comp_ena;
+   input                               abist_raw_dc_b;
+   input [0:3]                         obs0_abist_cmp;
+
+   wire                                sreset;
+   wire [0:71]                         tidn;
+
+   (* analysis_not_referenced="true" *)
+   wire                                unused;
+
+   // sim array
+   reg   [0:63]   mem[0:71];
+
+   reg            r0_e_q;
+   wire           r0_e_d;
+   reg   [0:5]    r0_a_q;
+   wire  [0:5]    r0_a_d;
+   reg   [0:71]   r0_d_q;
+   wire  [0:71]   r0_d_d;
+
+   reg            w0_e_q;
+   wire           w0_e_d;
+   reg   [0:5]    w0_a_q;
+   wire  [0:5]    w0_a_d;
+   reg   [0:71]   w0_d_q;
+   wire  [0:71]   w0_d_d;
+
+   integer i;
+   initial begin
+      for (i = 0; i < 64; i = i + 1)
+         mem[i] = 0;
+   end
+
+   //wtf:icarus $dumpvars cannot dump a vpiMemory
+   generate
+       genvar j;
+       for (j = 0; j < 63; j=j+1) begin: loc
+          wire [0:63] dat;
+          wire [0:7] par;
+          assign dat = mem[j][0:63];
+          assign par = mem[j][0:7];
+       end
+   endgenerate
+
+   generate
+
+   assign clk = nclk[0];
+   assign sreset = nclk[1];
+
+   always @(posedge clk) begin
+
+      r0_e_q <= rd0_act;
+      r0_a_q <= rd0_adr;
+      r0_d_q <= r0_e_q ? mem[r0_a_q] : 0;
+
+      if (w0_e_q) begin
+         mem[w0_a_q] <= w0_d_q;
+      end
+      w0_e_q <= wr_act;
+      w0_a_q <= wr_adr;
+      w0_d_q <= di;
+
+   end
+
+   assign do0 = r0_d_q;
+
+   assign abst_scan_out = abst_scan_in;
+   assign time_scan_out = time_scan_in;
+   assign repr_scan_out = repr_scan_in;
+
+   assign bo_pc_failout = 1'b0;
+   assign bo_pc_diagloop = 1'b0;
+
+   assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});
+
+  endgenerate
+
+endmodule