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litex software compile 64LE & 32BE

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pull/18/head
openpowerwtf 2 years ago
parent 7ed8d7029d
commit 4ed91f08a8
10 changed files with 1809 additions and 892 deletions
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9
dev/build/litex/a2o.py
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@ -1,6 +1,6 @@
#!/usr/bin/python3 #!/usr/bin/python3


# A2O Test - build with core.py # A2O Test (64LE)
# a2o.py --csr-csv csr.csv --no-compile-software # a2o.py --csr-csv csr.csv --no-compile-software
# a2o.py --csr-csv csr.csv --no-compile-software --build [--sys-clk-freq 50e6] # a2o.py --csr-csv csr.csv --no-compile-software --build [--sys-clk-freq 50e6]
# #
@ -16,9 +16,10 @@ from platforms import cmod7_kintex


# wtf - use local core (not built into litex) # wtf - use local core (not built into litex)
# help python find package # help python find package
import sys # not needed anymore
binPath = os.path.dirname(os.path.realpath(__file__)) #import sys
sys.path.append(os.path.join(binPath, 'a2p')) # dir with core package; core.py defines core source location #binPath = os.path.dirname(os.path.realpath(__file__))
#sys.path.append(os.path.join(binPath, 'a2o')) # dir with core package; core.py defines core source location
# get core def # get core def
from a2o import A2O from a2o import A2O
# add to litex dict # add to litex dict

37
dev/build/litex/a2o.txt
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@ -0,0 +1,37 @@
Building variant=WB_64LE.
Read 3790 bytes for ROM data.
Wrote mem.init
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libc'
make: Nothing to be done for 'all'.
make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libc'
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libcompiler_rt'
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libbase'
make: Nothing to be done for 'all'.
make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libbase'
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libfatfs'
make: Nothing to be done for 'all'.
make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libfatfs'
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/liblitespi'
make: Nothing to be done for 'all'.
make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/liblitespi'
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/liblitedram'
make: Nothing to be done for 'all'.
make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/liblitedram'
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libliteeth'
make: Nothing to be done for 'all'.
make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libliteeth'
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/liblitesdcard'
make: Nothing to be done for 'all'.
make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/liblitesdcard'
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/liblitesata'
make: Nothing to be done for 'all'.
make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/liblitesata'
make: Entering directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/bios'
python3 -m litex.soc.software.memusage bios.elf /data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/bios/../include/generated/regions.ld powerpc64le-linux-gnu

ROM usage: 28.17KiB (44.01%)
RAM usage: 0.00KiB (0.00%)

make: Leaving directory '/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/bios'

20
dev/build/litex/a2o/core.py
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@ -18,21 +18,30 @@ CPU_VARIANTS = {
'standard' : 'a2owb' 'standard' : 'a2owb'
} }


# 32 is from a2p plus -ma2; can get rid of some of them #wtf doesnt do anything, but you can somehow do it by using -Xassembler in gcc flags
GAS_FLAGS = {
'WB_32BE' : '-defsym BIOS_32=1',
'WB_64LE' : '-defsym BIOS_LE=1'
}

GCC_FLAGS = { GCC_FLAGS = {
'WB_32BE' : '-ma2 -m32 -mbig-endian fomit-frame-pointer -Wall -fno-builtin -nostdinc -fno-stack-protector -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes', 'WB_32BE' : '-mcpu=a2 -m32 -mbig-endian -fno-stack-protector -Xassembler -defsym -Xassembler BIOS_32=1',
'WB_64LE' : '-ma2 -m64 -mlittle-endian -mabi=elfv2 -fnostack-protector' 'WB_64LE' : '-mcpu=a2 -m64 -mlittle-endian -mabi=elfv2 -fno-stack-protector -Xassembler -defsym -Xassembler BIOS_LE=1'
} }



class A2O(CPU, AutoCSR): class A2O(CPU, AutoCSR):
name = 'a2o' name = 'a2o'
human_name = 'a2o' human_name = 'a2o'
variants = CPU_VARIANTS variants = CPU_VARIANTS

# default 64LE
family = 'ppc64' family = 'ppc64'
data_width = 64 data_width = 64
endianness = 'little' endianness = 'little'
gcc_triple = ('powerpc64le-linux', 'powerpc64le-linux-gnu') gcc_triple = ('powerpc64le-linux', 'powerpc64le-linux-gnu')
linker_output_format = 'elf64-powerpcle' linker_output_format = 'elf64-powerpcle'

nop = 'nop' nop = 'nop'
io_regions = {0xF0000000: 0x10000000} # origin, length io_regions = {0xF0000000: 0x10000000} # origin, length


@ -58,8 +67,9 @@ class A2O(CPU, AutoCSR):
if variant == 'standard': if variant == 'standard':
variant = 'WB_64LE' variant = 'WB_64LE'


if variant == 'WB_32LE': if variant == 'WB_32BE':
self.family = 'ppc32' #self.family = 'ppc' # kills meson build
self.family = 'powerpc'
self.data_width = 32 self.data_width = 32
self.endianness = 'big' self.endianness = 'big'
self.gcc_triple = 'powerpc-linux-gnu' self.gcc_triple = 'powerpc-linux-gnu'

1184
dev/build/litex/a2o/crt0.S
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85
dev/build/litex/a2o/crtsavres.s
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@ -0,0 +1,85 @@
# save/restore for 32b libc

.macro GLOBAL n
.type \n,@function
.global \n
\n:
.endm

# saves

GLOBAL _savegpr_31
GLOBAL _save32gpr_31
stw 31,-4(11)
blr

# restores

GLOBAL _restgpr_16_x
GLOBAL _rest32gpr_16_x
lwz 16,-64(11)

GLOBAL _restgpr_17_x
GLOBAL _rest32gpr_17_x
lwz 17,-60(11)

GLOBAL _restgpr_18_x
GLOBAL _rest32gpr_18_x
lwz 18,-56(11)

GLOBAL _restgpr_19_x
GLOBAL _rest32gpr_19_x
lwz 19,-52(11)

GLOBAL _restgpr_20_x
GLOBAL _rest32gpr_20_x
lwz 20,-48(11)

GLOBAL _restgpr_21_x
GLOBAL _rest32gpr_21_x
lwz 21,-44(11)

GLOBAL _restgpr_22_x
GLOBAL _rest32gpr_22_x
lwz 22,-40(11)

GLOBAL _restgpr_23_x
GLOBAL _rest32gpr_23_x
lwz 23,-36(11)

GLOBAL _restgpr_24_x
GLOBAL _rest32gpr_24_x
lwz 24,-32(11)

GLOBAL _restgpr_25_x
GLOBAL _rest32gpr_25_x
lwz 25,-28(11)

GLOBAL _restgpr_26_x
GLOBAL _rest32gpr_26_x
lwz 26,-24(11)

GLOBAL _restgpr_27_x
GLOBAL _rest32gpr_27_x
lwz 27,-20(11)

GLOBAL _restgpr_28_x
GLOBAL _rest32gpr_28_x
lwz 28,-16(11)

GLOBAL _restgpr_29_x
GLOBAL _rest32gpr_29_x
lwz 29,-12(11)

GLOBAL _restgpr_30_x
GLOBAL _rest32gpr_30_x
lwz 30,-8(11)

GLOBAL _restgpr_31_x
GLOBAL _rest32gpr_31_x
lwz 0,4(11)
lwz 31,-4(11)
mtlr 0
mr 1,11
blr

223
dev/build/litex/a2o_32.py
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@ -0,0 +1,223 @@
#!/usr/bin/python3

# A2O Test (32BE)
# a2o_32.py --csr-csv csr.csv --no-compile-software
# a2o_32.py --csr-csv csr.csv --no-compile-software --build [--sys-clk-freq 50e6]
#

import os
import argparse

from migen import *

# wtf - use local platform
from platforms import cmod7
from platforms import cmod7_kintex

# wtf - use local core (not built into litex)
# help python find package
# not needed anymore
#import sys
#binPath = os.path.dirname(os.path.realpath(__file__))
#sys.path.append(os.path.join(binPath, 'a2o')) # dir with core package; core.py defines core source location
# get core def
from a2o import A2O
# add to litex dict
from litex.soc.cores import cpu
cpu.CPUS['a2o'] = A2O

from litex.soc.cores.clock import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *

from litex.soc.cores.led import LedChaser
from litex.soc.cores import dna, xadc
from litex.soc.cores.gpio import GPIOIn
from litex.soc.cores.gpio import GPIOOut
from litex.soc.cores.bitbang import I2CMaster

from litex.soc.interconnect import wishbone

from litex.soc.cores import uart
from litex.soc.cores.uart import UART
from litex.soc.cores.uart import UARTPHY
from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeAnalyzer

# CRG ----------------------------------------------------------------------------------------------

class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()

self.submodules.pll = pll = S7MMCM(speedgrade=-1)
#wtf how do you add btn to reset sig?
#x = platform.request('user_btn',0)
self.comb += pll.reset.eq(self.rst)
#self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request('clk12'), 12e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.

self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)

def _to_signal(obj):
return obj.raw_bits() if isinstance(obj, Record) else obj

class BaseSoC(SoCCore):

def __init__(self, sys_clk_freq=int(50e6),
with_analyzer=False,
uart_baudrate=115200,
**kwargs):

coreUART = True
#romSize = 128*1024
#ramSize = 128*1024
romSize = 64 * 1024;
ramSize = 64 * 1024;
ddrSize = 16*1024*1024


# try build using different fpga's
#platform = cmod7.Platform()
#platform = cmod7.Platform(fpga='xc7a200t-SBG484-1') # arty-200
#platform = cmod7_kintex.Platform(fpga='xc7k325t-ffv676-1 ) # kintex-325
platform = cmod7_kintex.Platform(fpga='xc7k410t-ffv676-1') # kintex-410

SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32,
#with_uart=coreUART, integrated_rom_size=romSize, integrated_sram_size=ramSize, don't set rom/ram if doing it below!!!!!
with_uart=coreUART, integrated_rom_size=0, integrated_sram_size=0,
ident='A2O', ident_version=True, uart_baudrate=uart_baudrate,
cpu_type='a2o', cpu_variant='WB_32BE')

print(f'Building variant={self.cpu.variant}.')

# no irq yet, but should be able to connect; need irq handler in crt0.s
self.add_constant('UART_POLLING')

# this appears to be how to set up fixed csr order but not sure it works this way. https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py
#SoCCore.csr_map
#self.csr_map = {**SoCCore.csr_map, **{
#self.csr_map = {
# 'ctrl': 0,
# 'dna' : 1,
# 'uart': 2,
# 'i2c': 3,
# 'leds': 4
#}}
#interrupt_map = {**soc_cls.interrupt_map, **{
# 'uart': 0,
# 'timer0': 1,
#}}
self.mem_map = {
'rom': 0x00000000,
'ram': 0x00010000,
'main_ram': 0x01000000,
'csr': 0xFFF00000
}

# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

if not coreUART:
self.submodules.serial_bridge = UARTWishboneBridge(platform.request('serial'), sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)

self.add_csr('node_ctl')
self.add_csr('node_config')
self.add_csr('node_status')

# ON-BOARD MEM ------------------------------------------------------------------------------

with open('rom.init', 'r') as file:
hexdata = file.read().replace('\n', '')

#a2o how will this work for a2o? should allow 32BE or 64LE to load kernel+bios
# 1. core resets to 32BE
# 2. probably want to link kernel+bios in same mode, so have kernel deal with possible mode switch
# 3. load mem here in proper mode based on variant (A2O_32BE or A2O64_LE)

outFile = open('mem_init', 'w') # write data immediately so available even if not building (sim)
# this seems to work (specified in BE in rom.init, instructions are decoded properly)
# BUT, vivado wants each line to be 4B to match width (at least for sim)
bytedata = []
for i in range(0, len(hexdata), 8):
data = int(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2], 16) # BE->LE
bytedata.append(data)
outFile.write(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2] + '\n')
#bytedata.append(int(hexdata[i:i+2] + hexdata[i+2:i+4] + hexdata[i+4:i+6] + hexdata[i+6:i+8], 16))
romdata = bytedata
print('Read ' + str(len(romdata)) + ' bytes for ROM data.')
outFile.close()
print('Wrote mem.init')

self.add_rom('rom', origin=self.mem_map['rom'], size=romSize, contents=romdata) # name, origin, size, contents=[], mode='r'
# make this sram to match what linker expects
self.add_ram('sram', origin=self.mem_map['ram'], size=ramSize) # name, origin, size, contents=[], mode='rw'

# External Mem -----------------------------------------------------------------------------
self.add_ram('main_ram', origin=self.mem_map['main_ram'], size=ddrSize)

# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all('user_led'),
sys_clk_freq = sys_clk_freq
)
self.add_csr('leds')

# Buttons
self.submodules.buttons = GPIOIn(
pads = platform.request_all('user_btn')
)
self.add_csr('buttons')

# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.cpu.wb_stb,
self.cpu.wb_cyc,
self.cpu.wb_adr,
self.cpu.wb_we,
self.cpu.wb_ack,
self.cpu.wb_sel,
self.cpu.wb_datw,
self.cpu.wb.datr,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = 'sys',
csr_csv = 'analyzer.csv')
self.add_csr('analyzer')



# Build --------------------------------------------------------------------------------------------

def main():

parser = argparse.ArgumentParser(description='A2O Test')
parser.add_argument('--build', action='store_true', help='Build bitstream')
parser.add_argument('--load', action='store_true', help='Load bitstream')
parser.add_argument('--sys-clk-freq', default=100e6, help='System clock frequency (default: 100MHz)')
parser.add_argument('--with-analyzer', action='store_true', help='Include analyzer')

builder_args(parser)
args = parser.parse_args()

soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_analyzer = args.with_analyzer,
)

builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)

if __name__ == '__main__':
main()

1050
dev/build/litex/a2o_32.txt
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4
dev/build/litex/csr.csv
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@ -1,5 +1,5 @@
#-------------------------------------------------------------------------------- #--------------------------------------------------------------------------------
# Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22 # Auto-generated by LiteX (33ae301d) on 2022-08-17 12:09:08
#-------------------------------------------------------------------------------- #--------------------------------------------------------------------------------
csr_base,leds,0xfff01800,, csr_base,leds,0xfff01800,,
csr_base,buttons,0xfff02000,, csr_base,buttons,0xfff02000,,
@ -32,7 +32,7 @@ constant,config_clock_frequency,100000000,,
constant,config_cpu_has_interrupt,None,, constant,config_cpu_has_interrupt,None,,
constant,config_cpu_reset_addr,0,, constant,config_cpu_reset_addr,0,,
constant,config_cpu_type_a2o,None,, constant,config_cpu_type_a2o,None,,
constant,config_cpu_variant_standard,None,, constant,config_cpu_variant_wb_32be,None,,
constant,config_cpu_human_name,a2owb,, constant,config_cpu_human_name,a2owb,,
constant,config_cpu_nop,nop,, constant,config_cpu_nop,nop,,
constant,uart_polling,None,, constant,uart_polling,None,,

1 #--------------------------------------------------------------------------------
2 # Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22 # Auto-generated by LiteX (33ae301d) on 2022-08-17 12:09:08
3 #--------------------------------------------------------------------------------
4 csr_base,leds,0xfff01800,,
5 csr_base,buttons,0xfff02000,,
32 constant,config_cpu_has_interrupt,None,,
33 constant,config_cpu_reset_addr,0,,
34 constant,config_cpu_type_a2o,None,,
35 constant,config_cpu_variant_standard,None,, constant,config_cpu_variant_wb_32be,None,,
36 constant,config_cpu_human_name,a2owb,,
37 constant,config_cpu_nop,nop,,
38 constant,uart_polling,None,,

0
dev/build/litex/make → dev/build/litex/makesoc
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89
dev/build/litex/readme.md
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@ -2,6 +2,95 @@


## Litex ## Litex


### Try 32BE and 64LE software builds

#### 64LE

```
a2o.py --csr-csv csr.csv
# completes OK and build/cmod7_kintex/software is created
```

#### 32BE

```
a2o_32.py --csr-csv csr.csv

Running test binary command: /data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libc/meson-private/sanitycheckc.exe
C compiler for the build machine: ccache cc (gcc 9.4.0 "cc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0")
C linker for the build machine: cc ld.bfd 2.34
Build machine cpu family: x86_64
Build machine cpu: x86_64
Host machine cpu family: ppc
Host machine cpu: a2o
Target machine cpu family: ppc
Target machine cpu: a2o

../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/meson.build:99:2: ERROR: Problem encountered:

Unsupported architecture: "ppc"
```

* change core.py cpu_family="powerpc"; warning only :)

```
a2o_32.py --csr-csv csr.csv

...
WARNING: Unknown CPU family powerpc, please report this at https://github.com/mesonbuild/meson/issues/new
...

[15/795] Compiling C object newlib/libc.a.p/libc_machine_powerpc_setjmp.S.o
FAILED: newlib/libc.a.p/libc_machine_powerpc_setjmp.S.o
powerpc-linux-gnu-gcc -Inewlib/libc.a.p -Inewlib -I../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib -Inewlib/libm/common -I../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libm/common -Inewlib/libc/machine/powerpc -I../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/machine/powerpc -Inewlib/libc/tinystdio -I../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/tinystdio -I. -I../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data -Inewlib/libc/include -I../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/include -I/home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/tinystdio -I/home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/include -I/data/projects/litex/litex/soc/software/libbase -I/data/projects/litex/litex/soc/software/include -I/data/projects/litex/litex/soc/software -I/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/include -I/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/include/../libc -I/data/projects/a2o/dev/build/litex/a2o -fdiagnostics-color=always -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra -std=c18 -Os -g -ffunction-sections -Os -mcpu=a2 -m32 -mbig-endian -fomit-frame-pointer -fno-builtin -fno-stack-protector -fexceptions -D__a2o__ -g3 -fomit-frame-pointer -Wall -fno-builtin -fno-stack-protector -fexceptions -Wpragmas -include /data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/libc/picolibc.h -fno-stack-protector -U_FORTIFY_SOURCE -fno-common -frounding-math -DFORMAT_DEFAULT_INTEGER -Werror=implicit-function-declaration -Werror=vla -Warray-bounds -Wold-style-definition -Wno-missing-braces -Wno-implicit-int -Wno-return-type -D_COMPILING_NEWLIB -MD -MQ newlib/libc.a.p/libc_machine_powerpc_setjmp.S.o -MF newlib/libc.a.p/libc_machine_powerpc_setjmp.S.o.d -o newlib/libc.a.p/libc_machine_powerpc_setjmp.S.o -c ../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/machine/powerpc/setjmp.S
../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/machine/powerpc/setjmp.S:30:2: error: #error 32-bit
30 | #error 32-bit

```

* get rid of forced error in data/newlib/libc/machine/powerpc/setjmp.S

```
cd pythondata-software-picolibc$
# //#error 32-bit
pip3 install .
```

```
a2o_32.py --csr-csv csr.csv

../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/include/machine/endian.h:74:30: error: expected statement before ‘)’ token
74 | #define ntohl(_x) __ntohl(_x))
| ^
../../../../../../../../../../home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/xdr/xdr_rec.c:827:12: note: in expansion of macro ‘ntohl’
827 | header = ntohl (header);
| ^~~~~
[438/795] Compiling C object newlib/libc.a.p/libc_time_strftime.c.o
ninja: build stopped: subcommand failed.
```

* fix syntax in data/newlib/libc/include/machine/endian.h

```
cd pythondata-software-picolibc$
# #define htonl(_x) __htonl(_x)
# #define htons(_x) __htons(_x)
# #define ntohl(_x) __ntohl(_x)
# #define ntohs(_x) __ntohs(_x)
pip3 install .
```

* add crt0savres.s for missing 32b functions
* now compiles and builds
* seems semi-copacetic so far

```
powerpc-linux-gnu-objdump -d build/cmod7_kintex/software/bios/bios.elf > bios_32.d
```




#### Core and wishbone wrapper with extra stuff for Litex integration #### Core and wishbone wrapper with extra stuff for Litex integration


* create a2o/core.py and a2o.py (SOC) from a2p * create a2o/core.py and a2o.py (SOC) from a2p

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