Browse Source

kintex

master
openpowerwtf 4 months ago
parent
commit
5532d33b52
  1. 3
      dev/build/litex/build/cmod7_kintex/gateware/build_cmod7_kintex.sh
  2. 81
      dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex.tcl
  3. 1891
      dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex.v
  4. 54
      dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex.xdc
  5. 0
      dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex_main_ram.init
  6. 29
      dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex_mem.init
  7. 3790
      dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex_rom.init
  8. 0
      dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex_sram.init
  9. 357
      dev/build/litex/build/cmod7_kintex/software/include/generated/csr.h
  10. 8
      dev/build/litex/build/cmod7_kintex/software/include/generated/git.h
  11. 30
      dev/build/litex/build/cmod7_kintex/software/include/generated/mem.h
  12. 1
      dev/build/litex/build/cmod7_kintex/software/include/generated/output_format.ld
  13. 6
      dev/build/litex/build/cmod7_kintex/software/include/generated/regions.ld
  14. 65
      dev/build/litex/build/cmod7_kintex/software/include/generated/soc.h
  15. 26
      dev/build/litex/build/cmod7_kintex/software/include/generated/variables.mak

3
dev/build/litex/build/cmod7_kintex/gateware/build_cmod7_kintex.sh

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# Autogenerated by LiteX / git: 6932fc51
set -e
vivado -mode batch -source cmod7_kintex.tcl

81
dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex.tcl

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# Create Project

create_project -force -name cmod7_kintex -part xc7k410t-ffv676-1
set_msg_config -id {Common 17-55} -new_severity {Warning}

# Add Sources

add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/a2o_litex}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/trilib}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/trilib_clk1x}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/work}
read_verilog {/data/projects/a2o/dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex.v}

# Add EDIFs


# Add IPs


# Add constraints

read_xdc cmod7_kintex.xdc
set_property PROCESSING_ORDER EARLY [get_files cmod7_kintex.xdc]

# Add pre-synthesis commands


# Synthesis

synth_design -directive default -top cmod7_kintex -part xc7k410t-ffv676-1

# Synthesis report

report_timing_summary -file cmod7_kintex_timing_synth.rpt
report_utilization -hierarchical -file cmod7_kintex_utilization_hierarchical_synth.rpt
report_utilization -file cmod7_kintex_utilization_synth.rpt

# Optimize design

opt_design -directive default

# Add pre-placement commands


# Placement

place_design -directive default

# Placement report

report_utilization -hierarchical -file cmod7_kintex_utilization_hierarchical_place.rpt
report_utilization -file cmod7_kintex_utilization_place.rpt
report_io -file cmod7_kintex_io.rpt
report_control_sets -verbose -file cmod7_kintex_control_sets.rpt
report_clock_utilization -file cmod7_kintex_clock_utilization.rpt

# Add pre-routing commands


# Routing

route_design -directive default
phys_opt_design -directive default
write_checkpoint -force cmod7_kintex_route.dcp

# Routing report

report_timing_summary -no_header -no_detailed_paths
report_route_status -file cmod7_kintex_route_status.rpt
report_drc -file cmod7_kintex_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file cmod7_kintex_timing.rpt
report_power -file cmod7_kintex_power.rpt

# Bitstream generation

write_bitstream -force cmod7_kintex.bit

# End

quit

1891
dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex.v

File diff suppressed because it is too large Load Diff

54
dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex.xdc

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################################################################################
# IO constraints
################################################################################
# serial:0.tx
set_property LOC J18 [get_ports {serial_tx}]
set_property IOSTANDARD LVCMOS33 [get_ports {serial_tx}]

# serial:0.rx
set_property LOC J17 [get_ports {serial_rx}]
set_property IOSTANDARD LVCMOS33 [get_ports {serial_rx}]

# clk12:0
set_property LOC F22 [get_ports {clk12}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk12}]

# user_led:0
set_property LOC A17 [get_ports {user_led0}]
set_property IOSTANDARD LVCMOS33 [get_ports {user_led0}]

# user_led:1
set_property LOC C16 [get_ports {user_led1}]
set_property IOSTANDARD LVCMOS33 [get_ports {user_led1}]

# user_btn:0
set_property LOC A18 [get_ports {user_btn0}]
set_property IOSTANDARD LVCMOS33 [get_ports {user_btn0}]

# user_btn:1
set_property LOC B18 [get_ports {user_btn1}]
set_property IOSTANDARD LVCMOS33 [get_ports {user_btn1}]

################################################################################
# Design constraints
################################################################################

################################################################################
# Clock constraints
################################################################################


create_clock -name clk12 -period 83.333 [get_ports clk12]

set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets crg_clkin]] -asynchronous

################################################################################
# False path constraints
################################################################################


set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]

set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]

set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]

0
dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex_main_ram.init

29
dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex_mem.init

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2d
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2d
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00

3790
dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex_rom.init

File diff suppressed because it is too large Load Diff

0
dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex_sram.init

357
dev/build/litex/build/cmod7_kintex/software/include/generated/csr.h

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//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
//--------------------------------------------------------------------------------
#include <generated/soc.h>
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
#include <stdint.h>
#include <system.h>
#ifndef CSR_ACCESSORS_DEFINED
#include <hw/common.h>
#endif /* ! CSR_ACCESSORS_DEFINED */
#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#endif

/* leds */
#define CSR_LEDS_BASE (CSR_BASE + 0x1800L)
#define CSR_LEDS_OUT_ADDR (CSR_BASE + 0x1800L)
#define CSR_LEDS_OUT_SIZE 1
static inline uint32_t leds_out_read(void) {
return csr_read_simple((CSR_BASE + 0x1800L));
}
static inline void leds_out_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x1800L));
}

/* buttons */
#define CSR_BUTTONS_BASE (CSR_BASE + 0x2000L)
#define CSR_BUTTONS_IN_ADDR (CSR_BASE + 0x2000L)
#define CSR_BUTTONS_IN_SIZE 1
static inline uint32_t buttons_in_read(void) {
return csr_read_simple((CSR_BASE + 0x2000L));
}

/* ctrl */
#define CSR_CTRL_BASE (CSR_BASE + 0x2800L)
#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x2800L)
#define CSR_CTRL_RESET_SIZE 1
static inline uint32_t ctrl_reset_read(void) {
return csr_read_simple((CSR_BASE + 0x2800L));
}
static inline void ctrl_reset_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x2800L));
}
#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
#define CSR_CTRL_RESET_SOC_RST_SIZE 1
static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t ctrl_reset_soc_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_soc_rst_extract(word);
}
static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
#define CSR_CTRL_RESET_CPU_RST_SIZE 1
static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t ctrl_reset_cpu_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_cpu_rst_extract(word);
}
static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x2804L)
#define CSR_CTRL_SCRATCH_SIZE 1
static inline uint32_t ctrl_scratch_read(void) {
return csr_read_simple((CSR_BASE + 0x2804L));
}
static inline void ctrl_scratch_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x2804L));
}
#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x2808L)
#define CSR_CTRL_BUS_ERRORS_SIZE 1
static inline uint32_t ctrl_bus_errors_read(void) {
return csr_read_simple((CSR_BASE + 0x2808L));
}

/* identifier_mem */
#define CSR_IDENTIFIER_MEM_BASE (CSR_BASE + 0x3000L)

/* timer0 */
#define CSR_TIMER0_BASE (CSR_BASE + 0x3800L)
#define CSR_TIMER0_LOAD_ADDR (CSR_BASE + 0x3800L)
#define CSR_TIMER0_LOAD_SIZE 1
static inline uint32_t timer0_load_read(void) {
return csr_read_simple((CSR_BASE + 0x3800L));
}
static inline void timer0_load_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x3800L));
}
#define CSR_TIMER0_RELOAD_ADDR (CSR_BASE + 0x3804L)
#define CSR_TIMER0_RELOAD_SIZE 1
static inline uint32_t timer0_reload_read(void) {
return csr_read_simple((CSR_BASE + 0x3804L));
}
static inline void timer0_reload_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x3804L));
}
#define CSR_TIMER0_EN_ADDR (CSR_BASE + 0x3808L)
#define CSR_TIMER0_EN_SIZE 1
static inline uint32_t timer0_en_read(void) {
return csr_read_simple((CSR_BASE + 0x3808L));
}
static inline void timer0_en_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x3808L));
}
#define CSR_TIMER0_UPDATE_VALUE_ADDR (CSR_BASE + 0x380cL)
#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
static inline uint32_t timer0_update_value_read(void) {
return csr_read_simple((CSR_BASE + 0x380cL));
}
static inline void timer0_update_value_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x380cL));
}
#define CSR_TIMER0_VALUE_ADDR (CSR_BASE + 0x3810L)
#define CSR_TIMER0_VALUE_SIZE 1
static inline uint32_t timer0_value_read(void) {
return csr_read_simple((CSR_BASE + 0x3810L));
}
#define CSR_TIMER0_EV_STATUS_ADDR (CSR_BASE + 0x3814L)
#define CSR_TIMER0_EV_STATUS_SIZE 1
static inline uint32_t timer0_ev_status_read(void) {
return csr_read_simple((CSR_BASE + 0x3814L));
}
#define CSR_TIMER0_EV_STATUS_ZERO_OFFSET 0
#define CSR_TIMER0_EV_STATUS_ZERO_SIZE 1
static inline uint32_t timer0_ev_status_zero_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_status_zero_read(void) {
uint32_t word = timer0_ev_status_read();
return timer0_ev_status_zero_extract(word);
}
#define CSR_TIMER0_EV_PENDING_ADDR (CSR_BASE + 0x3818L)
#define CSR_TIMER0_EV_PENDING_SIZE 1
static inline uint32_t timer0_ev_pending_read(void) {
return csr_read_simple((CSR_BASE + 0x3818L));
}
static inline void timer0_ev_pending_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x3818L));
}
#define CSR_TIMER0_EV_PENDING_ZERO_OFFSET 0
#define CSR_TIMER0_EV_PENDING_ZERO_SIZE 1
static inline uint32_t timer0_ev_pending_zero_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_pending_zero_read(void) {
uint32_t word = timer0_ev_pending_read();
return timer0_ev_pending_zero_extract(word);
}
static inline uint32_t timer0_ev_pending_zero_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void timer0_ev_pending_zero_write(uint32_t plain_value) {
uint32_t oldword = timer0_ev_pending_read();
uint32_t newword = timer0_ev_pending_zero_replace(oldword, plain_value);
timer0_ev_pending_write(newword);
}
#define CSR_TIMER0_EV_ENABLE_ADDR (CSR_BASE + 0x381cL)
#define CSR_TIMER0_EV_ENABLE_SIZE 1
static inline uint32_t timer0_ev_enable_read(void) {
return csr_read_simple((CSR_BASE + 0x381cL));
}
static inline void timer0_ev_enable_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x381cL));
}
#define CSR_TIMER0_EV_ENABLE_ZERO_OFFSET 0
#define CSR_TIMER0_EV_ENABLE_ZERO_SIZE 1
static inline uint32_t timer0_ev_enable_zero_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_enable_zero_read(void) {
uint32_t word = timer0_ev_enable_read();
return timer0_ev_enable_zero_extract(word);
}
static inline uint32_t timer0_ev_enable_zero_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void timer0_ev_enable_zero_write(uint32_t plain_value) {
uint32_t oldword = timer0_ev_enable_read();
uint32_t newword = timer0_ev_enable_zero_replace(oldword, plain_value);
timer0_ev_enable_write(newword);
}

/* uart */
#define CSR_UART_BASE (CSR_BASE + 0x4000L)
#define CSR_UART_RXTX_ADDR (CSR_BASE + 0x4000L)
#define CSR_UART_RXTX_SIZE 1
static inline uint32_t uart_rxtx_read(void) {
return csr_read_simple((CSR_BASE + 0x4000L));
}
static inline void uart_rxtx_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x4000L));
}
#define CSR_UART_TXFULL_ADDR (CSR_BASE + 0x4004L)
#define CSR_UART_TXFULL_SIZE 1
static inline uint32_t uart_txfull_read(void) {
return csr_read_simple((CSR_BASE + 0x4004L));
}
#define CSR_UART_RXEMPTY_ADDR (CSR_BASE + 0x4008L)
#define CSR_UART_RXEMPTY_SIZE 1
static inline uint32_t uart_rxempty_read(void) {
return csr_read_simple((CSR_BASE + 0x4008L));
}
#define CSR_UART_EV_STATUS_ADDR (CSR_BASE + 0x400cL)
#define CSR_UART_EV_STATUS_SIZE 1
static inline uint32_t uart_ev_status_read(void) {
return csr_read_simple((CSR_BASE + 0x400cL));
}
#define CSR_UART_EV_STATUS_TX_OFFSET 0
#define CSR_UART_EV_STATUS_TX_SIZE 1
static inline uint32_t uart_ev_status_tx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_ev_status_tx_read(void) {
uint32_t word = uart_ev_status_read();
return uart_ev_status_tx_extract(word);
}
#define CSR_UART_EV_STATUS_RX_OFFSET 1
#define CSR_UART_EV_STATUS_RX_SIZE 1
static inline uint32_t uart_ev_status_rx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_ev_status_rx_read(void) {
uint32_t word = uart_ev_status_read();
return uart_ev_status_rx_extract(word);
}
#define CSR_UART_EV_PENDING_ADDR (CSR_BASE + 0x4010L)
#define CSR_UART_EV_PENDING_SIZE 1
static inline uint32_t uart_ev_pending_read(void) {
return csr_read_simple((CSR_BASE + 0x4010L));
}
static inline void uart_ev_pending_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x4010L));
}
#define CSR_UART_EV_PENDING_TX_OFFSET 0
#define CSR_UART_EV_PENDING_TX_SIZE 1
static inline uint32_t uart_ev_pending_tx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_ev_pending_tx_read(void) {
uint32_t word = uart_ev_pending_read();
return uart_ev_pending_tx_extract(word);
}
static inline uint32_t uart_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_ev_pending_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_ev_pending_read();
uint32_t newword = uart_ev_pending_tx_replace(oldword, plain_value);
uart_ev_pending_write(newword);
}
#define CSR_UART_EV_PENDING_RX_OFFSET 1
#define CSR_UART_EV_PENDING_RX_SIZE 1
static inline uint32_t uart_ev_pending_rx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_ev_pending_rx_read(void) {
uint32_t word = uart_ev_pending_read();
return uart_ev_pending_rx_extract(word);
}
static inline uint32_t uart_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_ev_pending_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_ev_pending_read();
uint32_t newword = uart_ev_pending_rx_replace(oldword, plain_value);
uart_ev_pending_write(newword);
}
#define CSR_UART_EV_ENABLE_ADDR (CSR_BASE + 0x4014L)
#define CSR_UART_EV_ENABLE_SIZE 1
static inline uint32_t uart_ev_enable_read(void) {
return csr_read_simple((CSR_BASE + 0x4014L));
}
static inline void uart_ev_enable_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x4014L));
}
#define CSR_UART_EV_ENABLE_TX_OFFSET 0
#define CSR_UART_EV_ENABLE_TX_SIZE 1
static inline uint32_t uart_ev_enable_tx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_ev_enable_tx_read(void) {
uint32_t word = uart_ev_enable_read();
return uart_ev_enable_tx_extract(word);
}
static inline uint32_t uart_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_ev_enable_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_ev_enable_read();
uint32_t newword = uart_ev_enable_tx_replace(oldword, plain_value);
uart_ev_enable_write(newword);
}
#define CSR_UART_EV_ENABLE_RX_OFFSET 1
#define CSR_UART_EV_ENABLE_RX_SIZE 1
static inline uint32_t uart_ev_enable_rx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_ev_enable_rx_read(void) {
uint32_t word = uart_ev_enable_read();
return uart_ev_enable_rx_extract(word);
}
static inline uint32_t uart_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_ev_enable_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_ev_enable_read();
uint32_t newword = uart_ev_enable_rx_replace(oldword, plain_value);
uart_ev_enable_write(newword);
}
#define CSR_UART_TXEMPTY_ADDR (CSR_BASE + 0x4018L)
#define CSR_UART_TXEMPTY_SIZE 1
static inline uint32_t uart_txempty_read(void) {
return csr_read_simple((CSR_BASE + 0x4018L));
}
#define CSR_UART_RXFULL_ADDR (CSR_BASE + 0x401cL)
#define CSR_UART_RXFULL_SIZE 1
static inline uint32_t uart_rxfull_read(void) {
return csr_read_simple((CSR_BASE + 0x401cL));
}

#endif

8
dev/build/litex/build/cmod7_kintex/software/include/generated/git.h

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
//--------------------------------------------------------------------------------
#ifndef __GENERATED_GIT_H
#define __GENERATED_GIT_H

#define LITEX_GIT_SHA1 "6932fc51"
#endif

30
dev/build/litex/build/cmod7_kintex/software/include/generated/mem.h

@ -0,0 +1,30 @@ @@ -0,0 +1,30 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
//--------------------------------------------------------------------------------
#ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H

#ifndef ROM_BASE
#define ROM_BASE 0x00000000L
#define ROM_SIZE 0x00010000
#endif

#ifndef SRAM_BASE
#define SRAM_BASE 0x00010000L
#define SRAM_SIZE 0x00010000
#endif

#ifndef MAIN_RAM_BASE
#define MAIN_RAM_BASE 0x00100000L
#define MAIN_RAM_SIZE 0x00000100
#endif

#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#define CSR_SIZE 0x00010000
#endif

#ifndef MEM_REGIONS
#define MEM_REGIONS "ROM 0x00000000 0x10000 \nSRAM 0x00010000 0x10000 \nMAIN_RAM 0x00100000 0x100 \nCSR 0xfff00000 0x10000 "
#endif
#endif

1
dev/build/litex/build/cmod7_kintex/software/include/generated/output_format.ld

@ -0,0 +1 @@ @@ -0,0 +1 @@
OUTPUT_FORMAT("elf64-powerpcle")

6
dev/build/litex/build/cmod7_kintex/software/include/generated/regions.ld

@ -0,0 +1,6 @@ @@ -0,0 +1,6 @@
MEMORY {
rom : ORIGIN = 0x00000000, LENGTH = 0x00010000
sram : ORIGIN = 0x00010000, LENGTH = 0x00010000
main_ram : ORIGIN = 0x00100000, LENGTH = 0x00000100
csr : ORIGIN = 0xfff00000, LENGTH = 0x00010000
}

65
dev/build/litex/build/cmod7_kintex/software/include/generated/soc.h

@ -0,0 +1,65 @@ @@ -0,0 +1,65 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
//--------------------------------------------------------------------------------
#ifndef __GENERATED_SOC_H
#define __GENERATED_SOC_H
#define CONFIG_CLOCK_FREQUENCY 100000000
#define CONFIG_CPU_HAS_INTERRUPT
#define CONFIG_CPU_RESET_ADDR 0
#define CONFIG_CPU_TYPE_A2O
#define CONFIG_CPU_VARIANT_STANDARD
#define CONFIG_CPU_HUMAN_NAME "a2owb"
#define CONFIG_CPU_NOP "nop"
#define CONFIG_ROM_INIT 1
#define CONFIG_CSR_DATA_WIDTH 32
#define CONFIG_CSR_ALIGNMENT 32
#define CONFIG_BUS_STANDARD "WISHBONE"
#define CONFIG_BUS_DATA_WIDTH 32
#define CONFIG_BUS_ADDRESS_WIDTH 32
#define CONFIG_BUS_BURSTING 0
#define TIMER0_INTERRUPT 1
#define UART_INTERRUPT 0

#ifndef __ASSEMBLER__
static inline int config_clock_frequency_read(void) {
return 100000000;
}
static inline int config_cpu_reset_addr_read(void) {
return 0;
}
static inline const char * config_cpu_human_name_read(void) {
return "a2owb";
}
static inline const char * config_cpu_nop_read(void) {
return "nop";
}
static inline int config_rom_init_read(void) {
return 1;
}
static inline int config_csr_data_width_read(void) {
return 32;
}
static inline int config_csr_alignment_read(void) {
return 32;
}
static inline const char * config_bus_standard_read(void) {
return "WISHBONE";
}
static inline int config_bus_data_width_read(void) {
return 32;
}
static inline int config_bus_address_width_read(void) {
return 32;
}
static inline int config_bus_bursting_read(void) {
return 0;
}
static inline int timer0_interrupt_read(void) {
return 1;
}
static inline int uart_interrupt_read(void) {
return 0;
}
#endif // !__ASSEMBLER__

#endif

26
dev/build/litex/build/cmod7_kintex/software/include/generated/variables.mak

@ -0,0 +1,26 @@ @@ -0,0 +1,26 @@
PACKAGES=libc libcompiler_rt libbase libfatfs liblitespi liblitedram libliteeth liblitesdcard liblitesata bios
PACKAGE_DIRS=/data/projects/litex/litex/soc/software/libc /data/projects/litex/litex/soc/software/libcompiler_rt /data/projects/litex/litex/soc/software/libbase /data/projects/litex/litex/soc/software/libfatfs /data/projects/litex/litex/soc/software/liblitespi /data/projects/litex/litex/soc/software/liblitedram /data/projects/litex/litex/soc/software/libliteeth /data/projects/litex/litex/soc/software/liblitesdcard /data/projects/litex/litex/soc/software/liblitesata /data/projects/litex/litex/soc/software/bios
LIBS=libc libcompiler_rt libbase libfatfs liblitespi liblitedram libliteeth liblitesdcard liblitesata
TRIPLE=--not-found--
CPU=a2o
CPUFAMILY=ppc64
CPUFLAGS=-ma2 -m64 -mlittle-endian -mabi=elfv2 -fnostack-protector -D__a2o__
CPUENDIANNESS=little
CLANG=0
CPU_DIRECTORY=/data/projects/a2o/dev/build/litex/a2o
SOC_DIRECTORY=/data/projects/litex/litex/soc
PICOLIBC_DIRECTORY=/home/wtf/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data
COMPILER_RT_DIRECTORY=/usr/local/lib/python3.8/dist-packages/pythondata_software_compiler_rt-0.0.post6206-py3.8.egg/pythondata_software_compiler_rt/data
export BUILDINC_DIRECTORY
BUILDINC_DIRECTORY=/data/projects/a2o/dev/build/litex/build/cmod7_kintex/software/include
LIBC_DIRECTORY=/data/projects/litex/litex/soc/software/libc
LIBCOMPILER_RT_DIRECTORY=/data/projects/litex/litex/soc/software/libcompiler_rt
LIBBASE_DIRECTORY=/data/projects/litex/litex/soc/software/libbase
LIBFATFS_DIRECTORY=/data/projects/litex/litex/soc/software/libfatfs
LIBLITESPI_DIRECTORY=/data/projects/litex/litex/soc/software/liblitespi
LIBLITEDRAM_DIRECTORY=/data/projects/litex/litex/soc/software/liblitedram
LIBLITEETH_DIRECTORY=/data/projects/litex/litex/soc/software/libliteeth
LIBLITESDCARD_DIRECTORY=/data/projects/litex/litex/soc/software/liblitesdcard
LIBLITESATA_DIRECTORY=/data/projects/litex/litex/soc/software/liblitesata
BIOS_DIRECTORY=/data/projects/litex/litex/soc/software/bios
LTO=0
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