verilator litex soc

dev/build/litex/a2o.py

@@ -1,6 +1,7 @@
 #!/usr/bin/python3
 
 # A2O Test - build with core.py
+# a2o.py --csr-csv csr.csv --no-compile-software
 # a2o.py --csr-csv csr.csv --no-compile-software --build  [--sys-clk-freq 50e6]
 #
 
@@ -11,6 +12,7 @@ from migen import *
 
 # wtf - use local platform
 from platforms import cmod7
+from platforms import cmod7_kintex
 
 # wtf - use local core (not built into litex)
 # help python find package
@@ -52,9 +54,7 @@ class _CRG(Module):
         self.clock_domains.cd_idelay    = ClockDomain()
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
-        #wtf if you do this it crashes later..request() takes the pin off 'available' list i think; so can't put to csr reg
-        #no idea how to modify the reset signal later
-        #maybe have to change this class to take a signal you create first?
+        #wtf how do you add btn to reset sig?
         #x = platform.request('user_btn',0)
         self.comb += pll.reset.eq(self.rst)
         #self.comb += pll.reset.eq(self.rst)
@@ -77,28 +77,29 @@ class BaseSoC(SoCCore):
                        **kwargs):
 
         coreUART = True
+        #romSize = 128*1024
+        #ramSize = 128*1024
+        romSize = 64 * 1024;
+        ramSize = 64 * 1024;
+        ddrSize = 16*1024*1024
+
 
         # try build using different fpga's
         #platform = cmod7.Platform()
         #platform = cmod7.Platform(fpga='xc7a200t-SBG484-1')  # arty-200
-        #platform = cmod7.Platform(fpga='xc7k325t-ffv676-1 )  #
-        platform = cmod7.Platform(fpga='xc7k410t-ffv676-1')   #
+        #platform = cmod7_kintex.Platform(fpga='xc7k325t-ffv676-1 )  # kintex-325
+        platform = cmod7_kintex.Platform(fpga='xc7k410t-ffv676-1')   # kintex-410
 
         SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32,
-            with_uart=coreUART, integrated_sram_size=0, integrated_rom_size=0,
-            ident='A2O Test', ident_version=True, uart_baudrate=uart_baudrate,
+            #with_uart=coreUART, integrated_rom_size=romSize, integrated_sram_size=ramSize, don't set rom/ram if doing it below!!!!!
+            with_uart=coreUART, integrated_rom_size=0, integrated_sram_size=0,
+            ident='A2O', ident_version=True, uart_baudrate=uart_baudrate,
             cpu_type='a2o')
 
         print(f'Building variant={self.cpu.variant}.')
 
-        # no irq yet? should be able to connect
-        #self.add_constant('UART_POLLING')
-
-         #!!!!!!!!!!!!!!!!!!
-         # any hints here on using uarts (to get the gpio one working)?
-         # cult-soft.de/2920/05/24/litex-uart-hub
-         # played a little below but didnt try if it works
-         #!!!!!!!!!!!!!!!!!!
+        # no irq yet, but should be able to connect; need irq handler in crt0.s
+        self.add_constant('UART_POLLING')
 
         # this appears to be how to set up fixed csr order but not sure it works this way.  https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py
         #SoCCore.csr_map
@@ -114,12 +115,11 @@ class BaseSoC(SoCCore):
         #    'uart':       0,
         #    'timer0':     1,
         #}}
-
         self.mem_map = {
-         'csr':      0xFFF00000,
-         'main_ram': 0x00100000,
          'rom':      0x00000000,
          'ram':      0x00010000,
+         'main_ram': 0x01000000,
+         'csr':      0xFFF00000
         }
 
         # CRG --------------------------------------------------------------------------------------
@@ -157,9 +157,12 @@ class BaseSoC(SoCCore):
         outFile.close()
         print('Wrote mem.init')
 
-        self.add_rom('rom', origin=self.mem_map['rom'], size=0x10000, contents=romdata)  # name, origin, size, contents=[], mode='r'
+        self.add_rom('rom', origin=self.mem_map['rom'], size=romSize, contents=romdata)  # name, origin, size, contents=[], mode='r'
         # make this sram to match what linker expects
-        self.add_ram('sram', origin=self.mem_map['ram'], size=0x10000)                   # name, origin, size, contents=[], mode='rw'
+        self.add_ram('sram', origin=self.mem_map['ram'], size=ramSize)                   # name, origin, size, contents=[], mode='rw'
+
+        # External Mem -----------------------------------------------------------------------------
+        self.add_ram('main_ram', origin=self.mem_map['main_ram'], size=ddrSize)
 
         # Leds -------------------------------------------------------------------------------------
         self.submodules.leds = LedChaser(
@@ -174,20 +177,17 @@ class BaseSoC(SoCCore):
         )
         self.add_csr('buttons')
 
-        # SRAM -------------------------------------------------------------------------------------
-        self.add_ram('main_ram', origin=self.mem_map['main_ram'], size=0x100)
-
         # Analyzer ---------------------------------------------------------------------------------
         if with_analyzer:
             analyzer_signals = [
-                self.cpu.dbus.stb,
-                self.cpu.dbus.cyc,
-                self.cpu.dbus.adr,
-                self.cpu.dbus.we,
-                self.cpu.dbus.ack,
-                self.cpu.dbus.sel,
-                self.cpu.dbus.dat_w,
-                self.cpu.dbus.dat_r,
+                self.cpu.wb_stb,
+                self.cpu.wb_cyc,
+                self.cpu.wb_adr,
+                self.cpu.wb_we,
+                self.cpu.wb_ack,
+                self.cpu.wb_sel,
+                self.cpu.wb_datw,
+                self.cpu.wb.datr,
             ]
             self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
                 depth        = 512,

dev/build/litex/a2o/boot-helper.S

@@ -0,0 +1,50 @@
+.section .text, "ax", @progbits
+# called by bios boot commands to do the jump to code (r1,r2,r3 can be specified in terminal 'boot' command)
+
+.include "defines.s"
+
+.global boot_helper
+# extern void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr);
+
+.align 4
+boot_helper:
+   lis      r3,_fstack@h
+   ori      r3,r3,_fstack@l   # top o mem
+   mtctr    r6
+   bctr                       # jump to callee
+
+   # play with stack. what could go wrong?
+   # r1 = new top
+   #   orig lr         20(r1)
+   #   ancient r1      16(r1)
+   #   local1          12(r1)
+   #   local2           8(r1)
+   #   (next lr)        4(r1)
+   #   orig r1          0(r1)
+   # doesnt help...getting a bad op, probably blr to wrong address off stack, within calls to do a putchar
+   stwu     r1,-32(r1)
+   mflr     r0
+   stw      r0,36(r1)
+   stw      r3,8(r1)
+   stw      r4,12(r1)
+   stw      r5,16(r1)
+   stw      r6,20(r1)
+   li       r3,'w'
+   slwi     r3,r3,8
+   ori      r3,r3,'t'
+   slwi     r3,r3,8
+   ori      r3,r3,'f'
+   slwi     r3,r3,8
+   ori      r3,r3,'!'
+   stw      r3,24(r1)
+   stw      r3,28(r1)
+   lwz      r0,36(r1)
+   mtlr     r6
+   addi     r1,r1,32
+   blr
+
+   #addi     r1,r1,32      # leave frame on stack
+   #mtctr    r6
+   #bctrl                   # jump to callee
+
+   b        .

dev/build/litex/a2o/core.py

@@ -38,6 +38,8 @@ class A2O(CPU, AutoCSR):
 
    @property
    def mem_map(self):
+      return {}
+      # how do you make this be default but not overwrite any defines in soc.py?
       return {
          'rom':          0x00000000,   # on-board
          'sram':         0x00004000,   # on-board
@@ -78,8 +80,8 @@ class A2O(CPU, AutoCSR):
       self.reset_address    = 0x00000000
 
       self.cpu_params = dict(
-         i_clk_1x            = ClockSignal('sys'),
-         i_clk_2x            = ClockSignal('sys2x'),
+         i_clk               = ClockSignal('sys'),
+         #i_clk_2x            = ClockSignal('sys2x'),
          i_rst               = ResetSignal() | self.reset,
 
          # how do i connect these to csr?
@@ -96,7 +98,9 @@ class A2O(CPU, AutoCSR):
          #wtf i guess you get these names from the Inteface() def - but what about other sigs?
          o_wb_cyc            = dbus.cyc,
          o_wb_stb            = dbus.stb,
-         o_wb_adr            = Cat(dbus.adr,Signal(2)),
+#wtf litex is declaring wire [29:0] a2o_dbus_adr and connecting directly here but a2owb;wb_adr is [0:31]
+#         o_wb_adr            = Cat(dbus.adr,Signal(2)),
+         o_wb_adr            = Cat(Signal(2),dbus.adr),  # wb adr [31:2] = a2o adr[0:29]
          o_wb_we             = dbus.we,
          o_wb_sel            = dbus.sel,
          o_wb_datw           = dbus.dat_w,

dev/build/litex/a2o/crt0.S

@@ -0,0 +1,973 @@
+# debug code for mem
+#.set TEST_MEM,1
+
+# boot code for rom integration with litex terminal code
+# requires 64K ROM
+# got rid of int handlers for now to shrink this code
+
+# cmod7 - skip ddr stuff
+
+# set for sim bypass version
+#.set SIM,1                 # this skips uart, ram check, etc.
+#.set DELAY,0x00000005
+
+# general delay (leds)
+# should probs put this in a mem loc so it can be easily changed w/o compile
+.set DELAY,0x01000000       # hardware (~1 secs)
+#.set DELAY,0x00000100
+
+# csr.csv
+# need to set up CONFIG:
+#csr_base,dna,0xfff00000,,
+#csr_base,xadc,0xfff00800,,
+#csr_base,leds,0xfff01000,,
+#csr_base,buttons,0xfff01800,,
+#csr_base,i2c,0xfff02000,,
+#csr_base,motor_0,0xfff02800,,
+#csr_base,ctrl,0xfff03000,,
+#csr_base,identifier_mem,0xfff03800,,
+#csr_base,timer0,0xfff04000,,
+#csr_base,uart,0xfff04800,,
+
+#
+#memory_region,rom,0x00000000,65536,cached
+#memory_region,ram,0x00010000,4096,cached
+#memory_region,sram,0x80000000,4096,cached
+#memory_region,csr,0xfff00000,65536,io
+
+.include "defines.s"
+
+#.section .hwinit # @00000000
+# change to use litex linker.ld
+.section .text
+
+.global _start
+
+# reset
+_start:
+      b         boot_start
+
+.set REGSAVE,0x04
+regsave:
+               .long 0
+               .long 0
+               .long 0
+               .long 0
+               .long 0
+               .long 0
+               .long 0
+               .long 0
+
+
+# ddr setup delay (intracommand)
+.ifdef SIM
+.set DDR_DELAY,0x00000010  # sim
+.else
+.set DDR_DELAY,0x00020000
+.endif
+
+.align 6
+.set CONFIG,0x40
+
+#.set SRAM_BASE, 0x00010000  # get from _fdata
+#.set STACK, 0x0001FFF8 # first save of r0 is 4 past this! #get from _fstack
+
+.set MAGIC, 0x08675309
+
+rom_lo:         .long 0
+rom_hi:         .long 0xFFFF
+sram_lo:        .long 0                # get from link syms; does chk for -1 to skip test
+sram_hi:        .long 0
+ddr_lo:         .long 0xFFFFFFFF       # -1: no gots
+ddr_hi:         .long 0xF7FFFFFF
+
+ctrl:           .long 0xFFF03000
+cpu:            .long 0xFFFFFFFF       # -1: no gots
+uart:           .long 0xFFF04800       # -1: no gots
+leds:           .long 0xFFF01000       # -1: no gots
+switches:       .long 0xFFFFFFFF       # -1: no gots
+buttons:        .long 0xFFF01800       # -1: no gots
+sdram:          .long 0xFFFFFFFF
+eob_data:       .long MAGIC
+
+# offsets for uart functions
+.set UART_RXTX, 0x00
+.set UART_TXFULL, 0x04
+.set UART_RXEMPTY, 0x08
+.set UART_EV_STATUS, 0x0C
+.set UART_EV_PENDING, 0x10
+.set UART_EV_ENABLE, 0x14
+.set UART_TXEMPTY, 0x18
+.set UART_RXFULL, 0x1C
+.set UARTX_RXTX, 0x20
+.set UARTX_TXFULL, 0x24
+.set UARTX_RXEMPTY, 0x28
+.set UARTX_EV_STATUS, 0x2C
+.set UARTX_EV_PENDING, 0x30
+.set UARTX_EV_ENABLE, 0x34
+.set UARTX_TXEMPTY, 0x38
+.set UARTX_RXFULL, 0x3C
+
+.align 7
+.set CONFIG_DDR,0x80
+
+#wtf can litex be forced to put these at specific offsets from csr_base???
+sdram_dfii:    .long 0xFFF06000        # csr_register,sdram_dfii_control,0xfff05000,1,rw
+ddr_cmd_delay: .long DDR_DELAY
+ddr_chk_loops: .long 1  # 0=infinite
+ddr_mrs0:      .long 0  # wtf eventually set these up as config vals
+
+# offsets from sdram_dfii base
+.set DFII_CONTROL, 0x00
+.set DFII_PI0_COMMAND, 0x04
+.set DFII_PI0_COMMAND_ISSUE, 0x08
+.set DFII_PI0_ADDRESS, 0x0C
+.set DFII_PI0_BADDRESS, 0x10
+.set DFII_PI0_WRDATA, 0x14
+.set DFII_PI0_RDDATA, 0x18
+.set DFII_PI1_COMMAND, 0x1C
+.set DFII_PI1_COMMAND_ISSUE, 0x20
+.set DFII_PI1_ADDRESS, 0x24
+.set DFII_PI1_BADDRESS, 0x28
+.set DFII_PI1_WRDATA, 0x2C
+.set DFII_PI1_RDDATA, 0x30
+
+# bits
+.set CONTROL_SEL, 0x01
+.set CONTROL_CKE, 0x02
+.set CONTROL_ODT, 0x04        #wtf does this exist for ddr2??
+.set CONTROL_RESET_N, 0x08
+.set COMMAND_CS, 0x01
+.set COMMAND_WE, 0x02
+.set COMMAND_CAS, 0x04
+.set COMMAND_RAS, 0x08
+.set COMMAND_WRDATA, 0x10
+.set COMMAND_RDDATA, 0x20
+.set DDR_PARM_DELAY, 0x00020000
+
+#
+.align 8
+int_100:
+      b         .
+
+# mck
+.align 8
+int_200:
+      b         .
+
+# dsi
+.align 8
+int_300:
+      b         .
+
+# dseg
+.align 7
+int_380:
+      b         .
+
+# isi
+.align 8
+int_400:
+      b         .
+
+# iseg
+.align 7
+int_480:
+      b         .
+
+# external
+.align 8
+int_500:
+      b         .
+
+# alignment
+.align 8
+int_600:
+      b         .
+
+# program
+.align 8
+int_700:
+      b         .
+
+# fp unavailable
+.align 8
+int_800:
+      b         .
+
+# dec
+.align 8
+int_900:
+      b         .
+
+# dec hyp
+.align 7
+int_980:
+      b         .
+
+# doorbell
+.align 8# offsets from sdram_dfii base
+.set DFII_CONTROL, 0x00
+.set DFII_PI0_COMMAND, 0x04
+.set DFII_PI0_COMMAND_ISSUE, 0x08
+.set DFII_PI0_ADDRESS, 0x0C
+.set DFII_PI0_BADDRESS, 0x10
+.set DFII_PI0_WRDATA, 0x14
+.set DFII_PI0_RDDATA, 0x18
+.set DFII_PI1_COMMAND, 0x1C
+.set DFII_PI1_COMMAND_ISSUE, 0x20
+.set DFII_PI1_ADDRESS, 0x24
+.set DFII_PI1_BADDRESS, 0x28
+.set DFII_PI1_WRDATA, 0x2C
+.set DFII_PI1_RDDATA, 0x30
+
+# bits
+.set CONTROL_SEL, 0x01
+.set CONTROL_CKE, 0x02
+.set CONTROL_ODT, 0x04        #wtf does this exist for ddr2??
+.set CONTROL_RESET_N, 0x08
+.set COMMAND_CS, 0x01
+.set COMMAND_WE, 0x02
+.set COMMAND_CAS, 0x04
+.set COMMAND_RAS, 0x08
+.set COMMAND_WRDATA, 0x10
+.set COMMAND_RDDATA, 0x20
+.set DDR_PARM_DELAY, 0x00020000
+int_C00:
+      b         .
+
+# trace
+.align 8
+int_D00:
+      b         .
+
+# dsi hyp
+.align 8
+int_E00:
+      b         .
+
+# isi hyp
+.align 5
+int_E20:
+      b         .
+
+# emulation hyp
+.align 5
+int_E40:
+      b         .
+
+# maintenance hyp
+.align 5
+int_E60:
+      b         .
+
+# doorbell hyp
+.align 5
+int_E80:
+      b         .
+
+# virtualization hyp
+.align 5
+int_EA0:
+      b         .
+
+# reserved
+.align 5
+int_EC0:
+      b         .
+
+# reserved
+.align 5
+int_EE0:
+      b         .
+
+# perfmon
+.align 5
+int_F00:
+      b         .
+
+# vector unavailable
+.align 5
+int_F20:
+      b         .
+
+# vsx unavailable
+.align 5
+int_F40:
+      b         .
+
+# facility unavailable
+.align 5
+int_F60:
+      b         .
+
+# facility unavailable hyp
+.align 5
+int_F80:
+      b         .
+
+# ------------------------------------------------------------------------------------------------------------------------------
+# init facilities and memories before blastoff
+#
+
+.macro load32  rx,v
+      li       \rx,0
+      oris     \rx,\rx,\v>>16
+      ori      \rx,\rx,\v&0x0000FFFF
+.endm
+
+.macro load16swiz rx,v
+      li       \rx,0
+      ori      \rx,\rx,(\v<<8)&0xFF00
+      ori      \rx,\rx,(\v>>8)&0x00FF
+.endm
+
+.macro delayr  rx
+      mtctr    \rx
+      bdnz     .
+.endm
+
+.macro delay   rx,v
+      li       \rx,0
+      oris     \rx,\rx,\v>>16
+      ori      \rx,\rx,\v&0x0000FFFF
+      mtctr    \rx
+      bdnz     .
+.endm
+
+.org 0x1000
+boot_start:
+
+########################################################################################################################################
+# sim only - go quickly to main() w/no console output
+
+.ifdef SIM
+      li         r3,0x01
+      bl         set_leds_b0
+      bl         uart_init
+      li         r3,0x02
+      bl         set_leds_b0
+      b          jump2main
+.endif
+
+########################################################################################################################################
+# clear and init core facilities
+
+      li         r3,0x01
+      bl         core_init
+      bl         set_leds_b0        # 01; core init'd
+      delay      r10,DELAY
+
+########################################################################################################################################
+# console
+
+console:
+
+      li         r3,0x02            # 02; console init
+      bl         set_leds_b0
+      bl         uart_init
+      delay      r10,DELAY
+
+      li         r3,0x03            # 03; console init done
+      bl         set_leds_b0
+      delay      r10,DELAY
+
+      li         r3,DATA+MSG_HELLO
+      bl         console_println
+
+########################################################################################################################################
+# check on-board sram
+
+.ifdef TEST_MEM
+      b          test_mem
+.endif
+
+sram_chk:
+      lwz        r10,sram_lo(r0)
+      cmpwi      r10,-1
+      beq        ddr_chk
+      # use syms
+      lis        r10,_fdata@h
+      ori        r10,r10,_fdata@l
+      #lwz        r11,sram_hi(r0)
+      # use stack top; else have to add sym to linker.ld
+      lis        r11,_fstack@h
+      ori        r11,r11,_fstack@l
+      addi       r11,r11,3
+
+      subf       r11,r10,r11
+      addi       r11,r11,1
+      srwi       r11,r11,4          # num word reads
+      mtctr      r11
+
+      li         r12,0
+      oris       r12,r12,0x0867
+      ori        r12,r12,0x5309     # data
+
+sram_writes:
+      stw        r12,0(r10)
+      addi       r10,r10,4
+      bdnz       sram_writes
+      # use syms
+      #lwz        r10,sram_lo(r0)
+      lis        r10,_fdata@h
+      ori        r10,r10,_fdata@l
+      mtctr      r11
+
+sram_reads:
+      lwz        r13,0(r10)
+      cmpw       r13,r12
+      bne        fail
+      addi       r10,r10,4
+      bdnz       sram_reads
+
+      li         r3,0x07            # 07; sram checked
+      bl         set_leds_b0
+      delay      r10,DELAY
+
+      li         r3,DATA+MSG_SRAM
+      bl         console_println
+
+# sram test someday
+########################################################################################################################################
+# check ddr, n loops
+
+#wtf is there a way to disable/enable l2????
+
+ddr_chk:
+      lwz        r10,ddr_lo(r0)
+      cmpwi      r10,-1
+      beq        rominit
+
+      li         r3,0x0F            # 0F; dram checking
+      bl         set_leds_b0
+      li         r3,DATA+MSG_DDR_0
+      bl         console_println
+
+      li         r8,0               # loop counter
+      lwz        r9,ddr_chk_loops(r0)
+
+      li         r12,0              # data
+      oris       r12,r12,0x6708
+      ori        r12,r12,0x0953
+
+ddr_start:
+      addi       r8,r8,1
+      mr         r3,r8
+      bl         set_leds_b1        # running pass
+
+      lwz        r10,ddr_lo(r0)
+      lwz        r11,ddr_hi(r0)
+      addi       r11,r11,1
+      subf       r11,r10,r11
+      srwi       r11,r11,2          # word r/w
+      mtctr      r11
+
+ddr_writes:
+      stw        r12,0(r10)
+      addi       r10,r10,4
+      bdnz       ddr_writes
+
+      lwz        r10,ddr_lo(r0)
+      mtctr      r11
+
+ddr_reads:
+      lwz        r13,0(r10)
+      cmpw       r13,r12
+      bne        ddr_fail_save
+      addi       r10,r10,4
+      bdnz       ddr_reads
+
+# loop done
+
+      addi       r12,r12,7            # change pattern
+      cmpwi      r9,0
+      beq        ddr_start
+      cmpw       r8,r9
+      bne        ddr_start
+
+      li         r3,0x0E             # 0E; dram OK
+      bl         set_leds_b0
+      li         r3,0x00
+      bl         set_leds_b1
+      li         r3,DATA+MSG_DDR_1
+      bl         console_println
+      delay      r10,DELAY
+
+########################################################################################################################################
+
+rominit:
+
+      li         r3,DATA+MSG_ROM_INIT
+      bl         console_println
+
+########################################################################################################################################
+# VMA/LMA: copy .data, clear .bss
+
+      # get the linker script symbols needed...
+      #lis        r1,(.TOC.-0)@h
+      #lis         r1,.toc.@h
+      #lis        r6,.got.@h
+      #lwz        r1,_fdata_rom@got(r6)
+
+      lis        r1,_fdata_rom@h
+      ori        r1,r1,_fdata_rom@l
+      lis        r2,_fdata@h
+      ori        r2,r2,_fdata@l
+      lis        r3,_edata_rom@h
+      ori        r3,r3,_edata_rom@l
+      lis        r4,_fbss@h
+      ori        r4,r4,_fbss@l
+      lis        r5,_ebss@h
+      ori        r5,r5,_ebss@l
+
+      subf       r9,r1,r3
+      srwi.      r9,r9,2
+      beq        romcopy_done
+      mtctr      r9
+      addi       r1,r1,-4
+      addi       r2,r2,-4
+
+romcopy:
+      lwzu       r9,4(r1)
+      stwu       r9,4(r2)
+      bdnz       romcopy
+
+romcopy_done:
+      subf       r9,r4,r5
+      srwi.      r9,r9,2
+      beq        romclear_done
+
+      mtctr      r9
+      addi       r4,r4,-4
+      li         r9,0
+
+romclear:
+      stwu       r9,4(r4)
+      bdnz       romclear
+
+romclear_done:
+
+########################################################################################################################################
+
+########################################################################################################################################
+
+process_start:
+
+      li         r3,DATA+MSG_BANNER
+      bl         console_println
+
+jump2main:
+      lis        r1,_fstack@h
+      ori        r1,r1,_fstack@l
+      li         r3, 0            # parm 1
+      b          main
+
+########################################################################################################################################
+
+.ifdef TEST_MEM
+
+.macro asciib  rt,rs
+      andi.    \rt,\rs,0x0F
+      cmpwi    \rt,10
+      blt      +8
+      addi     \rt,\rt,0x11-10
+      addi     \rt,\rt,0x30
+.endm
+
+.macro println_reg  rt
+      rotlwi     \rt,\rt,4
+      asciib     r3,\rt
+      bl         uart_write
+      rotlwi     \rt,\rt,4
+      asciib     r3,\rt
+      bl         uart_write
+      rotlwi     \rt,\rt,4
+      asciib     r3,\rt
+      bl         uart_write
+      rotlwi     \rt,\rt,4
+      asciib     r3,\rt
+      bl         uart_write
+      rotlwi     \rt,\rt,4
+      asciib     r3,\rt
+      bl         uart_write
+      rotlwi     \rt,\rt,4
+      asciib     r3,\rt
+      bl         uart_write
+      rotlwi     \rt,\rt,4
+      asciib     r3,\rt
+      bl         uart_write
+      rotlwi     \rt,\rt,4
+      asciib     r3,\rt
+      bl         uart_write
+      li         r3,0x0D
+      bl         uart_write
+      li         r3,0x0A
+      bl         uart_write
+.endm
+
+# running out of space
+print_r6:
+      mflr       r0
+      println_reg r6
+      mtlr       r0
+      blr
+
+test_mem:
+      lis        r5,1            # start@-
+      ori        r10,r5,0x40     # end@
+
+      load32     r6,0x0a0b0c0d
+      li         r3,'W'
+      bl         uart_write
+      bl print_r6
+
+      #stw        r6,0(r5)
+      #load32     r6,0
+      #stw        r6,4(r5)
+      #stw        r6,8(r5)
+      #stw        r6,12(r5)
+      stb        r6,0(r5)
+      srwi       r6,r6,8
+      stb        r6,5(r5)
+      srwi       r6,r6,8
+      stb        r6,10(r5)
+      srwi       r6,r6,8
+      stb        r6,15(r5)
+      lbz         r6,0(r5)
+      bl print_r6
+      lbz         r6,1(r5)
+      bl print_r6
+      lbz         r6,2(r5)
+      bl print_r6
+      lbz         r6,3(r5)
+      bl print_r6
+      lbz         r6,4(r5)
+      bl print_r6
+      nop
+      nop
+      nop
+      nop
+test_mem_read:
+      lwz        r7,0(r5)
+      li         r3,'R'
+      bl         uart_write
+      println_reg  r7
+      addi       r5,r5,4
+      cmpw       r5,r10
+      blt        test_mem_read
+      #b      .
+      b          sram_chk
+
+.endif
+
+########################################################################################################################################
+# rom: just check high address - could be a crc check
+
+test_rom:
+      lwz        r20,rom_hi(r0)
+      li         r21,-4
+      and        r21,r20,r21
+      lwz        r21,0(r21)
+      lwz        r22,eob_data(r0)
+      cmpw       r21,r22
+      li         r3,1
+      bne        fail
+      bl         set_leds
+
+      b          pass
+
+# put data in sram so it can be read from uart
+ddr_fail_save:
+
+      lis        r1,_fdata@h
+      ori        r1,r1,_fdata@l
+
+      stw        r0,0(1)
+      #stw        r1,4(1)
+      stw        r2,8(1)
+      stw        r3,12(1)       # loops
+      stw        r4,16(1)
+      stw        r5,20(1)
+      stw        r6,24(1)
+      stw        r7,28(1)
+      stw        r8,32(1)
+      stw        r9,36(1)
+      stw        r10,40(1)      # addr
+      stw        r11,44(1)
+      stw        r12,48(1)      # exp
+      stw        r13,52(1)      # act
+      stw        r14,56(1)
+      stw        r15,60(1)
+      stw        r16,64(1)
+      stw        r17,68(1)
+      stw        r18,72(1)
+      stw        r19,76(1)
+      stw        r20,80(1)
+      stw        r21,84(1)
+      stw        r22,88(1)
+      stw        r23,92(1)
+      stw        r24,96(1)
+      stw        r25,100(1)
+      stw        r26,104(1)
+      stw        r27,108(1)
+      stw        r28,112(1)
+      stw        r29,116(1)
+      stw        r30,120(1)
+      stw        r31,124(1)
+
+      mfcr       r31
+      stw        r31,128(1)      # cr
+      mfctr      r31
+      stw        r31,132(1)      # ctr
+      mflr       r31
+      stw        r31,136(1)      # lr
+      mfspr      r31,tar
+      stw        r31,140(1)      # tar
+      li         r31,-1
+      stw        r31,144(1)      # error code
+
+      b          fail
+
+console_echo:
+
+      mflr       r0
+
+      lwz        r5,sram_lo(r0)              # buffer start
+      mr         r6,r5                       # buffer ptr
+
+console_echo_1:
+      bl         uart_read_nonblock          # this could just be uart_read() unless want to do something else while waiting
+      cmpwi      r3, 0
+      beq        console_echo_1
+      bl         uart_read
+
+      cmpwi      r3,0x0A                     # lf
+      beq        console_echo_2
+      cmpwi      r3,0x0D                     # cr
+      beq        console_echo_2
+      stb        r3,0(6)
+      addi       r6,r6,1
+      bl         uart_write
+      b          console_echo_1
+
+console_echo_2:
+# print back the whole line surrounded by <>
+      subf       r3,r5,r6
+      mtctr      r3
+      li         r3,0x0D                     # cr
+      bl         uart_write
+      li         r3,0x0A                     # lf
+      bl         uart_write
+      li         r3,0x3C                     # <
+      bl         uart_write
+      mr         r6,r5                       # start of buffer
+
+console_echo_3:
+      lbz        r3,0(6)
+      bl         uart_write
+      addi       r6,r6,1
+      bdnz       console_echo_3
+
+      li         r3,0x3E                     # >
+      bl         uart_write
+      li         r3,0x0D                     # cr
+      bl         uart_write
+      li         r3,0x0A                     # lf
+      bl         uart_write
+      mr         r6,r5                       # start of buffer
+      b          console_echo_1
+
+      mtlr       r0
+      blr
+
+console_print:
+
+      mflr       r0
+      mr         r5,r3                       # buffer ptr
+
+console_print_1:
+      lbz        r3,0(5)
+      cmpwi      r3,0
+      beq        console_print_2
+      bl         uart_write
+      addi       r5,r5,1
+      bdnz       console_print_1
+
+console_print_2:
+      mtlr       r0
+      blr
+
+console_println:
+      mflr       r0
+      mr         r5,r3                       # buffer ptr
+
+console_println_1:
+      lbz        r3,0(5)
+      cmpwi      r3,0
+      beq        console_println_2
+      bl         uart_write
+      addi       r5,r5,1
+      bdnz       console_println_1
+
+console_println_2:
+      li         r3,0x0D                     # cr
+      bl         uart_write
+      li         r3,0x0A                     # lf
+      bl         uart_write
+
+      mtlr       r0
+      blr
+
+.org 0x1800
+
+pass:
+      mflr       r0
+      li         r3,0x01C0
+      bl         set_leds
+      b          .
+
+.align 6
+# fail w/generic code, or specify
+fail:
+      li         r3,0x6666
+fail_rc:
+      mflr       r0
+      bl         set_leds
+fail_no_rc:
+      b          .
+
+.align 6
+# set up everything that isn't reset; not really needed for fpga
+core_init:
+      blr
+
+# leds 15:0
+get_leds:
+      lwz        r1,leds(r0)
+      lhz        r3,0(1)
+      blr
+
+set_leds:
+      lwz        r1,leds(r0)
+      sth        r3,0(1)
+      blr
+
+# litex csr don't obey sel!?!?!
+set_leds_b0:
+      lwz        r1,leds(r0)
+      #stb        r3,0(1)
+      lhz        r2,0(1)               # 0011
+      andi.      r2,r2,0x00FF
+      slwi       r3,r3,8
+      or         r2,r2,r3
+      sth        r2,0(1)               # 0011
+      blr
+
+set_leds_b1:
+      lwz        r1,leds(r0)
+      lhz        r2,0(1)               # 0011
+      andi.      r2,r2,0xFF00
+      andi.      r3,r3,0x00FF
+      or         r2,r2,r3
+      sth        r2,0(1)               # 0011
+      blr
+
+.align 6
+
+.set UART_EV_TX, 0x1
+.set UART_EV_RX, 0x2
+
+uart_init:
+      lwz        r2, uart(r0)
+      lbz        r1, UART_EV_PENDING(r2)
+      stb        r1, UART_EV_PENDING(r2)
+      li         r1, UART_EV_TX | UART_EV_RX
+      stb        r1, UART_EV_ENABLE(r2)
+      blr
+
+
+uart_read:
+      lwz        r2, uart(r0)
+      lbz        r1, UART_RXEMPTY(r2)
+      cmpwi      r1,0
+      bne        uart_read
+      lbz        r3, UART_RXTX(r2)
+      li         r1, UART_EV_RX
+      stb        r1, UART_EV_PENDING(r2)
+      blr
+
+uart_read_nonblock:
+      lwz        r2, uart(r0)
+      li         r3,0
+      lbz        r1, UART_RXEMPTY(r2)
+      cmpw       r1,r3
+      bne        uart_read_nonblock_1
+      li         r3,1
+uart_read_nonblock_1:
+      blr
+
+uart_write:
+      lwz        r2, uart(r0)
+      lbz        r1, UART_TXFULL(r2)
+      cmpwi      r1,0
+      bne        uart_write
+      stb        r3, UART_RXTX(r2)
+      li         r1, UART_EV_TX
+      stb        r1, UART_EV_PENDING(r2)
+      blr
+
+uart_sync:
+      lwz        r2, uart(r0)
+      lbz        r1, UART_TXFULL(r2)
+      cmpwi      r1,0
+      bne        uart_sync
+      blr
+
+.org 0x1C00
+.set DATA, 0x1C00
+
+msg_hello:
+                .byte 0x0D
+                .byte 0x0A
+                .ascii "A2P POWAflight"
+                .byte 0x0D
+                .byte 0x0A
+                .asciz ""
+
+.align 5
+msg_sram:
+                .ascii "SRAM OK."
+                .asciz ""
+
+
+.align 5
+msg_ddr_0:
+                .ascii "SDRAM TEST..."
+                .asciz ""
+
+.align 5
+.msg_ddr_1:
+                .ascii "SDRAM OK "
+                .ascii "@10000000:"
+                .asciz "17FFFFFF"
+
+.align 5
+.msg_rom:
+                .ascii "Copying"
+                .ascii " ROM to"
+                .asciz " RAM..."
+
+.align 5
+.msg_banner:
+#.include "banner.s"
+                .ascii "Jumping to"
+                .asciz " main()..."
+
+.set MSG_HELLO, 0
+.set MSG_SRAM, MSG_HELLO+32
+.set MSG_DDR_0, MSG_SRAM+32
+.set MSG_DDR_1, MSG_DDR_0+32
+.set MSG_ROM_INIT, MSG_DDR_1+32
+.set MSG_BANNER, MSG_ROM_INIT+32
+

dev/build/litex/a2o/defines.s

@@ -0,0 +1,146 @@
+# © IBM Corp. 2020
+# Licensed under and subject to the terms of the CC-BY 4.0
+# license (https://creativecommons.org/licenses/by/4.0/legalcode). 
+# Additional rights, including the right to physically implement a softcore 
+# that is compliant with the required sections of the Power ISA 
+# Specification, will be available at no cost via the OpenPOWER Foundation. 
+# This README will be updated with additional information when OpenPOWER's 
+# license is available.
+
+#-----------------------------------------
+# Defines
+#-----------------------------------------
+
+# Regs
+
+.set    r0,  0
+.set    r1,  1
+.set    r2,  2
+.set    r3,  3
+.set    r4,  4
+.set    r5,  5
+.set    r6,  6
+.set    r7,  7
+.set    r8,  8
+.set    r9,  9
+.set    r10,10
+.set    r11,11
+.set    r12,12
+.set    r13,13
+.set    r14,14
+.set    r15,15
+.set    r16,16
+.set    r17,17
+.set    r18,18
+.set    r19,19
+.set    r20,20
+.set    r21,21
+.set    r22,22
+.set    r23,23
+.set    r24,24
+.set    r25,25
+.set    r26,26
+.set    r27,27
+.set    r28,28
+.set    r29,29
+.set    r30,30
+.set    r31,31
+
+.set    f0,  0
+.set    f1,  1
+.set    f2,  2
+.set    f3,  3
+.set    f4,  4
+.set    f5,  5
+.set    f6,  6
+.set    f7,  7
+.set    f8,  8
+.set    f9,  9
+.set    f10,10
+.set    f11,11
+.set    f12,12
+.set    f13,13
+.set    f14,14
+.set    f15,15
+.set    f16,16
+.set    f17,17
+.set    f18,18
+.set    f19,19
+.set    f20,20
+.set    f21,21
+.set    f22,22
+.set    f23,23
+.set    f24,24
+.set    f25,25
+.set    f26,26
+.set    f27,27
+.set    f28,28
+.set    f29,29
+.set    f30,30
+.set    f31,31
+
+.set    cr0, 0
+.set    cr1, 1
+.set    cr2, 2
+.set    cr3, 3
+.set    cr4, 4
+.set    cr5, 5
+.set    cr6, 6
+.set    cr7, 7
+
+# SPR numbers
+
+.set    srr0, 26
+.set    srr1, 27
+.set    epcr, 307
+.set    tar, 815
+.set    dsisr, 18
+.set    dar, 19
+
+.set    dbsr, 304
+.set    dbcr0, 308
+.set    dbcr1, 309
+.set    dbcr2, 310
+.set    dbcr3, 848
+
+.set    ivpr, 63
+
+.set    iucr0, 1011
+.set    iucr1, 883
+.set    iucr2, 884
+
+.set    iudbg0, 888
+.set    iudbg1, 889
+.set    iudbg2, 890
+.set    iulfsr, 891
+.set    iullcr, 892
+
+.set    mmucr0, 1020
+.set    mmucr1, 1021
+.set    mmucr2, 1022
+.set    mmucr3, 1023
+
+.set    tb, 268
+.set    tbl, 284
+.set    tbh, 285
+
+.set    dec, 22
+.set    udec, 550
+.set    tsr, 336
+.set    tcr, 340
+
+.set    xucr0, 1014
+.set    xucr1, 851
+.set    xucr2, 1016
+.set    xucr3, 852
+.set    xucr4, 853
+
+.set    tens, 438
+.set    tenc, 439
+.set    tensr, 437
+
+.set    pid, 48
+.set    pir, 286
+.set    pvr, 287
+.set    tir, 446
+

dev/build/litex/a2o/irq.h

@@ -0,0 +1,18 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+static inline void irq_setmask(unsigned int mask) {
+}
+
+static inline unsigned int irq_getmask(void) {
+   return 0;
+}
+
+static inline unsigned int irq_pending(void) {
+   return 0;
+}
+
+static inline void irq_setie(unsigned int mask) {
+}
+
+#endif

dev/build/litex/a2o/system.h

@@ -0,0 +1,61 @@
+// a2p
+
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#include <stdint.h>
+
+/*
+void flush_l2_cache(void) {
+}
+*/
+static void flush_cpu_icache(void);
+static void flush_cpu_dcache(void);
+
+static void flush_cpu_icache(void) {
+}
+static void flush_cpu_dcache(void) {
+}
+
+#define CSR_ACCESSORS_DEFINED
+
+#ifdef __ASSEMBLER__
+#define MMPTR(x) x
+#else /* ! __ASSEMBLER__ */
+
+/* CSRs are stored in subregister slices of CONFIG_CSR_DATA_WIDTH (native
+ * endianness), with the least significant slice at the lowest aligned
+ * (base) address. */
+
+#include <generated/soc.h>
+#if !defined(CONFIG_CSR_DATA_WIDTH)
+#error CSR_DATA_WIDTH MUST be set before including this file!
+#endif
+
+/* CSR subregisters (a.k.a. "simple CSRs") are embedded inside uint32_t
+ * aligned locations: */
+#define MMPTR(a) (*((volatile uint32_t *)(a)))
+
+static inline unsigned long swizzle(unsigned long v);
+
+static inline unsigned long swizzle(unsigned long v) {
+   return ((v & 0x000000FF) << 24) | ((v & 0x0000FF00) <<  8) | ((v & 0x00FF0000) >>  8) | ((v & 0xFF000000) >> 24);
+   //return v;
+}
+
+static inline void csr_write_simple(unsigned long v, unsigned long a)
+{
+	//MMPTR(a) = v;
+   MMPTR(a) = swizzle(v);
+}
+
+static inline unsigned long csr_read_simple(unsigned long a)
+{
+	//return MMPTR(a);
+	return swizzle(MMPTR(a));
+}
+
+#endif /* ! __ASSEMBLER__ */
+
+#endif /* __SYSTEM_H */
+

dev/build/litex/build/cmod7_kintex/gateware/build_cmod7_kintex.sh

@@ -1,3 +1,3 @@
-# Autogenerated by LiteX / git: 6932fc51
+# Autogenerated by LiteX / git: 33ae301d
 set -e
 vivado -mode batch -source cmod7_kintex.tcl

dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex.v

@@ -8,8 +8,8 @@
 //
 // Filename   : cmod7_kintex.v
 // Device     : xc7k410t-ffv676-1
-// LiteX sha1 : 6932fc51
-// Date       : 2022-08-04 09:13:14
+// LiteX sha1 : 33ae301d
+// Date       : 2022-08-15 13:16:22
 //------------------------------------------------------------------------------
 
 
@@ -284,17 +284,6 @@ wire [13:0] sram0_adr;
 wire [31:0] sram0_dat_r;
 reg  [3:0] sram0_we = 4'd0;
 wire [31:0] sram0_dat_w;
-reg  [1:0] leds_storage = 2'd0;
-reg  leds_re = 1'd0;
-reg  [1:0] leds_chaser = 2'd0;
-reg  leds_mode = 1'd0;
-wire leds_wait;
-wire leds_done;
-reg  [24:0] leds_count = 25'd25000000;
-reg  [1:0] leds_leds = 2'd0;
-wire [1:0] buttons_status;
-wire buttons_we;
-reg  buttons_re = 1'd0;
 wire [29:0] interface1_ram_bus_adr;
 wire [31:0] interface1_ram_bus_dat_w;
 wire [31:0] interface1_ram_bus_dat_r;
@@ -307,10 +296,21 @@ wire [2:0] interface1_ram_bus_cti;
 wire [1:0] interface1_ram_bus_bte;
 reg  interface1_ram_bus_err = 1'd0;
 reg  sram1_adr_burst = 1'd0;
-wire [5:0] sram1_adr;
+wire [21:0] sram1_adr;
 wire [31:0] sram1_dat_r;
 reg  [3:0] sram1_we = 4'd0;
 wire [31:0] sram1_dat_w;
+reg  [1:0] leds_storage = 2'd0;
+reg  leds_re = 1'd0;
+reg  [1:0] leds_chaser = 2'd0;
+reg  leds_mode = 1'd0;
+wire leds_wait;
+wire leds_done;
+reg  [24:0] leds_count = 25'd25000000;
+reg  [1:0] leds_leds = 2'd0;
+wire [1:0] buttons_status;
+wire buttons_we;
+reg  buttons_re = 1'd0;
 reg  [13:0] basesoc_adr = 14'd0;
 reg  basesoc_we = 1'd0;
 reg  [31:0] basesoc_dat_w = 32'd0;
@@ -527,7 +527,6 @@ always @(*) begin
 end
 assign bus_errors_status = bus_errors;
 always @(*) begin
-	serial_tx_rs232phytx_next_value1 <= 1'd0;
 	serial_tx_rs232phytx_next_value_ce1 <= 1'd0;
 	tx_enable <= 1'd0;
 	tx_data_rs232phytx_next_value2 <= 8'd0;
@@ -536,6 +535,7 @@ always @(*) begin
 	basesoc_rs232phytx_next_state <= 1'd0;
 	tx_count_rs232phytx_next_value0 <= 4'd0;
 	tx_count_rs232phytx_next_value_ce0 <= 1'd0;
+	serial_tx_rs232phytx_next_value1 <= 1'd0;
 	basesoc_rs232phytx_next_state <= basesoc_rs232phytx_state;
 	case (basesoc_rs232phytx_state)
 		1'd1: begin
@@ -739,6 +739,16 @@ end
 assign sram0_adr = interface0_ram_bus_adr[13:0];
 assign interface0_ram_bus_dat_r = sram0_dat_r;
 assign sram0_dat_w = interface0_ram_bus_dat_w;
+always @(*) begin
+	sram1_we <= 4'd0;
+	sram1_we[0] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[0]);
+	sram1_we[1] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[1]);
+	sram1_we[2] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[2]);
+	sram1_we[3] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[3]);
+end
+assign sram1_adr = interface1_ram_bus_adr[21:0];
+assign interface1_ram_bus_dat_r = sram1_dat_r;
+assign sram1_dat_w = interface1_ram_bus_dat_w;
 assign leds_wait = (~leds_done);
 always @(*) begin
 	leds_leds <= 2'd0;
@@ -750,21 +760,11 @@ always @(*) begin
 end
 assign {user_led1, user_led0} = (leds_leds ^ 1'd0);
 assign leds_done = (leds_count == 1'd0);
-always @(*) begin
-	sram1_we <= 4'd0;
-	sram1_we[0] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[0]);
-	sram1_we[1] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[1]);
-	sram1_we[2] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[2]);
-	sram1_we[3] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[3]);
-end
-assign sram1_adr = interface1_ram_bus_adr[5:0];
-assign interface1_ram_bus_dat_r = sram1_dat_r;
-assign sram1_dat_w = interface1_ram_bus_dat_w;
 always @(*) begin
 	basesoc_wishbone_ack <= 1'd0;
 	basesoc_dat_w <= 32'd0;
-	basesoc_next_state <= 1'd0;
 	basesoc_wishbone_dat_r <= 32'd0;
+	basesoc_next_state <= 1'd0;
 	basesoc_adr <= 14'd0;
 	basesoc_we <= 1'd0;
 	basesoc_next_state <= basesoc_state;
@@ -801,7 +801,7 @@ always @(*) begin
 	slave_sel <= 4'd0;
 	slave_sel[0] <= (shared_adr[29:14] == 1'd0);
 	slave_sel[1] <= (shared_adr[29:14] == 1'd1);
-	slave_sel[2] <= (shared_adr[29:6] == 13'd4096);
+	slave_sel[2] <= (shared_adr[29:22] == 1'd1);
 	slave_sel[3] <= (shared_adr[29:14] == 16'd65520);
 end
 assign ram_bus_adr = shared_adr;
@@ -839,9 +839,9 @@ assign basesoc_wishbone_cyc = (shared_cyc & slave_sel[3]);
 assign shared_err = (((ram_bus_err | interface0_ram_bus_err) | interface1_ram_bus_err) | basesoc_wishbone_err);
 assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack));
 always @(*) begin
-	shared_ack <= 1'd0;
 	error <= 1'd0;
 	shared_dat_r <= 32'd0;
+	shared_ack <= 1'd0;
 	shared_ack <= (((ram_bus_ack | interface0_ram_bus_ack) | interface1_ram_bus_ack) | basesoc_wishbone_ack);
 	shared_dat_r <= (((({32{slave_sel_r[0]}} & ram_bus_dat_r) | ({32{slave_sel_r[1]}} & interface0_ram_bus_dat_r)) | ({32{slave_sel_r[2]}} & interface1_ram_bus_dat_r)) | ({32{slave_sel_r[3]}} & basesoc_wishbone_dat_r));
 	if (done) begin
@@ -942,8 +942,8 @@ always @(*) begin
 end
 assign csr_bankarray_csrbank3_en0_r = csr_bankarray_interface3_bank_bus_dat_w[0];
 always @(*) begin
-	csr_bankarray_csrbank3_en0_re <= 1'd0;
 	csr_bankarray_csrbank3_en0_we <= 1'd0;
+	csr_bankarray_csrbank3_en0_re <= 1'd0;
 	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd2))) begin
 		csr_bankarray_csrbank3_en0_re <= csr_bankarray_interface3_bank_bus_we;
 		csr_bankarray_csrbank3_en0_we <= (~csr_bankarray_interface3_bank_bus_we);
@@ -969,8 +969,8 @@ always @(*) begin
 end
 assign csr_bankarray_csrbank3_ev_status_r = csr_bankarray_interface3_bank_bus_dat_w[0];
 always @(*) begin
-	csr_bankarray_csrbank3_ev_status_re <= 1'd0;
 	csr_bankarray_csrbank3_ev_status_we <= 1'd0;
+	csr_bankarray_csrbank3_ev_status_re <= 1'd0;
 	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd5))) begin
 		csr_bankarray_csrbank3_ev_status_re <= csr_bankarray_interface3_bank_bus_we;
 		csr_bankarray_csrbank3_ev_status_we <= (~csr_bankarray_interface3_bank_bus_we);
@@ -1011,8 +1011,8 @@ assign csr_bankarray_csrbank3_ev_enable0_w = timer_enable_storage;
 assign csr_bankarray_csrbank4_sel = (csr_bankarray_interface4_bank_bus_adr[13:9] == 4'd8);
 assign uart_rxtx_r = csr_bankarray_interface4_bank_bus_dat_w[7:0];
 always @(*) begin
-	uart_rxtx_we <= 1'd0;
 	uart_rxtx_re <= 1'd0;
+	uart_rxtx_we <= 1'd0;
 	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin
 		uart_rxtx_re <= csr_bankarray_interface4_bank_bus_we;
 		uart_rxtx_we <= (~csr_bankarray_interface4_bank_bus_we);
@@ -1056,8 +1056,8 @@ always @(*) begin
 end
 assign csr_bankarray_csrbank4_ev_enable0_r = csr_bankarray_interface4_bank_bus_dat_w[1:0];
 always @(*) begin
-	csr_bankarray_csrbank4_ev_enable0_re <= 1'd0;
 	csr_bankarray_csrbank4_ev_enable0_we <= 1'd0;
+	csr_bankarray_csrbank4_ev_enable0_re <= 1'd0;
 	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd5))) begin
 		csr_bankarray_csrbank4_ev_enable0_re <= csr_bankarray_interface4_bank_bus_we;
 		csr_bankarray_csrbank4_ev_enable0_we <= (~csr_bankarray_interface4_bank_bus_we);
@@ -1334,6 +1334,10 @@ always @(posedge sys_clk) begin
 	if (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & ((~interface0_ram_bus_ack) | sram0_adr_burst))) begin
 		interface0_ram_bus_ack <= 1'd1;
 	end
+	interface1_ram_bus_ack <= 1'd0;
+	if (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & ((~interface1_ram_bus_ack) | sram1_adr_burst))) begin
+		interface1_ram_bus_ack <= 1'd1;
+	end
 	if (leds_done) begin
 		leds_chaser <= {leds_chaser, (~leds_chaser[1])};
 	end
@@ -1347,10 +1351,6 @@ always @(posedge sys_clk) begin
 	end else begin
 		leds_count <= 25'd25000000;
 	end
-	interface1_ram_bus_ack <= 1'd0;
-	if (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & ((~interface1_ram_bus_ack) | sram1_adr_burst))) begin
-		interface1_ram_bus_ack <= 1'd1;
-	end
 	basesoc_state <= basesoc_next_state;
 	slave_sel_r <= slave_sel;
 	if (wait_1) begin
@@ -1554,13 +1554,13 @@ always @(posedge sys_clk) begin
 		timer_value <= 32'd0;
 		ram_bus_ack <= 1'd0;
 		interface0_ram_bus_ack <= 1'd0;
+		interface1_ram_bus_ack <= 1'd0;
 		leds_storage <= 2'd0;
 		leds_re <= 1'd0;
 		leds_chaser <= 2'd0;
 		leds_mode <= 1'd0;
 		leds_count <= 25'd25000000;
 		buttons_re <= 1'd0;
-		interface1_ram_bus_ack <= 1'd0;
 		slave_sel_r <= 4'd0;
 		count <= 20'd1000000;
 		csr_bankarray_sel_r <= 1'd0;
@@ -1580,10 +1580,10 @@ end
 //------------------------------------------------------------------------------
 
 //------------------------------------------------------------------------------
-// Memory mem: 29-words x 8-bit
+// Memory mem: 24-words x 8-bit
 //------------------------------------------------------------------------------
 // Port 0 | Read: Sync  | Write: ---- | 
-reg [7:0] mem[0:28];
+reg [7:0] mem[0:23];
 initial begin
 	$readmemh("cmod7_kintex_mem.init", mem);
 end
@@ -1695,14 +1695,14 @@ assign sram0_dat_r = sram[sram_adr0];
 
 
 //------------------------------------------------------------------------------
-// Memory main_ram: 64-words x 32-bit
+// Memory main_ram: 4194304-words x 32-bit
 //------------------------------------------------------------------------------
 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
-reg [31:0] main_ram[0:63];
+reg [31:0] main_ram[0:4194303];
 initial begin
 	$readmemh("cmod7_kintex_main_ram.init", main_ram);
 end
-reg [5:0] main_ram_adr0;
+reg [21:0] main_ram_adr0;
 always @(posedge sys_clk) begin
 	if (sram1_we[0])
 		main_ram[sram1_adr][7:0] <= sram1_dat_w[7:0];
@@ -1719,8 +1719,7 @@ assign sram1_dat_r = main_ram[main_ram_adr0];
 
 a2owb a2owb(
 	.cfg_wr(1'd0),
-	.clk_1x(sys_clk),
-	.clk_2x(sys2x_clk),
+	.clk(sys_clk),
 	.externalInterrupt(a2o_interrupt[0]),
 	.externalInterruptS(a2o_interruptS),
 	.rst((sys_rst | a2o_reset)),
@@ -1728,7 +1727,7 @@ a2owb a2owb(
 	.timerInterrupt(a2o_interrupt[1]),
 	.wb_ack(a2o_dbus_ack),
 	.wb_datr(a2o_dbus_dat_r),
-	.wb_adr({a2o, a2o_dbus_adr}),
+	.wb_adr({a2o_dbus_adr, a2o}),
 	.wb_cyc(a2o_dbus_cyc),
 	.wb_datw(a2o_dbus_dat_w),
 	.wb_sel(a2o_dbus_sel),
@@ -1887,5 +1886,5 @@ MMCME2_ADV #(
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2022-08-04 09:13:14.
+//  Auto-Generated by LiteX on 2022-08-15 13:16:22.
 //------------------------------------------------------------------------------

dev/build/litex/build/cmod7_kintex/gateware/cmod7_kintex_mem.init

@@ -2,11 +2,6 @@
 32
 4f
 20
-54
-65
-73
-74
-20
 32
 30
 32
@@ -15,15 +10,15 @@
 30
 38
 2d
-30
-34
+31
+35
 20
-30
-39
-3a
 31
 33
 3a
 31
-34
+36
+3a
+32
+32
 00

dev/build/litex/build/cmod7_kintex/software/include/generated/csr.h

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
+// Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22
 //--------------------------------------------------------------------------------
 #include <generated/soc.h>
 #ifndef __GENERATED_CSR_H

dev/build/litex/build/cmod7_kintex/software/include/generated/git.h

@@ -1,8 +1,8 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
+// Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22
 //--------------------------------------------------------------------------------
 #ifndef __GENERATED_GIT_H
 #define __GENERATED_GIT_H
 
-#define LITEX_GIT_SHA1 "6932fc51"
+#define LITEX_GIT_SHA1 "33ae301d"
 #endif

dev/build/litex/build/cmod7_kintex/software/include/generated/mem.h

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
+// Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22
 //--------------------------------------------------------------------------------
 #ifndef __GENERATED_MEM_H
 #define __GENERATED_MEM_H
@@ -15,8 +15,8 @@
 #endif
 
 #ifndef MAIN_RAM_BASE
-#define MAIN_RAM_BASE 0x00100000L
-#define MAIN_RAM_SIZE 0x00000100
+#define MAIN_RAM_BASE 0x01000000L
+#define MAIN_RAM_SIZE 0x01000000
 #endif
 
 #ifndef CSR_BASE
@@ -25,6 +25,6 @@
 #endif
 
 #ifndef MEM_REGIONS
-#define MEM_REGIONS "ROM       0x00000000 0x10000 \nSRAM      0x00010000 0x10000 \nMAIN_RAM  0x00100000 0x100 \nCSR       0xfff00000 0x10000 "
+#define MEM_REGIONS "ROM       0x00000000 0x10000 \nSRAM      0x00010000 0x10000 \nMAIN_RAM  0x01000000 0x1000000 \nCSR       0xfff00000 0x10000 "
 #endif
 #endif

dev/build/litex/build/cmod7_kintex/software/include/generated/regions.ld

@@ -1,6 +1,6 @@
 MEMORY {
 	rom : ORIGIN = 0x00000000, LENGTH = 0x00010000
 	sram : ORIGIN = 0x00010000, LENGTH = 0x00010000
-	main_ram : ORIGIN = 0x00100000, LENGTH = 0x00000100
+	main_ram : ORIGIN = 0x01000000, LENGTH = 0x01000000
 	csr : ORIGIN = 0xfff00000, LENGTH = 0x00010000
 }

dev/build/litex/build/cmod7_kintex/software/include/generated/soc.h

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
+// Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22
 //--------------------------------------------------------------------------------
 #ifndef __GENERATED_SOC_H
 #define __GENERATED_SOC_H
@@ -10,6 +10,7 @@
 #define CONFIG_CPU_VARIANT_STANDARD
 #define CONFIG_CPU_HUMAN_NAME "a2owb"
 #define CONFIG_CPU_NOP "nop"
+#define UART_POLLING
 #define CONFIG_ROM_INIT 1
 #define CONFIG_CSR_DATA_WIDTH 32
 #define CONFIG_CSR_ALIGNMENT 32

dev/build/litex/cellanal.py

@@ -0,0 +1,128 @@
+#!/usr/bin/python3
+# parse list of netnames, combine bits
+
+import re
+
+inFiles = ['cells_ff.txt', 'cells_lut.txt']
+
+#parent = 'A2P_WB'
+parent = 'a2p_i/A2P_WB/inst'
+
+areas = {
+   'IC': {'re': r'' + parent + '/IBusCachedPlugin_*'},
+   'decode': {'re': r'' + parent + '/decode_*'},
+   'execute': {'re': r'' + parent + '/execute_*'},
+   'regfile': {'re': r'' + parent + '/RegFilePlugin_*'},
+   'hazards': {'re': r'' + parent + '/Hazards_*'},
+   'ALU2': {'re': r'' + parent + '/ALU2_*'},
+   'MULDIV': {'re': r'' + parent + '/MULDIV*'},   # 1,2
+   'memory': {'re': r'' + parent + '/memory_*'},
+   'DC': {'re': r'' + parent + '/dataCache*'},
+   'SPR' :{'re': r'' + parent + '/SPRPlugin_*'},
+   'MSR' :{'re': r'' + parent + '/MSR_*'},
+   'writeBack': {'re': r'' + parent + '/writeBack_*'},
+   'ibus': {'re': r'' + parent + '/iBusWB_*'},
+   'dbus': {'re': r'' + parent + '/dBusWB_*'},
+   'SPINAL _zz_': {'re': r'' + parent + '/_zz_*'}
+}
+
+def analyze(inFile, areas, printSigs=False, printZZ=False):
+   sigs = {}
+
+   with open(inFile) as f:
+      lines = f.readlines()
+      for line in lines:
+         line = line.strip()
+         if line == '':
+            next
+         if line[0] == '*':
+            next
+         if '[' in line:
+            sig = line[0:line.find('[')]
+            strand = int(line[line.find('[')+1:line.find(']')])
+         else:
+            sig = line
+            strand = None
+
+         if strand is None:
+            sigs[sig] = {'len': 1}
+         else:
+            if sig in sigs:
+               sigs[sig]['bits'].append(strand)
+               sigs[sig]['len'] += 1
+            else:
+               sigs[sig] = {'len': 1, 'bits': [strand]}
+
+   total = 0
+   for name in sigs:
+      sig = sigs[name]
+      if 'bits' in sig:
+         sig['bits'] = sorted(sig['bits'], key=int)
+      total += sig['len']
+      if printSigs:
+         print(name, sig)
+      for areaName in areas:
+         area = areas[areaName]
+         match = re.match(area['re'], name)
+         if match is not None:
+            area['total'] += sigs[name]['len']
+            area['sigs'].append(name)
+            if 'matchedAreas' in sig:
+               print(f'*** Signal in multiple areas: {name}')
+               sig['matchedAreas'].append(areaName)
+            else:
+               sig['matchedAreas'] = [areaName]
+   print()
+
+   print(f'Total: {total}')
+   print()
+
+   totalAreas = 0
+   for name in areas:
+      area = areas[name]
+      print(f'{name:30s} {area["total"]:4d}')
+      totalAreas += area["total"]
+   print(f'{"Total in matched areas":30s}{totalAreas:5d}')
+   print()
+
+   if total != totalAreas:
+      print('Not accounted for in areas:')
+      for name in sigs:
+         sig = sigs[name]
+         if 'matchedAreas' not in sig:
+            print(f' {name}')
+      print()
+
+   totals = [0] * 5000
+
+   for name in sigs:
+      sig = sigs[name]
+      totals[sig['len']] += 1
+      if sig['len'] > 32:
+         print(f'*** >32 bits ({sig["len"]}): {name} ***')
+
+   running = 0
+   print('Totals by cells:')
+   for i in range(1, len(totals)):
+      running += i * totals[i]
+      if totals[i] != 0:
+         print(f' {i:4d}:{totals[i]:4d} {running:5d}')
+
+   if printZZ:
+      print('SPINAL _zz_')
+      a = areas['SPINAL _zz_']
+      for s in a['sigs']:
+         print(f' {s}')
+
+   return sigs, areas
+
+for f in inFiles:
+
+   for a in areas:
+      area = areas[a]
+      area['total'] = 0
+      area['sigs'] = []
+
+   print()
+   print(f'--- {f} ---')
+   analyze(f, areas, printSigs=False)

dev/build/litex/csr.csv

@@ -1,5 +1,5 @@
 #--------------------------------------------------------------------------------
-# Auto-generated by LiteX (6932fc51) on 2022-08-04 07:49:47
+# Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22
 #--------------------------------------------------------------------------------
 csr_base,leds,0xfff01800,,
 csr_base,buttons,0xfff02000,,
@@ -35,6 +35,7 @@ constant,config_cpu_type_a2o,None,,
 constant,config_cpu_variant_standard,None,,
 constant,config_cpu_human_name,a2owb,,
 constant,config_cpu_nop,nop,,
+constant,uart_polling,None,,
 constant,config_rom_init,1,,
 constant,config_csr_data_width,32,,
 constant,config_csr_alignment,32,,
@@ -46,5 +47,5 @@ constant,timer0_interrupt,1,,
 constant,uart_interrupt,0,,
 memory_region,rom,0x00000000,65536,cached
 memory_region,sram,0x00010000,65536,cached
-memory_region,main_ram,0x00100000,256,cached
+memory_region,main_ram,0x01000000,16777216,cached
 memory_region,csr,0xfff00000,65536,io

dev/build/litex/init.tcl

@@ -0,0 +1,18 @@
+proc startsim {} {
+   launch_simulation -mode behavioral
+   open_wave_config {wtf.wcfg}   
+   restart
+   source {sim.tcl}
+}
+
+proc rerun {} {
+   restart
+   source {sim.tcl}
+}
+
+proc jumpctr {{runCycs 100} {value 4} {stickCycs 5}} {
+   set f [add_force A2P_WB/execute_BranchPlugin_CTR -radix dec $value]
+   runCyc $stickCycs
+   remove_forces $f
+   runCyc $runCycs
+}

dev/build/litex/log.py

@@ -0,0 +1,272 @@
+# general text parser
+
+import os
+import sys
+from time import sleep
+import glob
+import json
+import re
+#import jsonpickle
+
+# config
+# file (inc. glob)
+# list of searches: type (re, etc), singe/multiline, text, template
+
+class Spec:
+   def __init__(self):
+      self.val = None
+      self.multiline = False
+      self.re = False
+      self.post = None   # postprocessor function
+      self.ci = False    # case-insensitive
+      self.flags = 0     # re flags
+      self.matchOnly = False  # return re match, or whole result (if not multiline)
+      self.before = 0
+      self.after = 0
+      # start from prev?      
+      # callback for every match?
+      self.search = False  # use re.search instead of re.match
+
+class Config:
+   def __init__(self):
+      self.specs = None
+      self.title = None
+    
+   def toJson(self):
+      return json.dumps(self, default=lambda o: o.__dict__)      
+
+class Log:
+
+   def __init__(self, config=None):
+      self.config = config
+    
+   # process all matching files, or newest only
+   def processGlob(self, g, spec, newest=False):
+      files = glob.glob(g)
+      if newest:
+         files = [max(files, key=os.path.getctime)]
+      for f in files:
+         processFile(f, spec)
+
+   # read file 
+   def processFile(self, fn, spec):
+      contents = None
+      lines = None
+
+      # process spec list in order
+      results = []
+      for s in spec:
+         
+         if s.multiline and contents is None:
+            with open(fn, 'rt') as f:
+               contents = f.read()        
+         elif lines is None:
+            lines = []
+            with open(fn, 'rt') as f:
+               for l in f:
+                  lines.append(l.rstrip('\n'))
+
+         v = []
+         if s.re:
+            if s.multiline:
+               r = re.findall(s.val, contents, s.flags) 
+               for i in range(len(r)):
+                  v.append(r[i])
+            else:
+               for i in range(len(lines)):
+                  l = lines[i]
+                  fn = re.match if not s.search else re.search
+                  res = fn(s.val, l, s.flags)
+                  if res is not None:
+                     if s.matchOnly:
+                        v.append(res.groups())
+                     else:
+                        if s.before == -1:
+                           for j in range(0, i):
+                              v.append(lines[j])
+                        elif s.before > 0:
+                           for j in range(max(0, i-s.before), i):
+                              v.append(lines[j])
+                        v.append(l)
+                        if s.after == -1:
+                           for j in range(i+1, len(lines)):
+                              v.append(lines[j])
+                        elif s.after > 0:
+                           for j in range(i+1, i+1+s.after):
+                              v.append(lines[j])
+                     
+         else:
+            if s.multiline:
+               p = 0
+               while p < len(contents):
+                  p1 = contents.find(s.val, p)
+                  if p1 == -1:
+                     break
+                  v.append(p1)
+                  p += len(p1)
+            else:
+               for i in range(len(lines)):
+                  l = lines[i]
+                  if l.find(s.val) != -1:
+                     if s.before == -1:
+                        for j in range(0, i):
+                           v.append(lines[j])
+                     elif s.before > 0:
+                        for j in range(max(0, i-s.before), i):
+                           v.append(lines[j])
+                     v.append(l)
+                     if s.after == -1:
+                        for j in range(i+1, len(lines)):
+                           v.append(lines[j])
+                     elif s.after > 0:
+                        for j in range(i+1, i+1+s.after):
+                           v.append(lines[j])
+         
+         results.append(v)
+
+      return results
+
+if __name__ == '__main__':
+   
+   import os.path, time
+   import argparse
+   parser = argparse.ArgumentParser()
+   parser.add_argument('logFile')
+   parser.add_argument('-l', '--loops', type=int, dest='loops', default=200, help='loops to run; default=200')
+   parser.add_argument('-m', '--move', type=int, dest='move', default=10, help='rate of movement (1/n iterations); default=10')
+   parser.add_argument('--test', dest='testVal', default=None, help='test value')
+   args = parser.parse_args()   
+
+   logFile = args.logFile
+
+   s0 = Spec()
+   s0.val = r'.*Command.*-hierarchical (.*)\*.*'
+   s0.re = True
+   s0.matchOnly = True
+
+   specs = [s0]
+   log = Log()
+   res = log.processFile(logFile, specs)
+   
+   comps = []
+   for r in res:
+      for i in r:
+         comps.append({
+            'name': i[0],
+            'luts': -1
+         })
+
+   s0.val = r'.*Slice LUTs.*?\|(.*?)\|'
+
+   res = log.processFile(logFile, specs)
+   
+   for r in res:
+      for i in range(len(r)):
+         comps[i]['luts'] = r[i][0]
+
+
+   mod = time.ctime(os.path.getmtime(logFile))
+   print(f"report: {logFile} [{mod}]")
+   for i in range(len(comps)):
+      print(f"{comps[i]['name']:16}: {comps[i]['luts']:>7}")
+
+
+   quit()
+   # openroad testing
+   
+   s0 = Spec()
+   s0.val = r'^Yosys .* \(git sha1'
+   s0.re = True
+
+   specs = [s0]
+
+   log = Log()
+
+   res = log.processFile(logFile, specs)
+   #print('Line:')
+   #print(res[0][0])
+
+   s0.val = r'(Yosys .* \(git sha1.*)\n'
+   s0.multiline = True
+   res = log.processFile(logFile, specs)
+   #print('Multiline:')
+   #print(res[0][0])
+
+   s1 = Spec()
+   s1.val = r'(306\.25\.1\.2\..*?)\nRemoving temp directory.'
+   s1.re = True
+   s1.multiline = True
+   s1.flags = re.DOTALL # want to match \n's
+
+   specs = [s1]
+   res = log.processFile(logFile, specs)
+   #print(res[0][0])
+
+   s1.val = r'(306\.28\. Printing statistics\..*?\n.*?\n\n.*?)\n\n'
+   res = log.processFile(logFile, specs)
+   #print(res[0][0])
+
+   print('Report: ' + logFile)
+   print('')
+
+   s0 = Spec()
+   s0.val = r'^Yosys .* \(git sha1'
+   s0.re = True
+
+   s1 = Spec()
+   s1.val = r'\n(318\. Printing statistics\..*Number of cells:.*?\n)'
+   s1.re = True
+   s1.multiline = True
+   s1.flags = re.DOTALL
+
+   s2 = Spec()
+   s2.val = r'^319\.'
+   s2.re = True
+   s2.multiline = False
+   s2.after = -1
+
+   specs = [s0, s1, s2]
+   config = Config()
+   config.specs = specs
+
+   res = log.processFile(logFile, config.specs)
+   for i in range(len(res)):
+      for l in res[i]:
+         print(l)
+      print('')
+
+   quit()
+
+   # python makes this hard for even trivial objects
+   print('Writing config.json...')
+
+   configJson = json.dumps(config, default=lambda x: x.__dict__)
+   #configJson = jsonpickle.encode(config)
+   print(configJson)
+   #quit()
+   #
+   #configJson = json.dumps(config.toJson(), indent=2)
+   with open('config.json', 'w') as configFile:
+      configFile.write(configJson)
+      configFile.close()
+
+   print('Reading config.json...')
+   print('')
+
+   print('string')
+   with open('config.json', 'r') as configFile:
+      print(configFile.read())
+      configFile.close()   
+
+   print('loads')
+   with open('config.json', 'r') as configFile:
+      config = json.loads(configFile.read())
+      print(config)
+      configFile.close()   
+
+   res = log.processFile(logFile, config.specs)
+   for i in range(len(res)):
+      for l in res[i]:
+         print(l)
+      print('')
+ 

dev/build/litex/make

@@ -0,0 +1,41 @@
+#!/usr/bin/bash
+
+code=../../src/test3/rom.init
+vivado=vivado
+dir=`pwd`
+
+soc=a2o.py
+gateware=build/cmod7/gateware
+top=$gateware/cmod7
+proj=proj.tcl
+
+if [ "$1" == "-c" ]; then
+   cp $code .
+   echo "Updated code."
+elif [ "$1" == "-p" ]; then
+   $vivado -mode tcl -source pgmfpga.tcl
+   echo "Done."
+   exit
+elif [ "$1" == "-v" ]; then
+   cd $gateware
+   $vivado -mode tcl -source $proj
+   echo "Done."
+   cd $dir
+   exit
+elif [ "$1" != "" ]; then
+   echo "make [-c|-p] (-c=also copy code, -p=just program, -v=run vivado project"
+   exit
+fi
+
+# build and program
+python3 $soc --csr-csv csr.csv --no-compile-software --build
+if [ $? -ne 0 ]; then
+   exit
+fi
+
+echo "Copying .v and .bit, and programming..."
+cp ${top}.v .
+cp ${top}.bit .
+$vivado -mode tcl -source pgmfpga.tcl
+
+echo "Done."

dev/build/litex/makesim

@@ -0,0 +1,19 @@
+#!/usr/bin/bash
+
+# don't run vivado
+# uart=576000
+
+if [ "$1" == "-c" ]; then
+   # code
+   cp ~/projects/a2p/src/powaflight-full/rom.init .
+fi
+
+# build and program
+python3 a2p_full_litex.py  --csr-csv csr.csv --no-compile-software --uart-baudrate 576000
+if [ $? -ne 0 ]; then
+   exit
+fi
+
+cp build/cmod7/gateware/cmod7.v cmod7-sim.v
+
+echo "Done."

dev/build/litex/pgmflash.tcl

@@ -0,0 +1,44 @@
+# vivado -mode tcl -source pgmflash.tcl
+# can also use this to load ~2 MB of bootable code/data
+# can also load multiple bitstreams by changing address
+#
+# does this 'erase' the memory or make it unusable or ???
+# delete_hw_cfgmem [current_hw_cfgmem]
+
+open_hw_manager
+
+connect_hw_server
+current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
+open_hw_target
+
+set dev [lindex [get_hw_devices] 0]
+current_hw_device $dev
+refresh_hw_device -update_hw_probes false $dev
+
+# select n25q32-3.3v-spi-x1-x2-x4 flash (32Mb)
+# should check get_hw_cfgmems to see if exists, and use lindex 0 if there?
+# get_hw_cfgmems
+# cfgmem_0
+create_hw_cfgmem -hw_device $dev [lindex [get_cfgmem_parts {n25q32-3.3v-spi-x1_x2_x4}] 0]
+set_property PROGRAM.BLANK_CHECK  0 [ get_property PROGRAM.HW_CFGMEM $dev
+set_property PROGRAM.ERASE  1 [ get_property PROGRAM.HW_CFGMEM $dev
+set_property PROGRAM.CFG_PROGRAM  1 [ get_property PROGRAM.HW_CFGMEM $dev
+set_property PROGRAM.VERIFY  1 [ get_property PROGRAM.HW_CFGMEM $dev
+set_property PROGRAM.CHECKSUM  0 [ get_property PROGRAM.HW_CFGMEM $dev
+refresh_hw_device $dev
+
+# when not a compressed bitstream and -size 2:
+# ERROR: [Writecfgmem 68-4] Bitstream at address 0x00000000 has size 2192012 bytes which cannot fit in memory of size 2097152 bytes.
+# -rw-rw-r-- 1 wtf wtf 2192113 Nov  9 07:43 cmod7.bit
+#  need to get this to be set in soc:
+#  set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+write_cfgmem -format mcs -size 4 -interface SMAPx8 -loadbit {up 0x00000000 ./cmod7.bit} ./cmod7.mcs
+program_hw_cfgmem [current_hw_cfgmem]
+
+refresh_hw_device $dev
+
+puts "Device programmed."
+
+quit
+
+

dev/build/litex/pgmfpga.tcl

@@ -0,0 +1,20 @@
+# vivado -mode tcl -source pgmfpga.tcl
+
+open_hw_manager
+
+connect_hw_server
+current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
+open_hw_target
+
+set dev [lindex [get_hw_devices] 0]
+current_hw_device $dev
+refresh_hw_device -update_hw_probes false $dev
+set_property PROGRAM.FILE {./cmod7.bit} $dev
+#set_property PROBES.FILE {./cmod7.ltx} $dev
+
+program_hw_devices $dev
+refresh_hw_device $dev
+
+puts "Device programmed."
+
+quit

dev/build/litex/project_init.tcl

@@ -0,0 +1,2 @@
+# 
+source init.tcl

dev/build/litex/readme.md

@@ -48,4 +48,8 @@ WARNING: [Vivado 12-4383] DRC UTLZ-1 may not change severity
 
 * errors to check in source: a lot of critical warnings are vdd vs VCC and gnd vs GND; are these inouts and ties missing?
 
+## 7k410tffv676-1  clk1x=50MHz
 
+```
+|     c0                                  |                                          c |     241529 |     240987 |     540 |    2 | 95676 |     96 |     12 |          0 |
+```

dev/build/litex/wtf_util.tcl

@@ -0,0 +1,111 @@
+open_run impl_1
+
+catch {
+   report_utilization -cells [get_cells -hierarchical A2P_WB*] -file cells_utilization.txt
+}
+
+catch {
+   report_utilization -cells [get_cells -hierarchical *_zz*]   -append -file cells_utilization.txt
+}
+catch {
+   report_utilization -cells [get_cells -hierarchical dBusWB*] -append -file cells_utilization.txt
+}
+catch {
+   report_utilization -cells [get_cells -hierarchical iBusWB*] -append -file cells_utilization.txt
+}
+
+catch {
+   report_utilization -cells [get_cells -hierarchical execute_MemoryTranslatorPlugin*] -append -file cells_utilization.txt
+   report_utilization -cells [get_cells -hierarchical MemoryTranslatorPlugin*] -append -file cells_utilization.txt
+}
+
+report_utilization -cells [get_cells -hierarchical RegFilePlugin*] -append -file cells_utilization.txt
+catch {
+   report_utilization -cells [get_cells -hierarchical SPRPlugin*] -append -file cells_utilization.txt
+}
+
+# egrep "Command|Slice LUT|Muxes" cells_utilization.txt
+
+# stages
+report_utilization -cells [get_cells -hierarchical IBusCachedPlugin*] -append -file cells_utilization.txt
+catch {
+   report_utilization -cells [get_cells -hierarchical IBusCachedPlugin_fetchPc_*] -append -file cells_utilization.txt
+   report_utilization -cells [get_cells -hierarchical IBusCachedPlugin_predictor_*] -append -file cells_utilization.txt
+   report_utilization -cells [get_cells -hierarchical IBusCachedPlugin_injector_*] -append -file cells_utilization.txt
+}
+report_utilization -cells [get_cells -hierarchical decode_*] -append -file cells_utilization.txt
+report_utilization -cells [get_cells -hierarchical execute_*] -append -file cells_utilization.txt
+catch {
+   report_utilization -cells [get_cells -hierarchical execute_BranchPlugin*] -append -file cells_utilization.txt
+}
+#went away when i added areas below!
+#report_utilization -cells [get_cells -hierarchical execute_IntAluPlugin*] -append -file cells_utilization.txt
+#why are these gone with donttouch?
+#report_utilization -cells [get_cells -hierarchical execute_DBusCachedPlugin*] -append -file cells_utilization.txt
+report_utilization -cells [get_cells -hierarchical memory_*] -append -file cells_utilization.txt
+report_utilization -cells [get_cells -hierarchical writeBack_*] -append -file cells_utilization.txt
+
+
+# new stuff!  got areas named
+catch {
+   report_utilization -cells [get_cells -hierarchical Hazards*] -append -file cells_utilization.txt
+   report_utilization -cells [get_cells -hierarchical *DECODER*] -append -file cells_utilization.txt
+   report_utilization -cells [get_cells -hierarchical *SRC1*] -append -file cells_utilization.txt
+   #?report_utilization -cells [get_cells -hierarchical *SRC2*] -append -file cells_utilization.txt
+   #report_utilization -cells [get_cells -hierarchical *ALU1*] -append -file cells_utilization.txt
+   report_utilization -cells [get_cells -hierarchical *ALU2*] -append -file cells_utilization.txt
+   #?report_utilization -cells [get_cells -hierarchical *MUL1*] -append -file cells_utilization.txt
+   #?report_utilization -cells [get_cells -hierarchical *MUL2*] -append -file cells_utilization.txt
+   #?report_utilization -cells [get_cells -hierarchical *MUL3*] -append -file cells_utilization.txt
+   report_utilization -cells [get_cells -hierarchical *MULDIV*] -append -file cells_utilization.txt
+   report_utilization -cells [get_cells -hierarchical *MULDIV1*] -append -file cells_utilization.txt
+   #?report_utilization -cells [get_cells -hierarchical *MULDIV2*] -append -file cells_utilization.txt
+}
+
+### cells
+
+# LUT
+set outFile [open {cells_lut.txt} w]
+
+#set cells [get_cells -hier -filter {PARENT == A2P_WB}]
+set cells [get_cells -hier -filter {PARENT == a2p_i/A2P_WB/inst}]vrv_i/VexRiscv_0/inst
+set cells [get_cells -hier -filter {PARENT == vrv_i/VexRiscv_0/inst}]
+
+set names {}
+
+puts ""
+puts "Cells (non-flop)"
+foreach cell $cells {
+   set name [get_property NAME $cell]
+   if {[get_property PRIMITIVE_GROUP $cell] != "LUT"} {
+      if {[get_property PRIMITIVE_GROUP $cell] != "FLOP_LATCH"} {
+         # OTHERS CARRY MUXFX BMEM MULT [EMPTY=MACRO TOP]
+         puts "Not a LUT or FLOP_LATCH: [get_property PRIMITIVE_GROUP $cell] $name"
+      }
+   } else {
+      #puts $name
+      puts $outFile $name
+      lappend names $name
+   }
+}
+puts "Cells (nonflop): [llength $names]"
+close $outFile
+
+# flops
+set outFile [open {cells_ff.txt} w]
+
+#set cells [get_cells -hier -filter {(PRIMITIVE_TYPE =~ FLOP*) && (PARENT == A2P_WB)}]
+set cells [get_cells -hier -filter {(PRIMITIVE_TYPE =~ FLOP*) && (PARENT == a2p_i/A2P_WB/inst)}]
+set cells [get_cells -hier -filter {(PRIMITIVE_TYPE =~ FLOP*) && (PARENT == vrv_i/VexRiscv_0/inst)}]
+set names {}
+
+puts ""
+puts "Flops"
+foreach cell $cells {
+   set name [get_property NAME $cell]
+   #puts $name
+   puts $outFile $name
+   lappend names $name
+}
+puts "Flops: [llength $names]"
+close $outFile

dev/readme.md

@@ -1,6 +1,6 @@
 # Testing RTL with new environments
 
-##
+## Working
 
 * RTL
 
@@ -13,6 +13,7 @@
 
   * too big(?) to build with verilator --public with cocotb
   * executing boot code and tst with a2o_litex wrapper
+  * executing boot code and tst with litex-gen'd SOC
 
 * Icarus (w/cocotb)
 
@@ -33,7 +34,5 @@
 #### node
 
 * test BE/LE versions; kernel can stay BE until jump to BIOS; any problem with BIOS to initial ROM copy/zero or is it always words?
-* eventually node should handle reset vector fetch; or make the reset vector tied to inputs so always configurable?
-* add config pins
-* add L2 internally (before WB)
+* add L2 internally (before WB); or at least a store queue
 

dev/verilog/a2o_litex/a2l2wb.v

@@ -59,6 +59,7 @@ module a2l2wb #(
 //  101 write mask set
 //  110 write mask rst
 //  111 write mask xor
+// also, should it be edge-triggered (single pulse from nop->cmd)?
 
    input                            cfg_wr,
    output [0:31]                    status,

dev/verilog/a2o_litex/a2owb.v

@@ -63,26 +63,26 @@ module a2owb (
     input                            clk,
     input                            rst,
 
-    input  [0:31]                    cfg_dat,
-    input                            cfg_wr,
-    output [0:31]                    status,
-
-    input                            timerInterrupt,
-    input                            externalInterrupt,
-    input                            softwareInterrupt,
-    input                            externalInterruptS,
-
-    output                           wb_stb,
-    output                           wb_cyc,
-    output [31:0]                    wb_adr,
-    output                           wb_we,
-    output [3:0]                     wb_sel,
-    output [31:0]                    wb_datw,
-    input                            wb_ack,
-    input  [31:0]                    wb_datr
+    input  [0:31]                    cfg_dat/*verilator public */,
+    input                            cfg_wr/*verilator public */,
+    output [0:31]                    status/*verilator public */,
+
+    input                            timerInterrupt/*verilator public */,
+    input                            externalInterrupt/*verilator public */,
+    input                            softwareInterrupt/*verilator public */,
+    input                            externalInterruptS/*verilator public */,
+
+    output                           wb_stb/*verilator public */,
+    output                           wb_cyc/*verilator public */,
+    output [31:0]                    wb_adr/*verilator public */,
+    output                           wb_we/*verilator public */,
+    output [3:0]                     wb_sel/*verilator public */,
+    output [31:0]                    wb_datw/*verilator public */,
+    input                            wb_ack/*verilator public */,
+    input  [31:0]                    wb_datr/*verilator public */
 );
 
-wire   [0:`THREADS-1]            an_ac_stcx_complete /*verilator public */;
+wire   [0:`THREADS-1]            an_ac_stcx_complete;
 wire   [0:`THREADS-1]            an_ac_stcx_pass;
 wire                             an_ac_icbi_ack;
 wire   [0:1]                     an_ac_icbi_ack_thread;

dev/verilog/notes.md

@@ -19,3 +19,67 @@
 ### special rings
 
 * tri_slat_scan's seem to be the comps used for core config and boot config
+
+### reg bits
+
+* erat-only
+
+   * These two modes are termed “MMU mode” and “ERAT-only mode”. This mode controlled by the CCR2[NOTLB] bit.
+
+   * mmu may be configurable to table-walk but not have a TLB(?) This would allow the erats and htw to be changed for radix before implementing
+     the TLB logic.
+
+
+### translation
+
+* ERAT holes (UM 6.2.3)
+
+The rules for configuring an exclusion range “hole” for a given TLB entry and placing one or more pages
+within the “hole” are as follows:
+
+1. Only TLB entries with page sizes greater than 4 KB can have an exclusion range hole enabled via X = 1.
+2. A virtual address to be translated that falls within the hole will not match this TLB entry.
+3. The size of the hole configured must be smaller than the page size of this TLB entry.
+4. The size of the hole is configurable to 2 n  4 KB, where n = 0 to log 2 (entry size in bytes) - 13.
+5. The legal binary values of the unused EPN bits of a given TLB entry are contained in the set defined by
+2 n - 1, where n = 0 to log 2 (entry size in bytes) - 13.
+6. Other TLB entries of valid page sizes (less than or equal to the hole size) can be mapped into the hole.
+7. Multiple other TLB entries can be mapped into the hole simultaneously.
+8. Not all of the address space defined by the hole needs to be mapped by other entries.
+9. Pages mapped in the hole must be page-size aligned.
+10. Pages mapped in the hole must not overlap.
+11. Pages mapped in the hole must be collectively fully contained within the hole.
+
+* Page sizes
+
+* UM 6.17.3 says
+
+> Supported values of the PS field for this implementation include:
+0b0010 (4 KB for sub-page size of 4 KB only), 0b0110 (64 KB), 0b1010 (1 MB), and
+0b1110 (16 MB).
+
+   Is this correct?  No 1G size? The logic (iuq_ic_ierat) says:
+
+```
+   parameter [0:2]                   CAM_PgSize_1GB  = 3'b110;
+   parameter [0:2]                   CAM_PgSize_16MB = 3'b111;
+   parameter [0:2]                   CAM_PgSize_1MB  = 3'b101;
+   parameter [0:2]                   CAM_PgSize_64KB = 3'b011;
+   parameter [0:2]                   CAM_PgSize_4KB  = 3'b001;
+```
+
+* UM also says:
+
+>Variable page sizes for direct (IND=0) entries (4KB, 64KB, 1MB, 16MB, 1GB), simultaneously resi-
+dent in TLB and/or ERAT, and indirect (IND=1) entries (1 MB and 256 MB) in TLB
+
+>The MMU divides the address space into pages. Five direct (IND=0) page sizes (4KB, 64KB, 1MB, 16MB,
+1GB) are simultaneously supported,
+
+### implementing radix
+
+Possible:
+
+1. toss all of MMU and rewrite using MMU interface; update ERAT entries as necessary
+2. keep everything and change HTW/TLB for radix (plus ERATs)
+3. do in steps; get ERATS+HTW working and then add TLB logic

dev/verilog/unisims_soc/BUFG.v

@@ -0,0 +1,4 @@
+module BUFG (output O, input I);
+   assign O = I;
+endmodule
+

dev/verilog/unisims_soc/DNA_PORT.v

@@ -0,0 +1,10 @@
+module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT);
+
+    parameter [56:0] SIM_DNA_VALUE = 57'h0;
+
+    output DOUT;
+    input  CLK, DIN, READ, SHIFT;
+
+    assign DOUT = 1'b0;
+
+endmodule

dev/verilog/unisims_soc/FD.v

@@ -0,0 +1,21 @@
+
+`timescale  1 ps / 1 ps
+
+module FD (Q, C, D);
+
+    parameter INIT = 1'b0;
+
+    output Q;
+    input  C, D;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    always @(posedge C)
+       q_out <=  D;
+
+    assign Q = q_out;
+
+endmodule

dev/verilog/unisims_soc/FDCE.v

@@ -0,0 +1,24 @@
+`timescale  1 ps / 1 ps
+
+module FDCE (C, CE, CLR, D, Q);
+
+    parameter INIT = 1'b1;
+
+    output Q;
+
+    input  C, CE, D, CLR;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    assign Q = q_out;
+
+    always @(posedge C or posedge CLR)
+        if (CLR)
+             q_out <= 0;
+        else if (CE)
+	         q_out <= D;
+
+endmodule

dev/verilog/unisims_soc/FDPE.v

@@ -0,0 +1,24 @@
+`timescale  1 ps / 1 ps
+
+module FDPE (Q, C, CE, D, PRE);
+
+    parameter INIT = 1'b1;
+
+    output Q;
+
+    input  C, CE, D, PRE;
+
+    wire Q;
+    reg q_out;
+
+    initial q_out = INIT;
+
+    assign Q = q_out;
+
+    always @(posedge C or posedge PRE)
+        if (PRE)
+             q_out <= 1;
+        else if (CE)
+	         q_out <= D;
+
+endmodule

dev/verilog/unisims_soc/IDELAYCTRL.v

@@ -0,0 +1,10 @@
+module IDELAYCTRL #(
+)(
+  output RDY,
+  input REFCLK,
+  input RST
+);
+
+assign RDY = !RST;
+endmodule
+

dev/verilog/unisims_soc/IDELAYE2.v

@@ -0,0 +1,24 @@
+// wtf didn't check what it actually does!
+
+module IDELAYE2 #(
+	parameter CINVCTRL_SEL,
+	parameter DELAY_SRC,
+	parameter HIGH_PERFORMANCE_MODE,
+	parameter IDELAY_TYPE,
+	parameter IDELAY_VALUE,
+	parameter PIPE_SEL,
+	parameter REFCLK_FREQUENCY,
+	parameter SIGNAL_PATTERN
+)(
+  input C,
+  input CE,
+  input IDATAIN,
+  input INC,
+  input LD,
+  input LDPIPEEN,
+  output DATAOUT
+);
+
+assign DATAOUT = IDATAIN;
+endmodule
+

dev/verilog/unisims_soc/IOBUF.v

@@ -0,0 +1,13 @@
+//wtf nop
+
+module IOBUF #(
+)
+(
+   input I,
+   input T,
+   inout IO,
+   inout O
+);
+
+endmodule
+

dev/verilog/unisims_soc/IOBUFDS.v

@@ -0,0 +1,13 @@
+//wtf nop
+
+module IOBUFDS #(
+)
+(
+   input I,
+   input T,
+   inout IO,
+   inout IOB
+);
+
+endmodule
+

dev/verilog/unisims_soc/ISERDESE2.v

@@ -0,0 +1,31 @@
+//wtf doesnt do nothin!
+
+module ISERDESE2 #(
+   parameter DATA_RATE,
+   parameter DATA_WIDTH,
+   parameter INTERFACE_TYPE,
+   parameter IOBDELAY,
+   parameter NUM_CE,
+   parameter SERDES_MODE
+)
+(
+   input BITSLIP,
+   input CE1,
+   input CLK,
+   input CLKB,
+   input CLKDIV,
+   input DDLY,
+   input RST,
+   output Q1,
+   output Q2,
+   output Q3,
+   output Q4,
+   output Q5,
+   output Q6,
+   output Q7,
+   output Q8
+);
+
+
+endmodule
+

dev/verilog/unisims_soc/MMCME2_ADV.v

@@ -0,0 +1,95 @@
+`timescale 1 ps / 1 ps
+
+module MMCME2_ADV #(
+  parameter BANDWIDTH = "OPTIMIZED",
+  parameter real CLKFBOUT_MULT_F = 5.000,
+  parameter real CLKFBOUT_PHASE = 0.000,
+  parameter CLKFBOUT_USE_FINE_PS = "FALSE",
+  parameter real CLKIN1_PERIOD = 0.000,
+  parameter real CLKIN2_PERIOD = 0.000,
+  parameter real CLKOUT0_DIVIDE_F = 1.000,
+  parameter real CLKOUT0_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT0_PHASE = 0.000,
+  parameter CLKOUT0_USE_FINE_PS = "FALSE",
+  parameter integer CLKOUT1_DIVIDE = 1,
+  parameter real CLKOUT1_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT1_PHASE = 0.000,
+  parameter CLKOUT1_USE_FINE_PS = "FALSE",
+  parameter integer CLKOUT2_DIVIDE = 1,
+  parameter real CLKOUT2_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT2_PHASE = 0.000,
+  parameter CLKOUT2_USE_FINE_PS = "FALSE",
+  parameter integer CLKOUT3_DIVIDE = 1,
+  parameter real CLKOUT3_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT3_PHASE = 0.000,
+  parameter CLKOUT3_USE_FINE_PS = "FALSE",
+  parameter CLKOUT4_CASCADE = "FALSE",
+  parameter integer CLKOUT4_DIVIDE = 1,
+  parameter real CLKOUT4_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT4_PHASE = 0.000,
+  parameter CLKOUT4_USE_FINE_PS = "FALSE",
+  parameter integer CLKOUT5_DIVIDE = 1,
+  parameter real CLKOUT5_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT5_PHASE = 0.000,
+  parameter CLKOUT5_USE_FINE_PS = "FALSE",
+  parameter integer CLKOUT6_DIVIDE = 1,
+  parameter real CLKOUT6_DUTY_CYCLE = 0.500,
+  parameter real CLKOUT6_PHASE = 0.000,
+  parameter CLKOUT6_USE_FINE_PS = "FALSE",
+  parameter COMPENSATION = "ZHOLD",
+  parameter integer DIVCLK_DIVIDE = 1,
+  parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
+  parameter [0:0] IS_PSEN_INVERTED = 1'b0,
+  parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0,
+  parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
+  parameter [0:0] IS_RST_INVERTED = 1'b0,
+  parameter real REF_JITTER1 = 0.010,
+  parameter real REF_JITTER2 = 0.010,
+  parameter SS_EN = "FALSE",
+  parameter SS_MODE = "CENTER_HIGH",
+  parameter integer SS_MOD_PERIOD = 10000,
+  parameter STARTUP_WAIT = "FALSE"
+)(
+  output CLKFBOUT,
+  output CLKFBOUTB,
+  output CLKFBSTOPPED,
+  output CLKINSTOPPED,
+  output CLKOUT0,
+  output CLKOUT0B,
+  output CLKOUT1,
+  output CLKOUT1B,
+  output CLKOUT2,
+  output CLKOUT2B,
+  output CLKOUT3,
+  output CLKOUT3B,
+  output CLKOUT4,
+  output CLKOUT5,
+  output CLKOUT6,
+  output [15:0] DO,
+  output DRDY,
+  output LOCKED,
+  output PSDONE,
+
+  input CLKFBIN,
+  input CLKIN1,
+  input CLKIN2,
+  input CLKINSEL,
+  input [6:0] DADDR,
+  input DCLK,
+  input DEN,
+  input [15:0] DI,
+  input DWE,
+  input PSCLK,
+  input PSEN,
+  input PSINCDEC,
+  input PWRDWN,
+  input RST
+);
+
+  assign CLKFBOUT = 1'b0;  //feedback
+  assign CLKOUT0 =  CLKIN1;
+  assign CLKOUT1 =  CLKIN1;
+  assign CLKOUT2 =  CLKIN1;
+  assign LOCKED = 1'b1;
+
+endmodule

dev/verilog/unisims_soc/OBUFDS.v

@@ -0,0 +1,12 @@
+//wtf nop
+
+module OBUFDS #(
+)
+(
+   input I,
+   inout O,
+   inout OB
+);
+
+endmodule
+

dev/verilog/unisims_soc/OSERDESE2.v

@@ -0,0 +1,33 @@
+//wtf doesnt do nothin!
+
+module OSERDESE2 #(
+   parameter DATA_RATE_OQ,
+   parameter DATA_RATE_TQ,
+   parameter DATA_WIDTH,
+   parameter SERDES_MODE,
+   parameter TRISTATE_WIDTH
+)
+(
+   input CLK,
+   input CLKDIV,
+   input DDLY,
+   input RST,
+   input D1,
+   input D2,
+   input D3,
+   input D4,
+   input D5,
+   input D6,
+   input D7,
+   input D8,
+   input OCE,
+   input OFB,
+   input T1,
+   input TCE,
+   output OQ,
+   output TQ
+);
+
+
+endmodule
+

dev/verilog/unisims_soc/XADC.v

@@ -0,0 +1,93 @@
+`timescale 1ps / 1ps
+
+module XADC (
+        ALM,
+        BUSY,
+        CHANNEL,
+        DO,
+        DRDY,
+        EOC,
+        EOS,
+        JTAGBUSY,
+        JTAGLOCKED,
+        JTAGMODIFIED,
+        MUXADDR,
+        OT,
+        CONVST,
+        CONVSTCLK,
+        DADDR,
+        DCLK,
+        DEN,
+        DI,
+        DWE,
+        RESET,
+        VAUXN,
+        VAUXP,
+        VN,
+        VP
+
+);
+
+  output BUSY;
+  output DRDY;
+  output EOC;
+  output EOS;
+  output JTAGBUSY;
+  output JTAGLOCKED;
+  output JTAGMODIFIED;
+  output OT;
+  output [15:0] DO;
+  output [7:0] ALM;
+  output [4:0] CHANNEL;
+  output [4:0] MUXADDR;
+
+  input CONVST;
+  input CONVSTCLK;
+  input DCLK;
+  input DEN;
+  input DWE;
+  input RESET;
+  input VN;
+  input VP;
+  input [15:0] DI;
+  input [15:0] VAUXN;
+  input [15:0] VAUXP;
+  input [6:0] DADDR;
+
+  parameter  [15:0] INIT_40 = 16'h0;
+  parameter  [15:0] INIT_41 = 16'h0;
+  parameter  [15:0] INIT_42 = 16'h0800;
+  parameter  [15:0] INIT_43 = 16'h0;
+  parameter  [15:0] INIT_44 = 16'h0;
+  parameter  [15:0] INIT_45 = 16'h0;
+  parameter  [15:0] INIT_46 = 16'h0;
+  parameter  [15:0] INIT_47 = 16'h0;
+  parameter  [15:0] INIT_48 = 16'h0;
+  parameter  [15:0] INIT_49 = 16'h0;
+  parameter  [15:0] INIT_4A = 16'h0;
+  parameter  [15:0] INIT_4B = 16'h0;
+  parameter  [15:0] INIT_4C = 16'h0;
+  parameter  [15:0] INIT_4D = 16'h0;
+  parameter  [15:0] INIT_4E = 16'h0;
+  parameter  [15:0] INIT_4F = 16'h0;
+  parameter  [15:0] INIT_50 = 16'h0;
+  parameter  [15:0] INIT_51 = 16'h0;
+  parameter  [15:0] INIT_52 = 16'h0;
+  parameter  [15:0] INIT_53 = 16'h0;
+  parameter  [15:0] INIT_54 = 16'h0;
+  parameter  [15:0] INIT_55 = 16'h0;
+  parameter  [15:0] INIT_56 = 16'h0;
+  parameter  [15:0] INIT_57 = 16'h0;
+  parameter  [15:0] INIT_58 = 16'h0;
+  parameter  [15:0] INIT_59 = 16'h0;
+  parameter  [15:0] INIT_5A = 16'h0;
+  parameter  [15:0] INIT_5B = 16'h0;
+  parameter  [15:0] INIT_5C = 16'h0;
+  parameter  [15:0] INIT_5D = 16'h0;
+  parameter  [15:0] INIT_5E = 16'h0;
+  parameter  [15:0] INIT_5F = 16'h0;
+
+   assign BUSY = 1'b0;
+   assign DRDY = 1'b1;
+
+endmodule