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verilator optimization experiments

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pull/18/head
openpowerwtf 2 years ago
parent cb04a607db
commit 81f5d8dca2
53 changed files with 27300 additions and 0 deletions
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54
dev/sim/verilator/readme.md
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@ -45,6 +45,60 @@ obj_dir_$mod/V$mod | tee sim_soc.txt
vcd2fst a2olitex.vcd soc.fst vcd2fst a2olitex.vcd soc.fst
rm a2olitex.vcd rm a2olitex.vcd
gtkwave soc.fst soc.gtkw gtkwave soc.fst soc.gtkw

time obj_dir_$mod/V$mod > sim_soc_notrace.txt

real 1m3.318s
user 0m58.941s
sys 0m3.368s
```

* notrace - faster execution?

```
dir=obj_dir_${mod}_notrace
verilator -cc --exe -CFLAGS -DNO_TRACE=1 --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -I$. -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims -Iverilog/unisims_soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt
make -j6 -C $dir -f V$mod.mk V$mod

time $dir/V$mod > sim_soc_notrace.txt

real 0m19.814s
user 0m19.577s
sys 0m0.188s
```

that is ~1.25KHz clk (25K cycs/20s).

* -O3 + notrace

```
dir=obj_dir_${mod}_notrace_o3
verilator -cc --exe -O3 -CFLAGS -DNO_TRACE=1 --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -I$. -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims -Iverilog/unisims_soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt
make -j6 -C $dir -f V$mod.mk V$mod
$dir/V$mod | tee sim_soc_o3.txt

time $dir/V$mod > sim_soc_notrace_o3.txt

real 0m23.279s
user 0m22.916s
sys 0m0.260s

```

* -O3 -O3 + notrace

```
dir=obj_dir_${mod}_notrace_o3_o3
verilator -cc --exe -O3 -CFLAGS -O3 -CFLAGS -DNO_TRACE=1 --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -I$. -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims -Iverilog/unisims_soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt
make -j6 -C $dir -f V$mod.mk V$mod
$dir/V$mod | tee sim_soc_o3_o3.txt

time $dir/V$mod > sim_soc_notrace_o3_o3.txt

real 0m23.244s
user 0m22.963s
sys 0m0.192s

``` ```


##### first try ##### first try

2
dev/sim/verilator/tb_litex_soc.cpp
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@ -1,7 +1,9 @@
// simple verilator top // simple verilator top
// litex soc w/a2o // litex soc w/a2o


#ifndef NO_TRACE
#define TRACING #define TRACING
#endif


// old public access method // old public access method
//#define OLD_PUBLIC //#define OLD_PUBLIC

297
dev/src/test3_smt/arcitst.h
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@ -0,0 +1,297 @@
# asmtst.tpl
# powerpc-linux-gnu-as -c arcitst.s

.include "defines.s"

# -------------------------------------------------------------------------------------------------
# c-accessible

.global init_tst
.global tst_start
.global tst_end
.global tst_inits
.global tst_results
.global tst_expects

# -------------------------------------------------------------------------------------------------
tst_misc:

tst_info: .asciz "info text"
tst_header: .asciz "header text"

.set SAVESPR,sprg3
.set MAGIC,0x8675309

# -------------------------------------------------------------------------------------------------
.align 5
tst_inits:

init_r0: .int 0x5EA9536C
init_r1: .int 0x07EC9BA7
init_r2: .int 0xFFFFFFFF
init_r3: .int 0x18FAD811
init_r4: .int 0xFFFFFFFF
init_r5: .int 0xFFFFFFFF
init_r6: .int 0xFFFFFFFF
init_r7: .int 0xFFFFFFFF
init_r8: .int 0xFFFFFFFF
init_r9: .int 0xFFFFFFFF
init_r10: .int 0xB186394A
init_r11: .int 0x07EC9BA7
init_r12: .int 0xFFFFFFFF
init_r13: .int 0xFC9D07CE
init_r14: .int 0x7305868F
init_r15: .int 0xFFFFFFFF
init_r16: .int 0xFFFFFFFF
init_r17: .int 0x6E078D56
init_r18: .int 0xFFFFFFFF
init_r19: .int 0xFFFFFFFF
init_r20: .int 0x0F8F2BB1
init_r21: .int 0xFFFFFFFF
init_r22: .int 0xFFFFFFFF
init_r23: .int 0x9E47F6C0
init_r24: .int 0x46B0FC81
init_r25: .int 0xFFFFFFFF
init_r26: .int 0xFFFFFFFF
init_r27: .int 0x48026438
init_r28: .int 0xEFB046E4
init_r29: .int 0x4B5CBE25
init_r30: .int 0xFFFFFFFF
init_r31: .int 0xFFFFFFFF

init_cr: .int 0xB0215BC8
init_xer: .int 0xBFC0004B
init_ctr: .int 0xF7DA2C8A
init_lr: .int 0x8BC7C22B
init_tar: .int 0xFFFFFFFF
init_msr: .int 0x00001081

init_iar: .int 0x00010000

save_r1: .int 0

codelen: .int 13
ops: .int 0x36E86A7F,0x10748A7F,0x71AE9D7E,0x1C865B55,0xF45EAA7D,0x2000154D,0x50E01B7C,0x4933037B,0x00082B7D,0x36B8317C,0x00000060,0x00000060,0x00000060
iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x0001001C,0x00010020,0x00010024,0x00010028,0x0001002C,0x00010030

# -------------------------------------------------------------------------------------------------
# r3=@tst_inits
.align 5
init_tst:

# save c stuff
stw r1,(save_r1-tst_inits)(r3)

# copy ops
opcopy:
lwz r1,(codelen-tst_inits)(r3)
mtctr r1
opcopy_loop:
la r1,(cops-tst_inits)(r3)
la r2,(iars-tst_inits)(r3)
stw r1,0(r2)
addi r2,r2,4
bdnz opcopy_loop

# init test regs
init_regs:
lwz r1,(init_cr-tst_inits)(r3)
mtcr r1
lwz r1,(init_xer-tst_inits)(r3)
mtxer r1
lwz r1,(init_ctr-tst_inits)(r3)
mtctr r1
lwz r1,(init_lr-tst_inits)(r3)
mtlr r1
lwz r1,(init_tar-tst_inits)(r3)
mtspr tar,r1

lwz r0,(init_r0-tst_inits)(r3)
lwz r1,(init_r1-tst_inits)(r3)
lwz r2,(init_r2-tst_inits)(r3)
lwz r4,(init_r4-tst_inits)(r3)
lwz r5,(init_r5-tst_inits)(r3)
lwz r6,(init_r6-tst_inits)(r3)
lwz r7,(init_r7-tst_inits)(r3)
lwz r8,(init_r8-tst_inits)(r3)
lwz r9,(init_r9-tst_inits)(r3)
lwz r10,(init_r10-tst_inits)(r3)
lwz r11,(init_r11-tst_inits)(r3)
lwz r12,(init_r12-tst_inits)(r3)
lwz r13,(init_r13-tst_inits)(r3)
lwz r14,(init_r14-tst_inits)(r3)
lwz r15,(init_r15-tst_inits)(r3)
lwz r16,(init_r16-tst_inits)(r3)
lwz r17,(init_r17-tst_inits)(r3)
lwz r18,(init_r18-tst_inits)(r3)
lwz r19,(init_r19-tst_inits)(r3)
lwz r20,(init_r20-tst_inits)(r3)
lwz r21,(init_r21-tst_inits)(r3)
lwz r22,(init_r22-tst_inits)(r3)
lwz r23,(init_r23-tst_inits)(r3)
lwz r24,(init_r24-tst_inits)(r3)
lwz r25,(init_r25-tst_inits)(r3)
lwz r26,(init_r26-tst_inits)(r3)
lwz r27,(init_r27-tst_inits)(r3)
lwz r28,(init_r28-tst_inits)(r3)
lwz r29,(init_r29-tst_inits)(r3)
lwz r30,(init_r30-tst_inits)(r3)
lwz r31,(init_r31-tst_inits)(r3)
lwz r3,(init_r3-tst_inits)(r3)

jmp2tst: rfi

# needs to be inserted into epilogue of tst!
#tst_end:
# b save_results

# -------------------------------------------------------------------------------------------------
.align 5
save_results:
# use a designated spr to save (sprgx, ...)
mtspr SAVESPR,r1
lis r1,tst_results@h
ori r1,r1,tst_results@l
stw r0,(rslt_r0-tst_results)(r1)
stw r2,(rslt_r2-tst_results)(r1)
stw r3,(rslt_r3-tst_results)(r1)
stw r4,(rslt_r4-tst_results)(r1)
stw r5,(rslt_r5-tst_results)(r1)
stw r6,(rslt_r6-tst_results)(r1)
stw r7,(rslt_r7-tst_results)(r1)
stw r8,(rslt_r8-tst_results)(r1)
stw r9,(rslt_r9-tst_results)(r1)
stw r10,(rslt_r10-tst_results)(r1)
stw r11,(rslt_r11-tst_results)(r1)
stw r12,(rslt_r12-tst_results)(r1)
stw r13,(rslt_r13-tst_results)(r1)
stw r14,(rslt_r14-tst_results)(r1)
stw r15,(rslt_r15-tst_results)(r1)
stw r16,(rslt_r16-tst_results)(r1)
stw r17,(rslt_r17-tst_results)(r1)
stw r18,(rslt_r18-tst_results)(r1)
stw r19,(rslt_r19-tst_results)(r1)
stw r20,(rslt_r20-tst_results)(r1)
stw r21,(rslt_r21-tst_results)(r1)
stw r22,(rslt_r22-tst_results)(r1)
stw r23,(rslt_r23-tst_results)(r1)
stw r24,(rslt_r24-tst_results)(r1)
stw r25,(rslt_r25-tst_results)(r1)
stw r26,(rslt_r26-tst_results)(r1)
stw r27,(rslt_r27-tst_results)(r1)
stw r28,(rslt_r28-tst_results)(r1)
stw r29,(rslt_r29-tst_results)(r1)
stw r30,(rslt_r30-tst_results)(r1)
stw r31,(rslt_r31-tst_results)(r1)
mfspr r2,SAVESPR
stw r2,(rslt_r1-tst_results)(r1)
mfcr r2
stw r2,(rslt_cr-tst_results)(r1)
mfxer r2
stw r2,(rslt_xer-tst_results)(r1)
mfctr r2
stw r2,(rslt_ctr-tst_results)(r1)
mflr r2
stw r2,(rslt_lr-tst_results)(r1)
mfspr r2,tar
stw r2,(rslt_tar-tst_results)(r1)

tst_cleanup:
# restore c stuff
lis r3,tst_inits@h
ori r3,r3,tst_inits@l
lwz r1,(save_r1-tst_inits)(r3)
lis r3,MAGIC@h
ori r3,r3,MAGIC@l

b tst_done

# -------------------------------------------------------------------------------------------------
.align 5
tst_results:

rslt_r0: .int 0xFFFFFFFF
rslt_r1: .int 0xFFFFFFFF
rslt_r2: .int 0xFFFFFFFF
rslt_r3: .int 0xFFFFFFFF
rslt_r4: .int 0xFFFFFFFF
rslt_r5: .int 0xFFFFFFFF
rslt_r6: .int 0xFFFFFFFF
rslt_r7: .int 0xFFFFFFFF
rslt_r8: .int 0xFFFFFFFF
rslt_r9: .int 0xFFFFFFFF
rslt_r10: .int 0xFFFFFFFF
rslt_r11: .int 0xFFFFFFFF
rslt_r12: .int 0xFFFFFFFF
rslt_r13: .int 0xFFFFFFFF
rslt_r14: .int 0xFFFFFFFF
rslt_r15: .int 0xFFFFFFFF
rslt_r16: .int 0xFFFFFFFF
rslt_r17: .int 0xFFFFFFFF
rslt_r18: .int 0xFFFFFFFF
rslt_r19: .int 0xFFFFFFFF
rslt_r20: .int 0xFFFFFFFF
rslt_r21: .int 0xFFFFFFFF
rslt_r22: .int 0xFFFFFFFF
rslt_r23: .int 0xFFFFFFFF
rslt_r24: .int 0xFFFFFFFF
rslt_r25: .int 0xFFFFFFFF
rslt_r26: .int 0xFFFFFFFF
rslt_r27: .int 0xFFFFFFFF
rslt_r28: .int 0xFFFFFFFF
rslt_r29: .int 0xFFFFFFFF
rslt_r30: .int 0xFFFFFFFF
rslt_r31: .int 0xFFFFFFFF

rslt_cr: .int 0xFFFFFFFF
rslt_xer: .int 0xFFFFFFFF
rslt_ctr: .int 0xFFFFFFFF
rslt_lr: .int 0xFFFFFFFF
rslt_tar: .int 0xFFFFFFFF

# -------------------------------------------------------------------------------------------------
.align 5
tst_expects:

expt_r0: .int 0x7305868F
expt_r1: .int 0x07EC9BA7
expt_r2: .int 0xFFFFFFFF
expt_r3: .int 0xAC3F2040
expt_r4: .int 0xFFFFFFFF
expt_r5: .int 0xFFFFFFFF
expt_r6: .int 0xFFFFFFFF
expt_r7: .int 0xFFFFFFFF
expt_r8: .int 0xFFFFFFFF
expt_r9: .int 0xFFFFFFFF
expt_r10: .int 0xE83E7000
expt_r11: .int 0x07EC9BA7
expt_r12: .int 0xFFFFFFFF
expt_r13: .int 0xFC9D07CE
expt_r14: .int 0x7305868F
expt_r15: .int 0xFFFFFFFF
expt_r16: .int 0xFFFFFFFF
expt_r17: .int 0x00000000
expt_r18: .int 0xFFFFFFFF
expt_r19: .int 0xFFFFFFFF
expt_r20: .int 0x0F8F2BB1
expt_r21: .int 0xFFFFFFFF
expt_r22: .int 0xFFFFFFFF
expt_r23: .int 0x9E47F6C0
expt_r24: .int 0x46B0FC81
expt_r25: .int 0xFFFFFFFF
expt_r26: .int 0xFFFFFFFF
expt_r27: .int 0x00000000
expt_r28: .int 0x7305868F
expt_r29: .int 0x0000007C
expt_r30: .int 0xFFFFFFFF
expt_r31: .int 0xFFFFFFFF

expt_cr: .int 0x90315BC8
expt_xer: .int 0x82C0004B
expt_ctr: .int 0xF7DA2C89
expt_lr: .int 0x8BC7C22B
expt_tar: .int 0xFFFFFFFF
expt_msr: .int 0x00001081

expt_iar: .int 0x00010038

492
dev/src/test3_smt/arcitst.lst
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@ -0,0 +1,492 @@
1 # asmtst.tpl
2
3 .include "defines.s"
1 # © IBM Corp. 2020
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 #-----------------------------------------
11 # Defines
12 #-----------------------------------------
13
14 # Regs
15
16 .set r0, 0
17 .set r1, 1
18 .set r2, 2
19 .set r3, 3
20 .set r4, 4
21 .set r5, 5
22 .set r6, 6
23 .set r7, 7
24 .set r8, 8
25 .set r9, 9
26 .set r10,10
27 .set r11,11
28 .set r12,12
29 .set r13,13
30 .set r14,14
31 .set r15,15
32 .set r16,16
33 .set r17,17
34 .set r18,18
35 .set r19,19
36 .set r20,20
37 .set r21,21
38 .set r22,22
39 .set r23,23
40 .set r24,24
41 .set r25,25
42 .set r26,26
43 .set r27,27
44 .set r28,28
45 .set r29,29
46 .set r30,30
47 .set r31,31
48
49 .set f0, 0
50 .set f1, 1
51 .set f2, 2
52 .set f3, 3
53 .set f4, 4
54 .set f5, 5
55 .set f6, 6
56 .set f7, 7
57 .set f8, 8
58 .set f9, 9
59 .set f10,10
60 .set f11,11
61 .set f12,12
62 .set f13,13
63 .set f14,14
64 .set f15,15
65 .set f16,16
66 .set f17,17
67 .set f18,18
68 .set f19,19
69 .set f20,20
70 .set f21,21
71 .set f22,22
72 .set f23,23
73 .set f24,24
74 .set f25,25
75 .set f26,26
76 .set f27,27
77 .set f28,28
78 .set f29,29
79 .set f30,30
80 .set f31,31
81
82 .set cr0, 0
83 .set cr1, 1
84 .set cr2, 2
85 .set cr3, 3
86 .set cr4, 4
87 .set cr5, 5
88 .set cr6, 6
89 .set cr7, 7
90
91 # SPR numbers
92
93 .set srr0, 26
94 .set srr1, 27
95 .set dar, 19
96 .set dsisr, 18
97 .set epcr, 307
98 .set tar, 815
99
100 .set dbsr, 304
101 .set dbcr0, 308
102 .set dbcr1, 309
103 .set dbcr2, 310
104 .set dbcr3, 848
105
106 .set ivpr, 63
107
108 .set iucr0, 1011
109 .set iucr1, 883
110 .set iucr2, 884
111
112 .set iudbg0, 888
113 .set iudbg1, 889
114 .set iudbg2, 890
115 .set iulfsr, 891
116 .set iullcr, 892
117
118 .set mmucr0, 1020
119 .set mmucr1, 1021
120 .set mmucr2, 1022
121 .set mmucr3, 1023
122
123 .set tb, 268
124 .set tbl, 284
125 .set tbh, 285
126
127 .set dec, 22
128 .set udec, 550
129 .set tsr, 336
130 .set tcr, 340
131
132 .set xucr0, 1014
133 .set xucr1, 851
134 .set xucr2, 1016
135 .set xucr3, 852
136 .set xucr4, 853
137
138 .set tens, 438
139 .set tenc, 439
140 .set tensr, 437
141
142 .set pid, 48
143 .set pir, 286
144 .set pvr, 287
145 .set tir, 446
146
147 #.set sprg0,
148 #.set sprg1,
149 #.set sprg2,
150 .set sprg3, 259
4
5 # -------------------------------------------------------------------------------------------------
6 # c-accessible
7
8 .global init_tst
9 .global tst_start
10 .global tst_end
11 .global tst_inits
12 .global tst_results
13 .global tst_expects
14
15 # -------------------------------------------------------------------------------------------------
16 tst_misc:
17
18 0000 696E666F tst_info: .asciz "info text"
18 20746578
18 7400
19 000a 68656164 tst_header: .asciz "header text"
19 65722074
19 65787400
20
21 .set SAVESPR,tar
22 .set MAGIC,0x8675309
23
24 # -------------------------------------------------------------------------------------------------
25 0016 00000000 .align 5
25 00000000
25 0000
26 tst_inits:
27
28 0020 00000000 init_r0: .int 0x00000000
29 0024 5822C905 init_r1: .int 0x5822C905
30 0028 FFFFFFFF init_r2: .int 0xFFFFFFFF
31 002c 91B6D1A3 init_r3: .int 0x91B6D1A3
32 0030 FFFFFFFF init_r4: .int 0xFFFFFFFF
33 0034 FFFFFFFF init_r5: .int 0xFFFFFFFF
34 0038 FFFFFFFF init_r6: .int 0xFFFFFFFF
35 003c FFFFFFFF init_r7: .int 0xFFFFFFFF
36 0040 FFFFFFFF init_r8: .int 0xFFFFFFFF
37 0044 7E11EE88 init_r9: .int 0x7E11EE88
38 0048 FFFFFFFF init_r10: .int 0xFFFFFFFF
39 004c 7FFFFFFF init_r11: .int 0x7FFFFFFF
40 0050 FFFFFFFF init_r12: .int 0xFFFFFFFF
41 0054 FFFFFFFF init_r13: .int 0xFFFFFFFF
42 0058 8C20BDE6 init_r14: .int 0x8C20BDE6
43 005c FFFFFFFF init_r15: .int 0xFFFFFFFF
44 0060 76D0DADF init_r16: .int 0x76D0DADF
45 0064 15111F42 init_r17: .int 0x15111F42
46 0068 FFFFFFFF init_r18: .int 0xFFFFFFFF
47 006c 36108E50 init_r19: .int 0x36108E50
48 0070 FFFFFFFF init_r20: .int 0xFFFFFFFF
49 0074 FFFFFFFF init_r21: .int 0xFFFFFFFF
50 0078 328A0CED init_r22: .int 0x328A0CED
51 007c FFFFFFFF init_r23: .int 0xFFFFFFFF
52 0080 FFFFFFFF init_r24: .int 0xFFFFFFFF
53 0084 AF224C19 init_r25: .int 0xAF224C19
54 0088 FFFFFFFF init_r26: .int 0xFFFFFFFF
55 008c FFFFFFFF init_r27: .int 0xFFFFFFFF
56 0090 D624B27A init_r28: .int 0xD624B27A
57 0094 FFFFFFFF init_r29: .int 0xFFFFFFFF
58 0098 FFFFFFFF init_r30: .int 0xFFFFFFFF
59 009c FFFFFFFF init_r31: .int 0xFFFFFFFF
60
61 00a0 DBFD3628 init_cr: .int 0xDBFD3628
62 00a4 89F0006E init_xer: .int 0x89F0006E
63 00a8 FFFFFFFF init_ctr: .int 0xFFFFFFFF
64 00ac FFFFFFFF init_lr: .int 0xFFFFFFFF
65 00b0 FFFFFFFF init_tar: .int 0xFFFFFFFF
66 00b4 00001104 init_msr: .int 0x00001104
67
68 00b8 00010000 init_iar: .int 0x00010000
69
70 00bc 00000000 save_r1: .int 0
71
72 00c0 0000000D codelen: .int 13
73 00c4 7C61CC14 ops: .int 0x7C61CC14,0x7D230595,0x7AC37392,0x7E094C11,0x7E1CB115,0x7A338886,0x7C6004D1,0x
73 7D230595
73 7AC37392
73 7E094C11
73 7E1CB115
74 00f8 00010000 iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x
74 00010004
74 00010008
74 0001000C
74 00010010
75
76 # -------------------------------------------------------------------------------------------------
77 # r3=@tst_inits
78 012c 48000014 .align 5
78 60000000
78 60000000
78 60000000
78 60000000
79 init_tst:
80
81 # save c stuff
82 0140 9023009C stw r1,(save_r1-tst_inits)(r3)
83
84 # copy ops
85 opcopy:
86 0144 802300A0 lwz r1,(codelen-tst_inits)(r3)
87 0148 7C2903A6 mtctr r1
88 014c 382300A4 la r1,(ops-tst_inits)(r3) # @ ops list
89 0150 384300D8 la r2,(iars-tst_inits)(r3) # @ iars list
90 opcopy_loop:
91 0154 80810000 lwz r4,0(r1) # next op
92 0158 80A20000 lwz r5,0(r2) # next iar
93 015c 90850000 stw r4,0(r5) # store it
94 0160 38210004 addi r1,r1,4 # inc to next
95 0164 38420004 addi r2,r2,4
96 0168 4200FFEC bdnz opcopy_loop
97
98 # add end of test op - could be done here or by builder
99 # ways to end:
100 # ba <fixed_loc> - avoid reloc, target op can then branch to tst_end
101 # trap,sc,scv - branch to tst_end in handler
102 # attn, priv op, etc. - "
103 # overwrite the last epilogue op to avoid any crossing
104 opcopy_eot:
105 016c 3C804800 lis r4,0x4800
106 0170 60840006 ori r4,r4,0x0006 # ba 0x0004
107 0174 90850000 stw r4,0(r5)
108
109 # get tst start
110 0178 80200000 lwz r1,init_msr(r0)
111 017c 7C3B03A6 mtsrr1 r1
112 0180 80200000 lwz r1,iars(r0)
113 0184 7C3A03A6 mtsrr0 r1
114
115 # init test regs
116 init_regs:
117 0188 80230080 lwz r1,(init_cr-tst_inits)(r3)
118 018c 7C2FF120 mtcr r1
119 0190 80230084 lwz r1,(init_xer-tst_inits)(r3)
120 0194 7C2103A6 mtxer r1
121 0198 80230088 lwz r1,(init_ctr-tst_inits)(r3)
122 019c 7C2903A6 mtctr r1
123 01a0 8023008C lwz r1,(init_lr-tst_inits)(r3)
124 01a4 7C2803A6 mtlr r1
125 01a8 80230090 lwz r1,(init_tar-tst_inits)(r3)
126 01ac 7C2FCBA6 mtspr tar,r1
127
128 01b0 80030000 lwz r0,(init_r0-tst_inits)(r3)
129 01b4 80230004 lwz r1,(init_r1-tst_inits)(r3)
130 01b8 80430008 lwz r2,(init_r2-tst_inits)(r3)
131 01bc 80830010 lwz r4,(init_r4-tst_inits)(r3)
132 01c0 80A30014 lwz r5,(init_r5-tst_inits)(r3)
133 01c4 80C30018 lwz r6,(init_r6-tst_inits)(r3)
134 01c8 80E3001C lwz r7,(init_r7-tst_inits)(r3)
135 01cc 81030020 lwz r8,(init_r8-tst_inits)(r3)
136 01d0 81230024 lwz r9,(init_r9-tst_inits)(r3)
137 01d4 81430028 lwz r10,(init_r10-tst_inits)(r3)
138 01d8 8163002C lwz r11,(init_r11-tst_inits)(r3)
139 01dc 81830030 lwz r12,(init_r12-tst_inits)(r3)
140 01e0 81A30034 lwz r13,(init_r13-tst_inits)(r3)
141 01e4 81C30038 lwz r14,(init_r14-tst_inits)(r3)
142 01e8 81E3003C lwz r15,(init_r15-tst_inits)(r3)
143 01ec 82030040 lwz r16,(init_r16-tst_inits)(r3)
144 01f0 82230044 lwz r17,(init_r17-tst_inits)(r3)
145 01f4 82430048 lwz r18,(init_r18-tst_inits)(r3)
146 01f8 8263004C lwz r19,(init_r19-tst_inits)(r3)
147 01fc 82830050 lwz r20,(init_r20-tst_inits)(r3)
148 0200 82A30054 lwz r21,(init_r21-tst_inits)(r3)
149 0204 82C30058 lwz r22,(init_r22-tst_inits)(r3)
150 0208 82E3005C lwz r23,(init_r23-tst_inits)(r3)
151 020c 83030060 lwz r24,(init_r24-tst_inits)(r3)
152 0210 83230064 lwz r25,(init_r25-tst_inits)(r3)
153 0214 83430068 lwz r26,(init_r26-tst_inits)(r3)
154 0218 8363006C lwz r27,(init_r27-tst_inits)(r3)
155 021c 83830070 lwz r28,(init_r28-tst_inits)(r3)
156 0220 83A30074 lwz r29,(init_r29-tst_inits)(r3)
157 0224 83C30078 lwz r30,(init_r30-tst_inits)(r3)
158 0228 83E3007C lwz r31,(init_r31-tst_inits)(r3)
159 022c 8063000C lwz r3,(init_r3-tst_inits)(r3)
160
161 jmp2tst:
162 0230 4C000064 rfi
163 #rfid
164 #ba 0x10000
165
166 tst_end:
167 0234 4800000C b save_results
168
169 # -------------------------------------------------------------------------------------------------
170 0238 60000000 .align 5
170 60000000
171 save_results:
172 # use a designated spr to save (sprgx, ...)
173 0240 7C2FCBA6 mtspr SAVESPR,r1
174 0244 3C200000 lis r1,tst_results@h
175 0248 60210000 ori r1,r1,tst_results@l
176 024c 90010000 stw r0,(rslt_r0-tst_results)(r1)
177 0250 90410008 stw r2,(rslt_r2-tst_results)(r1)
178 0254 9061000C stw r3,(rslt_r3-tst_results)(r1)
179 0258 90810010 stw r4,(rslt_r4-tst_results)(r1)
180 025c 90A10014 stw r5,(rslt_r5-tst_results)(r1)
181 0260 90C10018 stw r6,(rslt_r6-tst_results)(r1)
182 0264 90E1001C stw r7,(rslt_r7-tst_results)(r1)
183 0268 91010020 stw r8,(rslt_r8-tst_results)(r1)
184 026c 91210024 stw r9,(rslt_r9-tst_results)(r1)
185 0270 91410028 stw r10,(rslt_r10-tst_results)(r1)
186 0274 9161002C stw r11,(rslt_r11-tst_results)(r1)
187 0278 91810030 stw r12,(rslt_r12-tst_results)(r1)
188 027c 91A10034 stw r13,(rslt_r13-tst_results)(r1)
189 0280 91C10038 stw r14,(rslt_r14-tst_results)(r1)
190 0284 91E1003C stw r15,(rslt_r15-tst_results)(r1)
191 0288 92010040 stw r16,(rslt_r16-tst_results)(r1)
192 028c 92210044 stw r17,(rslt_r17-tst_results)(r1)
193 0290 92410048 stw r18,(rslt_r18-tst_results)(r1)
194 0294 9261004C stw r19,(rslt_r19-tst_results)(r1)
195 0298 92810050 stw r20,(rslt_r20-tst_results)(r1)
196 029c 92A10054 stw r21,(rslt_r21-tst_results)(r1)
197 02a0 92C10058 stw r22,(rslt_r22-tst_results)(r1)
198 02a4 92E1005C stw r23,(rslt_r23-tst_results)(r1)
199 02a8 93010060 stw r24,(rslt_r24-tst_results)(r1)
200 02ac 93210064 stw r25,(rslt_r25-tst_results)(r1)
201 02b0 93410068 stw r26,(rslt_r26-tst_results)(r1)
202 02b4 9361006C stw r27,(rslt_r27-tst_results)(r1)
203 02b8 93810070 stw r28,(rslt_r28-tst_results)(r1)
204 02bc 93A10074 stw r29,(rslt_r29-tst_results)(r1)
205 02c0 93C10078 stw r30,(rslt_r30-tst_results)(r1)
206 02c4 93E1007C stw r31,(rslt_r31-tst_results)(r1)
207 02c8 7C4FCAA6 mfspr r2,SAVESPR
208 02cc 90410004 stw r2,(rslt_r1-tst_results)(r1)
209 02d0 7C400026 mfcr r2
210 02d4 90410080 stw r2,(rslt_cr-tst_results)(r1)
211 02d8 7C4102A6 mfxer r2
212 02dc 90410084 stw r2,(rslt_xer-tst_results)(r1)
213 02e0 7C4902A6 mfctr r2
214 02e4 90410088 stw r2,(rslt_ctr-tst_results)(r1)
215 02e8 7C4802A6 mflr r2
216 02ec 9041008C stw r2,(rslt_lr-tst_results)(r1)
217 02f0 7C4FCAA6 mfspr r2,tar
218 02f4 90410090 stw r2,(rslt_tar-tst_results)(r1)
219
220 tst_cleanup:
221 # restore c stuff
222 02f8 3C600000 lis r3,tst_inits@h
223 02fc 60630000 ori r3,r3,tst_inits@l
224 0300 8023009C lwz r1,(save_r1-tst_inits)(r3)
225 0304 3C600867 lis r3,MAGIC@h
226 0308 60635309 ori r3,r3,MAGIC@l
227
228 030c 48000003 bla tst_done
229
230 # -------------------------------------------------------------------------------------------------
231 0310 60000000 .align 5
231 60000000
231 60000000
231 60000000
232 tst_results:
233
234 0320 FFFFFFFF rslt_r0: .int 0xFFFFFFFF
235 0324 FFFFFFFF rslt_r1: .int 0xFFFFFFFF
236 0328 FFFFFFFF rslt_r2: .int 0xFFFFFFFF
237 032c FFFFFFFF rslt_r3: .int 0xFFFFFFFF
238 0330 FFFFFFFF rslt_r4: .int 0xFFFFFFFF
239 0334 FFFFFFFF rslt_r5: .int 0xFFFFFFFF
240 0338 FFFFFFFF rslt_r6: .int 0xFFFFFFFF
241 033c FFFFFFFF rslt_r7: .int 0xFFFFFFFF
242 0340 FFFFFFFF rslt_r8: .int 0xFFFFFFFF
243 0344 FFFFFFFF rslt_r9: .int 0xFFFFFFFF
244 0348 FFFFFFFF rslt_r10: .int 0xFFFFFFFF
245 034c FFFFFFFF rslt_r11: .int 0xFFFFFFFF
246 0350 FFFFFFFF rslt_r12: .int 0xFFFFFFFF
247 0354 FFFFFFFF rslt_r13: .int 0xFFFFFFFF
248 0358 FFFFFFFF rslt_r14: .int 0xFFFFFFFF
249 035c FFFFFFFF rslt_r15: .int 0xFFFFFFFF
250 0360 FFFFFFFF rslt_r16: .int 0xFFFFFFFF
251 0364 FFFFFFFF rslt_r17: .int 0xFFFFFFFF
252 0368 FFFFFFFF rslt_r18: .int 0xFFFFFFFF
253 036c FFFFFFFF rslt_r19: .int 0xFFFFFFFF
254 0370 FFFFFFFF rslt_r20: .int 0xFFFFFFFF
255 0374 FFFFFFFF rslt_r21: .int 0xFFFFFFFF
256 0378 FFFFFFFF rslt_r22: .int 0xFFFFFFFF
257 037c FFFFFFFF rslt_r23: .int 0xFFFFFFFF
258 0380 FFFFFFFF rslt_r24: .int 0xFFFFFFFF
259 0384 FFFFFFFF rslt_r25: .int 0xFFFFFFFF
260 0388 FFFFFFFF rslt_r26: .int 0xFFFFFFFF
261 038c FFFFFFFF rslt_r27: .int 0xFFFFFFFF
262 0390 FFFFFFFF rslt_r28: .int 0xFFFFFFFF
263 0394 FFFFFFFF rslt_r29: .int 0xFFFFFFFF
264 0398 FFFFFFFF rslt_r30: .int 0xFFFFFFFF
265 039c FFFFFFFF rslt_r31: .int 0xFFFFFFFF
266
267 03a0 FFFFFFFF rslt_cr: .int 0xFFFFFFFF
268 03a4 FFFFFFFF rslt_xer: .int 0xFFFFFFFF
269 03a8 FFFFFFFF rslt_ctr: .int 0xFFFFFFFF
270 03ac FFFFFFFF rslt_lr: .int 0xFFFFFFFF
271 03b0 FFFFFFFF rslt_tar: .int 0xFFFFFFFF
272
273 # -------------------------------------------------------------------------------------------------
274 03b4 60000000 .align 5
274 60000000
274 60000000
275 tst_expects:
276
277 03c0 00000000 expt_r0: .int 0x00000000
278 03c4 CD75F313 expt_r1: .int 0xCD75F313
279 03c8 FFFFFFFF expt_r2: .int 0xFFFFFFFF
280 03cc 00000000 expt_r3: .int 0x00000000
281 03d0 FFFFFFFF expt_r4: .int 0xFFFFFFFF
282 03d4 FFFFFFFF expt_r5: .int 0xFFFFFFFF
283 03d8 FFFFFFFF expt_r6: .int 0xFFFFFFFF
284 03dc FFFFFFFF expt_r7: .int 0xFFFFFFFF
285 03e0 FFFFFFFF expt_r8: .int 0xFFFFFFFF
286 03e4 008A0C68 expt_r9: .int 0x008A0C68
287 03e8 FFFFFFFF expt_r10: .int 0xFFFFFFFF
288 03ec 7FFFFFFF expt_r11: .int 0x7FFFFFFF
289 03f0 FFFFFFFF expt_r12: .int 0xFFFFFFFF
290 03f4 FFFFFFFF expt_r13: .int 0xFFFFFFFF
291 03f8 8C20BDE6 expt_r14: .int 0x8C20BDE6
292 03fc FFFFFFFF expt_r15: .int 0xFFFFFFFF
293 0400 08AEBF68 expt_r16: .int 0x08AEBF68
294 0404 80000001 expt_r17: .int 0x80000001
295 0408 FFFFFFFF expt_r18: .int 0xFFFFFFFF
296 040c 00000000 expt_r19: .int 0x00000000
297 0410 FFFFFFFF expt_r20: .int 0xFFFFFFFF
298 0414 FFFFFFFF expt_r21: .int 0xFFFFFFFF
299 0418 328A0CED expt_r22: .int 0x328A0CED
300 041c FFFFFFFF expt_r23: .int 0xFFFFFFFF
301 0420 FFFFFFFF expt_r24: .int 0xFFFFFFFF
302 0424 AF224C19 expt_r25: .int 0xAF224C19
303 0428 FFFFFFFF expt_r26: .int 0xFFFFFFFF
304 042c FFFFFFFF expt_r27: .int 0xFFFFFFFF
305 0430 D624B27A expt_r28: .int 0xD624B27A
306 0434 FFFFFFFF expt_r29: .int 0xFFFFFFFF
307 0438 FFFFFFFF expt_r30: .int 0xFFFFFFFF
308 043c FFFFFFFF expt_r31: .int 0xFFFFFFFF
309
310 0440 9BFD3628 expt_cr: .int 0x9BFD3628
311 0444 98F0006E expt_xer: .int 0x98F0006E
312 0448 FFFFFFFF expt_ctr: .int 0xFFFFFFFF
313 044c FFFFFFFF expt_lr: .int 0xFFFFFFFF
314 0450 FFFFFFFF expt_tar: .int 0xFFFFFFFF
315 0454 00001104 expt_msr: .int 0x00001104
316
317 0458 00010038 expt_iar: .int 0x00010038
318

318
dev/src/test3_smt/arcitst.s
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# asmtst.tpl

.include "defines.s"

# -------------------------------------------------------------------------------------------------
# c-accessible

.global init_tst
.global tst_start
.global tst_end
.global tst_inits
.global tst_results
.global tst_expects

# -------------------------------------------------------------------------------------------------
tst_misc:

tst_info: .asciz "info text"
tst_header: .asciz "header text"

.set SAVESPR,tar
.set MAGIC,0x8675309

# -------------------------------------------------------------------------------------------------
.align 5
tst_inits:

init_r0: .int 0x00000000
init_r1: .int 0x5822C905
init_r2: .int 0xFFFFFFFF
init_r3: .int 0x91B6D1A3
init_r4: .int 0xFFFFFFFF
init_r5: .int 0xFFFFFFFF
init_r6: .int 0xFFFFFFFF
init_r7: .int 0xFFFFFFFF
init_r8: .int 0xFFFFFFFF
init_r9: .int 0x7E11EE88
init_r10: .int 0xFFFFFFFF
init_r11: .int 0x7FFFFFFF
init_r12: .int 0xFFFFFFFF
init_r13: .int 0xFFFFFFFF
init_r14: .int 0x8C20BDE6
init_r15: .int 0xFFFFFFFF
init_r16: .int 0x76D0DADF
init_r17: .int 0x15111F42
init_r18: .int 0xFFFFFFFF
init_r19: .int 0x36108E50
init_r20: .int 0xFFFFFFFF
init_r21: .int 0xFFFFFFFF
init_r22: .int 0x328A0CED
init_r23: .int 0xFFFFFFFF
init_r24: .int 0xFFFFFFFF
init_r25: .int 0xAF224C19
init_r26: .int 0xFFFFFFFF
init_r27: .int 0xFFFFFFFF
init_r28: .int 0xD624B27A
init_r29: .int 0xFFFFFFFF
init_r30: .int 0xFFFFFFFF
init_r31: .int 0xFFFFFFFF

init_cr: .int 0xDBFD3628
init_xer: .int 0x89F0006E
init_ctr: .int 0xFFFFFFFF
init_lr: .int 0xFFFFFFFF
init_tar: .int 0xFFFFFFFF
init_msr: .int 0x00001104

init_iar: .int 0x00010000

save_r1: .int 0

codelen: .int 13
ops: .int 0x7C61CC14,0x7D230595,0x7AC37392,0x7E094C11,0x7E1CB115,0x7A338886,0x7C6004D1,0x7E09B038,0x7C360591,0x7E2B00D1,0x60000000,0x60000000,0x60000000
iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x0001001C,0x00010020,0x00010024,0x00010028,0x0001002C,0x00010030

# -------------------------------------------------------------------------------------------------
# r3=@tst_inits
.align 5
init_tst:

# save c stuff
stw r1,(save_r1-tst_inits)(r3)

# copy ops
opcopy:
lwz r1,(codelen-tst_inits)(r3)
mtctr r1
la r1,(ops-tst_inits)(r3) # @ ops list
la r2,(iars-tst_inits)(r3) # @ iars list
opcopy_loop:
lwz r4,0(r1) # next op
lwz r5,0(r2) # next iar
stw r4,0(r5) # store it
addi r1,r1,4 # inc to next
addi r2,r2,4
bdnz opcopy_loop

# add end of test op - could be done here or by builder
# ways to end:
# ba <fixed_loc> - avoid reloc, target op can then branch to tst_end
# trap,sc,scv - branch to tst_end in handler
# attn, priv op, etc. - "
# overwrite the last epilogue op to avoid any crossing
opcopy_eot:
lis r4,0x4800
ori r4,r4,0x0006 # ba 0x0004
stw r4,0(r5)

# get tst start
lwz r1,init_msr(r0)
mtsrr1 r1
lwz r1,iars(r0)
mtsrr0 r1

# init test regs
init_regs:
lwz r1,(init_cr-tst_inits)(r3)
mtcr r1
lwz r1,(init_xer-tst_inits)(r3)
mtxer r1
lwz r1,(init_ctr-tst_inits)(r3)
mtctr r1
lwz r1,(init_lr-tst_inits)(r3)
mtlr r1
lwz r1,(init_tar-tst_inits)(r3)
mtspr tar,r1

lwz r0,(init_r0-tst_inits)(r3)
lwz r1,(init_r1-tst_inits)(r3)
lwz r2,(init_r2-tst_inits)(r3)
lwz r4,(init_r4-tst_inits)(r3)
lwz r5,(init_r5-tst_inits)(r3)
lwz r6,(init_r6-tst_inits)(r3)
lwz r7,(init_r7-tst_inits)(r3)
lwz r8,(init_r8-tst_inits)(r3)
lwz r9,(init_r9-tst_inits)(r3)
lwz r10,(init_r10-tst_inits)(r3)
lwz r11,(init_r11-tst_inits)(r3)
lwz r12,(init_r12-tst_inits)(r3)
lwz r13,(init_r13-tst_inits)(r3)
lwz r14,(init_r14-tst_inits)(r3)
lwz r15,(init_r15-tst_inits)(r3)
lwz r16,(init_r16-tst_inits)(r3)
lwz r17,(init_r17-tst_inits)(r3)
lwz r18,(init_r18-tst_inits)(r3)
lwz r19,(init_r19-tst_inits)(r3)
lwz r20,(init_r20-tst_inits)(r3)
lwz r21,(init_r21-tst_inits)(r3)
lwz r22,(init_r22-tst_inits)(r3)
lwz r23,(init_r23-tst_inits)(r3)
lwz r24,(init_r24-tst_inits)(r3)
lwz r25,(init_r25-tst_inits)(r3)
lwz r26,(init_r26-tst_inits)(r3)
lwz r27,(init_r27-tst_inits)(r3)
lwz r28,(init_r28-tst_inits)(r3)
lwz r29,(init_r29-tst_inits)(r3)
lwz r30,(init_r30-tst_inits)(r3)
lwz r31,(init_r31-tst_inits)(r3)
lwz r3,(init_r3-tst_inits)(r3)

jmp2tst:
rfi
#rfid
#ba 0x10000

tst_end:
b save_results

# -------------------------------------------------------------------------------------------------
.align 5
save_results:
# use a designated spr to save (sprgx, ...)
mtspr SAVESPR,r1
lis r1,tst_results@h
ori r1,r1,tst_results@l
stw r0,(rslt_r0-tst_results)(r1)
stw r2,(rslt_r2-tst_results)(r1)
stw r3,(rslt_r3-tst_results)(r1)
stw r4,(rslt_r4-tst_results)(r1)
stw r5,(rslt_r5-tst_results)(r1)
stw r6,(rslt_r6-tst_results)(r1)
stw r7,(rslt_r7-tst_results)(r1)
stw r8,(rslt_r8-tst_results)(r1)
stw r9,(rslt_r9-tst_results)(r1)
stw r10,(rslt_r10-tst_results)(r1)
stw r11,(rslt_r11-tst_results)(r1)
stw r12,(rslt_r12-tst_results)(r1)
stw r13,(rslt_r13-tst_results)(r1)
stw r14,(rslt_r14-tst_results)(r1)
stw r15,(rslt_r15-tst_results)(r1)
stw r16,(rslt_r16-tst_results)(r1)
stw r17,(rslt_r17-tst_results)(r1)
stw r18,(rslt_r18-tst_results)(r1)
stw r19,(rslt_r19-tst_results)(r1)
stw r20,(rslt_r20-tst_results)(r1)
stw r21,(rslt_r21-tst_results)(r1)
stw r22,(rslt_r22-tst_results)(r1)
stw r23,(rslt_r23-tst_results)(r1)
stw r24,(rslt_r24-tst_results)(r1)
stw r25,(rslt_r25-tst_results)(r1)
stw r26,(rslt_r26-tst_results)(r1)
stw r27,(rslt_r27-tst_results)(r1)
stw r28,(rslt_r28-tst_results)(r1)
stw r29,(rslt_r29-tst_results)(r1)
stw r30,(rslt_r30-tst_results)(r1)
stw r31,(rslt_r31-tst_results)(r1)
mfspr r2,SAVESPR
stw r2,(rslt_r1-tst_results)(r1)
mfcr r2
stw r2,(rslt_cr-tst_results)(r1)
mfxer r2
stw r2,(rslt_xer-tst_results)(r1)
mfctr r2
stw r2,(rslt_ctr-tst_results)(r1)
mflr r2
stw r2,(rslt_lr-tst_results)(r1)
mfspr r2,tar
stw r2,(rslt_tar-tst_results)(r1)

tst_cleanup:
# restore c stuff
lis r3,tst_inits@h
ori r3,r3,tst_inits@l
lwz r1,(save_r1-tst_inits)(r3)
lis r3,MAGIC@h
ori r3,r3,MAGIC@l

bla tst_done

# -------------------------------------------------------------------------------------------------
.align 5
tst_results:

rslt_r0: .int 0xFFFFFFFF
rslt_r1: .int 0xFFFFFFFF
rslt_r2: .int 0xFFFFFFFF
rslt_r3: .int 0xFFFFFFFF
rslt_r4: .int 0xFFFFFFFF
rslt_r5: .int 0xFFFFFFFF
rslt_r6: .int 0xFFFFFFFF
rslt_r7: .int 0xFFFFFFFF
rslt_r8: .int 0xFFFFFFFF
rslt_r9: .int 0xFFFFFFFF
rslt_r10: .int 0xFFFFFFFF
rslt_r11: .int 0xFFFFFFFF
rslt_r12: .int 0xFFFFFFFF
rslt_r13: .int 0xFFFFFFFF
rslt_r14: .int 0xFFFFFFFF
rslt_r15: .int 0xFFFFFFFF
rslt_r16: .int 0xFFFFFFFF
rslt_r17: .int 0xFFFFFFFF
rslt_r18: .int 0xFFFFFFFF
rslt_r19: .int 0xFFFFFFFF
rslt_r20: .int 0xFFFFFFFF
rslt_r21: .int 0xFFFFFFFF
rslt_r22: .int 0xFFFFFFFF
rslt_r23: .int 0xFFFFFFFF
rslt_r24: .int 0xFFFFFFFF
rslt_r25: .int 0xFFFFFFFF
rslt_r26: .int 0xFFFFFFFF
rslt_r27: .int 0xFFFFFFFF
rslt_r28: .int 0xFFFFFFFF
rslt_r29: .int 0xFFFFFFFF
rslt_r30: .int 0xFFFFFFFF
rslt_r31: .int 0xFFFFFFFF

rslt_cr: .int 0xFFFFFFFF
rslt_xer: .int 0xFFFFFFFF
rslt_ctr: .int 0xFFFFFFFF
rslt_lr: .int 0xFFFFFFFF
rslt_tar: .int 0xFFFFFFFF

# -------------------------------------------------------------------------------------------------
.align 5
tst_expects:

expt_r0: .int 0x00000000
expt_r1: .int 0xCD75F313
expt_r2: .int 0xFFFFFFFF
expt_r3: .int 0x00000000
expt_r4: .int 0xFFFFFFFF
expt_r5: .int 0xFFFFFFFF
expt_r6: .int 0xFFFFFFFF
expt_r7: .int 0xFFFFFFFF
expt_r8: .int 0xFFFFFFFF
expt_r9: .int 0x008A0C68
expt_r10: .int 0xFFFFFFFF
expt_r11: .int 0x7FFFFFFF
expt_r12: .int 0xFFFFFFFF
expt_r13: .int 0xFFFFFFFF
expt_r14: .int 0x8C20BDE6
expt_r15: .int 0xFFFFFFFF
expt_r16: .int 0x08AEBF68
expt_r17: .int 0x80000001
expt_r18: .int 0xFFFFFFFF
expt_r19: .int 0x00000000
expt_r20: .int 0xFFFFFFFF
expt_r21: .int 0xFFFFFFFF
expt_r22: .int 0x328A0CED
expt_r23: .int 0xFFFFFFFF
expt_r24: .int 0xFFFFFFFF
expt_r25: .int 0xAF224C19
expt_r26: .int 0xFFFFFFFF
expt_r27: .int 0xFFFFFFFF
expt_r28: .int 0xD624B27A
expt_r29: .int 0xFFFFFFFF
expt_r30: .int 0xFFFFFFFF
expt_r31: .int 0xFFFFFFFF

expt_cr: .int 0x9BFD3628
expt_xer: .int 0x98F0006E
expt_ctr: .int 0xFFFFFFFF
expt_lr: .int 0xFFFFFFFF
expt_tar: .int 0xFFFFFFFF
expt_msr: .int 0x00001104

expt_iar: .int 0x00010038

1
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../bin

175
dev/src/test3_smt/bios.c
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#include <stdint.h>
#include <stdio.h>

#include "bios.h"

#ifdef PRINTF
#include "liblitex.h"

//static char printbuf[1000]; // make this a pointer with address a define
//const char* printbuf = (char *)0x12000;
#ifndef PRINTBUF
#define PRINTBUF 0x0001C000
#endif
//static int printbuf_ptr = 0;
static char *printbuf_ptr = (char *)PRINTBUF;
//wtf needs smt
void putchar_handler(char c) {
//printbuf[printbuf_ptr++] = c;
//*(printbuf + printbuf_ptr++) = c;
*printbuf_ptr++ = c;
}
#endif

// arci stuff
//void tst_done(unsigned int rc);
void tst_done(unsigned int rc);

// in kernel (for constant locs)
extern void tst_pass(void);
extern void tst_fail(int i);
/*
void tst_pass(void);
void tst_fail(int i);

void tst_fail(int i) {
while(1) {}
}

void tst_pass(void) {
while(1) {}
}
*/

//inline unsigned int checkResult(unsigned int r) __attribute__((always_inline));
unsigned int checkResult(unsigned int r);

extern unsigned int tst_start;
extern unsigned int tst_end;
extern unsigned int tst_inits;
extern unsigned int tst_results;
extern unsigned int tst_expects;

int main(int tid) {
int *p;
int *fdata = &_fdata;
unsigned int *inits = &tst_inits;

if (tid != 0) {
return -1;
}

// r/w memory init

// copy
for (p = &_fdata_rom; p < &_edata_rom; p++){
*(fdata++) = *p;
}
// zero
for (p = &_fbss; p < &_ebss; p++) {
*(p++) = 0;
}

#ifdef PRINTF
console_set_write_hook(putchar_handler);
putchar('w');
putchar('t');
putchar('f');
putchar('\n');
printf("main(%i)\n", tid);
#endif

// core init
set_epcr(0x03000000); // icm=gicm=1
set_dec(0);
set_tbh(0);
set_tbl(0);
set_tsr(0xFE000000); // mask: clear enw,wis,wrs,dis,fis,udis
set_xucr0(get_xucr0() & ~0x00000200); // set tcs=0
set_tsr(0);
set_tcr(0); // disable all timers

// thread enable
// set_tens(0x3);

// run a .tst
// danger! once r1 is whacked, any c code like bad int handler, etc. needs
// to make sure it has a safe stack for calls
asm (
"mr 3,%0\n"
//"lis 4,init_tst@h\n"
//"ori 4,4,init_tst@l\n"
//"mtctr 4\n"
//"bcctr\n"
"b init_tst\n"
: // outputs
: "r"(inits) // inputs
: "r3" // clobbers
);

while(1) {}
return 0;
}

#define MAGIC 0x08675309

// r1 has been restored to where it was for 'b init_tst' above
void tst_done(unsigned int rc) {
unsigned int i, ok = 1;
unsigned int act, exp;

if (rc != MAGIC) {
tst_fail(0x80000000);
}

// check GPR & CR
for (i = 0; i < 32; i++) {
act = *(&tst_results + i);
exp = *(&tst_expects + i);
ok = ok && (act == exp);
if (!ok) {
tst_fail(i);
}
}

// check XER - a2o not compliant right now (only so/ov/ca/len)
i = 33;
act = *(&tst_results + i);
exp = *(&tst_expects + i) & 0xE000007F;
ok = ok && (act == exp);
if (!ok) {
tst_fail(i);
}

// check CLT - skip tar, a2o doesn't have usermode sprg to use for save reg, so using tar
//for (i = 34; i < 37; i++) {
for (i = 34; i < 36; i++) {
act = *(&tst_results + i);
exp = *(&tst_expects + i);
ok = ok && (act == exp);
if (!ok) {
tst_fail(i);
}
}

// could get back to kernel
tst_pass();
while (1) {}
}

// these are branched to! but if fun, they assume r1 is stack!!!!

// tst is ended with sc to return to priv mode; then save results
void int_sc(int code, int srr0) {
asm (
"b tst_end\n"
: // outputs
: // inputs
: // clobbers
);
}

void int_unhandled(void) {
while(1) {}
}

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dev/src/test3_smt/bios.h
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#ifndef _BIOS_H_
#define _BIOS_H_

// need address for linker constants!
extern int _fdata_rom;
extern int _edata_rom;
extern int _fdata;
extern int _fbss;
extern int _ebss;

// printf to mem
void putchar_handler(char c);


void int_sc(int code, int srr0);
void int_unhandled(void);

inline void set_epcr(int v) __attribute__((always_inline));
inline void set_dec(int v) __attribute__((always_inline));
inline void set_tbh(int v) __attribute__((always_inline));
inline void set_tbl(int v) __attribute__((always_inline));
inline void set_tsr(int v) __attribute__((always_inline));
inline void set_tcr(int v) __attribute__((always_inline));
inline void set_tens(int v) __attribute__((always_inline));
inline void set_xucr0(int v) __attribute__((always_inline));
inline int get_xucr0(void) __attribute__((always_inline));

inline void set_epcr(int v) {
asm volatile(
"mtspr 307,%0\n" // epcr
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_dec(int v) {
asm volatile(
"mtspr 22,%0\n" // dec
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tbh(int v) {
asm volatile(
"mtspr 285,%0\n" // tbh
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tbl(int v) {
asm volatile(
"mtspr 284,%0\n" // tbl
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tsr(int v) {
asm volatile(
"mtspr 336,%0\n" // tsr
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tcr(int v) {
asm volatile(
"mtspr 340,%0\n" // tcr
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline int get_xucr0(void) {
int v;
asm volatile(
"mfspr %0,1014\n" // xucr0
: "=r"(v) // outputs
: // inputs
: // clobbers
);
return v;
}

inline void set_xucr0(int v) {
asm volatile(
"mtspr 1014,%0\n" // xucr0
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tens(int v) {
asm volatile(
"mtspr 438,%0\n" // tens
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

#endif

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# © IBM Corp. 2022
# Licensed under and subject to the terms of the CC-BY 4.0
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
# Additional rights, including the right to physically implement a softcore
# that is compliant with the required sections of the Power ISA
# Specification, will be available at no cost via the OpenPOWER Foundation.
# This README will be updated with additional information when OpenPOWER's
# license is available.

# boot kernel
# resets to 32BE
# set up translations for starting bios (inc. BE/LE)
# copy modifiable rom data to ram - or do in bios?
# set up msr for running bios (inc. 32/64)
# jump to bios


.include "defines.s"

.macro load32 rx,v
li \rx,0
oris \rx,\rx,\v>>16
ori \rx,\rx,\v&0x0000FFFF
.endm

.macro load16swiz rx,v
li \rx,0
ori \rx,\rx,(\v<<8)&0xFF00
ori \rx,\rx,(\v>>8)&0x00FF
.endm

# constants from linker script, or defsym

.ifndef THREAD_ENABLES
.set THREAD_ENABLES 0x1
.endif

.ifdef BIOS_32
# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
.set BIOS_MSR,0x0002B000
.else
# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
.set BIOS_MSR,0x8002B000
.endif

#wtf this should to be done in bios based on the tst
# erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
.ifdef BIOS_LE
.set BIOS_ERATW2,0x000000BF
.else
.set BIOS_ERATW2,0x0000003F
.endif

# bios might be able to use one stack during thread startup if careful
.ifndef BIOS_STACK_0
.set BIOS_STACK_0,_stack_0
.endif

.ifndef BIOS_STACK_1
.set BIOS_STACK_1,_stack_1
.endif

#wtf get rid of this and just make the low 1G a single erat entry - it can be fixed up by bios later
.ifndef BIOS_START
.set BIOS_START,0x00010000
.endif

.section .text

.global _start

.org 0x000
_start:
int_000:
b boot_start

.ifdef TST_END
# tst ends with ba here, which switches to priv and jumps to tst_end
sc
.endif

# critical input
.org 0x020
int_020:
.ifdef INT_UNHANDLED
b int_unhandled
.else
b .
.endif

# debug
.org 0x040
int_040:
b .

# dsi
.org 0x060
int_060:
b .

# isi
.org 0x080
int_080:
b .

# external
.org 0x0A0
int_0A0:
b .

# alignment
.org 0x0C0
int_0C0:
b .

# program
.org 0x0E0
int_0E0:
b .

# fp unavailable
.org 0x100
int_100:
b .

# sc
.org 0x120
int_120:
.ifdef TST_END
# tst results haven't been saved yet; if want to call bios, need to save r1, then restore or set stack
b tst_end
.else
.ifdef INT_SC
# lev is in 20:26, but supposed to use scv now
li r3,0
mfsrr0 r4
b int_sc
.else
.ifdef INT_UNHANDLED
b int_unhandled
.else
b .
.endif
.endif
.endif

# apu unavailable
.org 0x140
int_140:
b .

# decrementer
.org 0x160
int_160:
b .

# fit
.org 0x180
int_180:
b .

# watchdog
.org 0x1A0
int_1A0:
b .

# dtlb
.org 0x1C0
int_1C0:
b .

# itlb
.org 0x1E0
int_1E0:
b .

# vector unavailable
.org 0x200
int_200:
b .

#
.org 0x220
int_220:
b .

#
.org 0x240
int_240:
b .

#
.org 0x260
int_260:
b .

# doorbell
.org 0x280
int_280:
b .

# doorbell critical
.org 0x2A0
int_2A0:
b .

# doorbell guest
.org 0x2C0
int_2C0:
b .

# doorbell guest critical
.org 0x2E0
int_2E0:
b .

# hvsc
.org 0x300
int_300:
b .

# hvpriv
.org 0x320
int_320:
b .

# lrat
.org 0x340
int_340:
b .

# ------------------------------------------------------------------------------------------------------------------------------
# initial translation
# both erats:
# 00000000 64K: (rom, BE)
# 00010000 64K: (ram, BE or LE)
#
.org 0x400
boot_start:

mfspr r5,tir # who am i?
cmpdi r5,0x00 # skip unless T0
bne init_t123

lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)

# derat 31 @00000000
li r0,0x001F # entry #31
li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

mtspr mmucr0,r3
eratwe r2,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63

# derat 30 @<BIOS_START>
li r0,0x001E # entry #30
load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
load32 r8,BIOS_START
ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

eratwe r10,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)

# ierat 15 @00000000
li r0,0x000F # entry #15
li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

mtspr mmucr0,r3
eratwe r2,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

# *** leave the init'd entry 14 for MT access to FFFFFFC0
# ierat 13 @<BIOS_START>
li r0,0x000D # entry #13
load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
load32 r8,BIOS_START
ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

eratwe r10,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

b init_t0

# ------------------------------------------------------------------------------------------------------------------------------
# init
#

# T0

init_t0:

# set up threads
# set thread configuration

li r1,THREAD_ENABLES
mtspr tens,r1 # 60:63 = tid 3:0 enabled
not r1,r1
mtspr tenc,r1 # in case T0 is marked disabled
isync

# set up BIOS msr

load32 r10,BIOS_MSR
mtmsr r10
isync
# can't use load32 unless you can .set BIOS_STACK_0 to the linked value
# load32 r1,BIOS_STACK_0 # @stack_0
# this ignores def
# lis r1,_stack_0@h
# ori r1,r1,_stack_0@l
# this requires data load
lwz r1,stack_0(r0)

b boot_complete

# except T0

init_t123:

# set up BIOS msr

load32 r10,BIOS_MSR
mtmsr r10
isync
# check tir if more than 2 threads possible
lwz r1,stack_1(r0)

b boot_complete

# ------------------------------------------------------------------------------------------------------------------------------
boot_complete:

# set up thread and hop to it

lis r3,main@h
ori r3,r3,main@l
mtctr r3
mfspr r3,tir # who am i?
bctrl
b kernel_return

# ------------------------------------------------------------------------------------------------------------------------------

.ifdef TST_PASSFAIL
.global tst_pass
.global tst_fail

.org 0x7F0
tst_pass:
b .

.org 0x7F4
tst_fail:
b .
.endif

.org 0x7FC
kernel_return:
b .

# dec
.org 0x800
int_800:
b .

# perf
.org 0x820
int_820:
b .

.org 0x8F0
.section .rodata
stack_0: .long BIOS_STACK_0
stack_1: .long BIOS_STACK_1

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#!/usr/bin/bash

export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"

#LITEXLIB=
#PRINTF=
LITEXLIB="libc.o vsnprintf.o console.o"
# getting dtlb in vsnprintf
PRINTF="-DPRINTF"

# defines

## define vars to init rom with csr's it uses...

#
#csr_base=`grep '#define CSR_BASE' generated/csr.h | cut -d ' ' -f 3 | cut -c 1-6`
#uart_base=`grep 'CSR_UART_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
#UART_ADDR="${csr_base}${uart_base}"
#defsyms="-defsym $UART_ADDR"
#
#uart_base=`grep 'CSR_UART_1_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
#if [[ "$uart_base" != "" ]] ; then
# UART_1_ADDR="${csr_base}${uart_base}"
# defsyms="$defsyms -defsym $UART_1_ADDR"
#fi
#
#uart_base=`grep 'CSR_UART_2_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
#if [[ "$uart_base" != "" ]] ; then
# UART_2_ADDR="${csr_base}${uart_base}"
# defsyms="$defsyms -defsym $UART_2_ADDR"
#fi
#
#leds_base=`grep 'CSR_LEDS_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
#if [[ "$leds_base" != "" ]] ; then
# LEDS_ADDR="${csr_base}${leds_base}"
# defsyms="$defsyms -defsym $LEDS_ADDR"
#fi
#
#echo "CSR Addresses"
#echo "Console UART: ${UART_ADDR}"
#echo " LEDS: ${LEDS_ADDR}"
#echo " UART_1: ${UART_1_ADDR}"
#echo " UART_2: ${UART_1_ADDR}"

# a2o nanokernel

echo -n "Compiling..."

echo -n "boot.s "
#powerpc-linux-gnu-as -mbig-endian -ma2 -defsym INT_SC=1 -defsym INT_UNHANDLED=1 -I. boot.s -ahlnd -o crt0.o > crt0.lst
powerpc-linux-gnu-as -mbig-endian -ma2 -defsym THREAD_ENABLES=3 -defsym TST_END=1 -defsym INT_UNHANDLED=1 -defsym TST_PASSFAIL=1 -I. boot.s -ahlnd -o crt0.o > crt0.lst

if [ $? -ne 0 ]; then
exit
fi

echo -n "arcitst.s "
#powerpc-linux-gnu-as -defsym UART_ADDR=$UART_ADDR -defsym LEDS_ADDR=$LEDS_ADDR -defsym UNHANDLED=1 -mbig-endian -mpower9 -I./asm asm/cmod7-boot.s -ahlnd -o crt0.o > crt0.lst
powerpc-linux-gnu-as -mbig-endian -ma2 -I. arcitst.s -ahlnd -o arcitst.o > arcitst.lst
if [ $? -ne 0 ]; then
exit
fi

echo ""
echo -n "bios.c "
powerpc-linux-gnu-gcc $PRINTF -c -I. $CFLAGS bios.c
if [ $? -ne 0 ]; then
exit
fi

echo ""
echo "Linking..."
powerpc-linux-gnu-ld -nostdlib -nodefaultlibs -T linker.ld crt0.o bios.o arcitst.o $LITEXLIB -o rom
if [ $? -ne 0 ]; then
exit
fi

powerpc-linux-gnu-objdump -d rom > rom.d #wtf: why not getting labels in asm code?
powerpc-linux-gnu-objdump -s rom > rom.s
#powerpc-linux-gnu-objcopy --change-section-lma .bios=0x10000 -O binary rom rom.bin
powerpc-linux-gnu-objcopy -O binary rom rom.bin

#python3 -m litex.soc.software.memusage rom ./generated/regions.ld powerpc-linux-gnu

# make rom.bin.hex
bin/bin2init rom.bin
mv rom.bin.hex rom.init

echo "Built rom.d, rom.s, rom.init."

romsize=`grep rom regions.ld | cut -d " " -f 8 | cut -c 3-10`

echo "Hardware ROM Size $romsize"
#echo ""
#echo "CSR Addresses"
#echo "Console UART: ${UART_ADDR}"
#echo " LEDS: ${LEDS_ADDR}"
#echo " UART_1: ${UART_1_ADDR}"
#echo " UART_2: ${UART_2_ADDR}"
#

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#!/usr/bin/bash

export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"

echo -n "Compiling..."

echo ""

echo -n "libc.c "
powerpc-linux-gnu-gcc -c -Ilitex/include/base -Ilitex/include/flibm $CFLAGS -DNO_FLOAT litex/libbase/libc.c
if [ $? -ne 0 ]; then
exit
fi

echo -n "vsnprintf.c "
# NO_FLOAT gets rid of
#snprintf.c:(.text+0x800): undefined reference to `log10'
#powerpc-linux-gnu-ld: vsnprintf.c:(.text+0x80c): undefined reference to `floor'
#powerpc-linux-gnu-ld: vsnprintf.c:(.text+0x824): undefined reference to `pow'
#powerpc-linux-gnu-ld: vsnprintf.c:(.text+0x898): undefined reference to `fmod'
#powerpc-linux-gnu-ld: vsnprintf.c:(.text+0x950): undefined reference to `fmod'
powerpc-linux-gnu-gcc -c -Ilitex/include/base -Ilitex/include/flibm $CFLAGS -DNO_FLOAT litex/libbase/vsnprintf.c
if [ $? -ne 0 ]; then
exit
fi

echo -n "console.c "
# use hacked console.c to printf to mem instead of uart - use console_set_write_hook(console_write_hook putchar_handler)) to print to buffer
#powerpc-linux-gnu-gcc -c -Ilitex/include/base -Ilitex/include/flibm $CFLAGS litex/libbase/console.c
powerpc-linux-gnu-gcc -nostdlib -nodefaultlibs -c -Ilitex/include/base -Ilitex/include/flibm $CFLAGS console.c

if [ $? -ne 0 ]; then
exit
fi

echo ""

#echo "Linking to test dependencies..."
#powerpc-linux-gnu-ld -nostdlib -nodefaultlibs libc.o vsnprintf.o console.o -o litexlib.o
#if [ $? -ne 0 ]; then
# exit
#fi

113
dev/src/test3_smt/console.c
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// use console_set_write_hook(func) to do putchar() to mem

//#include <uart.h>
#include <console.h>
#include <stdio.h>
#include <stdarg.h>

//#include <generated/csr.h>

FILE *stdin, *stdout, *stderr;

static console_write_hook write_hook;
static console_read_hook read_hook;
static console_read_nonblock_hook read_nonblock_hook;

void console_set_write_hook(console_write_hook h)
{
write_hook = h;
}

void console_set_read_hook(console_read_hook r, console_read_nonblock_hook rn)
{
read_hook = r;
read_nonblock_hook = rn;
}

#ifdef CSR_UART_BASE
int putchar(int c)
{
uart_write(c);
if(write_hook != NULL)
write_hook(c);
if (c == '\n')
putchar('\r');
return c;
}

char readchar(void)
{
while(1) {
if(uart_read_nonblock())
return uart_read();
if((read_nonblock_hook != NULL) && read_nonblock_hook())
return read_hook();
}
}

int readchar_nonblock(void)
{
return (uart_read_nonblock()
|| ((read_nonblock_hook != NULL) && read_nonblock_hook()));
}

#else

int putchar(int c)
{
if(write_hook != NULL)
write_hook(c);
return c;
}

char readchar(void)
{
while(1) {
if((read_nonblock_hook != NULL) && read_nonblock_hook())
return read_hook();
}
}

int readchar_nonblock(void)
{
return ((read_nonblock_hook != NULL) && read_nonblock_hook());
}

#endif

int puts(const char *s)
{
putsnonl(s);
putchar('\n');
return 1;
}

void putsnonl(const char *s)
{
while(*s) {
putchar(*s);
s++;
}
}

#define PRINTF_BUFFER_SIZE 256

int vprintf(const char *fmt, va_list args)
{
int len;
char outbuf[PRINTF_BUFFER_SIZE];
len = vscnprintf(outbuf, sizeof(outbuf), fmt, args);
outbuf[len] = 0;
putsnonl(outbuf);
return len;
}

int printf(const char *fmt, ...)
{
int len;
va_list args;
va_start(args, fmt);
len = vprintf(fmt, args);
va_end(args);
return len;
}

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674
dev/src/test3_smt/crt0.lst
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1 # © IBM Corp. 2022
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 # boot kernel
11 # resets to 32BE
12 # set up translations for starting bios (inc. BE/LE)
13 # copy modifiable rom data to ram - or do in bios?
14 # set up msr for running bios (inc. 32/64)
15 # jump to bios
16
17
18 .include "defines.s"
1 # © IBM Corp. 2020
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 #-----------------------------------------
11 # Defines
12 #-----------------------------------------
13
14 # Regs
15
16 .set r0, 0
17 .set r1, 1
18 .set r2, 2
19 .set r3, 3
20 .set r4, 4
21 .set r5, 5
22 .set r6, 6
23 .set r7, 7
24 .set r8, 8
25 .set r9, 9
26 .set r10,10
27 .set r11,11
28 .set r12,12
29 .set r13,13
30 .set r14,14
31 .set r15,15
32 .set r16,16
33 .set r17,17
34 .set r18,18
35 .set r19,19
36 .set r20,20
37 .set r21,21
38 .set r22,22
39 .set r23,23
40 .set r24,24
41 .set r25,25
42 .set r26,26
43 .set r27,27
44 .set r28,28
45 .set r29,29
46 .set r30,30
47 .set r31,31
48
49 .set f0, 0
50 .set f1, 1
51 .set f2, 2
52 .set f3, 3
53 .set f4, 4
54 .set f5, 5
55 .set f6, 6
56 .set f7, 7
57 .set f8, 8
58 .set f9, 9
59 .set f10,10
60 .set f11,11
61 .set f12,12
62 .set f13,13
63 .set f14,14
64 .set f15,15
65 .set f16,16
66 .set f17,17
67 .set f18,18
68 .set f19,19
69 .set f20,20
70 .set f21,21
71 .set f22,22
72 .set f23,23
73 .set f24,24
74 .set f25,25
75 .set f26,26
76 .set f27,27
77 .set f28,28
78 .set f29,29
79 .set f30,30
80 .set f31,31
81
82 .set cr0, 0
83 .set cr1, 1
84 .set cr2, 2
85 .set cr3, 3
86 .set cr4, 4
87 .set cr5, 5
88 .set cr6, 6
89 .set cr7, 7
90
91 # SPR numbers
92
93 .set srr0, 26
94 .set srr1, 27
95 .set dar, 19
96 .set dsisr, 18
97 .set epcr, 307
98 .set tar, 815
99
100 .set dbsr, 304
101 .set dbcr0, 308
102 .set dbcr1, 309
103 .set dbcr2, 310
104 .set dbcr3, 848
105
106 .set ivpr, 63
107
108 .set iucr0, 1011
109 .set iucr1, 883
110 .set iucr2, 884
111
112 .set iudbg0, 888
113 .set iudbg1, 889
114 .set iudbg2, 890
115 .set iulfsr, 891
116 .set iullcr, 892
117
118 .set mmucr0, 1020
119 .set mmucr1, 1021
120 .set mmucr2, 1022
121 .set mmucr3, 1023
122
123 .set tb, 268
124 .set tbl, 284
125 .set tbh, 285
126
127 .set dec, 22
128 .set udec, 550
129 .set tsr, 336
130 .set tcr, 340
131
132 .set xucr0, 1014
133 .set xucr1, 851
134 .set xucr2, 1016
135 .set xucr3, 852
136 .set xucr4, 853
137
138 .set tens, 438
139 .set tenc, 439
140 .set tensr, 437
141
142 .set pid, 48
143 .set pir, 286
144 .set pvr, 287
145 .set tir, 446
146
147 #.set sprg0,
148 #.set sprg1,
149 #.set sprg2,
150 .set sprg3, 259
19
20 .macro load32 rx,v
21 li \rx,0
22 oris \rx,\rx,\v>>16
23 ori \rx,\rx,\v&0x0000FFFF
24 .endm
25
26 .macro load16swiz rx,v
27 li \rx,0
28 ori \rx,\rx,(\v<<8)&0xFF00
29 ori \rx,\rx,(\v>>8)&0x00FF
30 .endm
31
32 # constants from linker script, or defsym
33
34 .ifndef THREAD_ENABLES
35 .set THREAD_ENABLES 0x1
36 .endif
37
38 .ifdef BIOS_32
39 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
40 .set BIOS_MSR,0x0002B000
41 .else
42 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
43 .set BIOS_MSR,0x8002B000
44 .endif
45
46 #wtf this should to be done in bios based on the tst
47 # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw
48 .ifdef BIOS_LE
49 .set BIOS_ERATW2,0x000000BF
50 .else
51 .set BIOS_ERATW2,0x0000003F
52 .endif
53
54 # bios might be able to use one stack during thread startup if careful
55 .ifndef BIOS_STACK_0
56 .set BIOS_STACK_0,_stack_0
57 .endif
58
59 .ifndef BIOS_STACK_1
60 .set BIOS_STACK_1,_stack_1
61 .endif
62
63 #wtf get rid of this and just make the low 1G a single erat entry - it can be fixed up by bios late
64 .ifndef BIOS_START
65 .set BIOS_START,0x00010000
66 .endif
67
68 .section .text
69
70 .global _start
71
72 .org 0x000
73 _start:
74 int_000:
75 0000 48000400 b boot_start
76
77 .ifdef TST_END
78 # tst ends with ba here, which switches to priv and jumps to tst_end
79 0004 44000002 sc
80 .endif
81
82 # critical input
83 0008 00000000 .org 0x020
83 00000000
83 00000000
83 00000000
83 00000000
84 int_020:
85 .ifdef INT_UNHANDLED
86 0020 48000000 b int_unhandled
87 .else
88 b .
89 .endif
90
91 # debug
92 0024 00000000 .org 0x040
92 00000000
92 00000000
92 00000000
92 00000000
93 int_040:
94 0040 48000000 b .
95
96 # dsi
97 0044 00000000 .org 0x060
97 00000000
97 00000000
97 00000000
97 00000000
98 int_060:
99 0060 48000000 b .
100
101 # isi
102 0064 00000000 .org 0x080
102 00000000
102 00000000
102 00000000
102 00000000
103 int_080:
104 0080 48000000 b .
105
106 # external
107 0084 00000000 .org 0x0A0
107 00000000
107 00000000
107 00000000
107 00000000
108 int_0A0:
109 00a0 48000000 b .
110
111 # alignment
112 00a4 00000000 .org 0x0C0
112 00000000
112 00000000
112 00000000
112 00000000
113 int_0C0:
114 00c0 48000000 b .
115
116 # program
117 00c4 00000000 .org 0x0E0
117 00000000
117 00000000
117 00000000
117 00000000
118 int_0E0:
119 00e0 48000000 b .
120
121 # fp unavailable
122 00e4 00000000 .org 0x100
122 00000000
122 00000000
122 00000000
122 00000000
123 int_100:
124 0100 48000000 b .
125
126 # sc
127 0104 00000000 .org 0x120
127 00000000
127 00000000
127 00000000
127 00000000
128 int_120:
129 .ifdef TST_END
130 # tst results haven't been saved yet; if want to call bios, need to save r1, then restore or set st
131 0120 48000000 b tst_end
132 .else
133 .ifdef INT_SC
134 # lev is in 20:26, but supposed to use scv now
135 li r3,0
136 mfsrr0 r4
137 b int_sc
138 .else
139 .ifdef INT_UNHANDLED
140 b int_unhandled
141 .else
142 b .
143 .endif
144 .endif
145 .endif
146
147 # apu unavailable
148 0124 00000000 .org 0x140
148 00000000
148 00000000
148 00000000
148 00000000
149 int_140:
150 0140 48000000 b .
151
152 # decrementer
153 0144 00000000 .org 0x160
153 00000000
153 00000000
153 00000000
153 00000000
154 int_160:
155 0160 48000000 b .
156
157 # fit
158 0164 00000000 .org 0x180
158 00000000
158 00000000
158 00000000
158 00000000
159 int_180:
160 0180 48000000 b .
161
162 # watchdog
163 0184 00000000 .org 0x1A0
163 00000000
163 00000000
163 00000000
163 00000000
164 int_1A0:
165 01a0 48000000 b .
166
167 # dtlb
168 01a4 00000000 .org 0x1C0
168 00000000
168 00000000
168 00000000
168 00000000
169 int_1C0:
170 01c0 48000000 b .
171
172 # itlb
173 01c4 00000000 .org 0x1E0
173 00000000
173 00000000
173 00000000
173 00000000
174 int_1E0:
175 01e0 48000000 b .
176
177 # vector unavailable
178 01e4 00000000 .org 0x200
178 00000000
178 00000000
178 00000000
178 00000000
179 int_200:
180 0200 48000000 b .
181
182 #
183 0204 00000000 .org 0x220
183 00000000
183 00000000
183 00000000
183 00000000
184 int_220:
185 0220 48000000 b .
186
187 #
188 0224 00000000 .org 0x240
188 00000000
188 00000000
188 00000000
188 00000000
189 int_240:
190 0240 48000000 b .
191
192 #
193 0244 00000000 .org 0x260
193 00000000
193 00000000
193 00000000
193 00000000
194 int_260:
195 0260 48000000 b .
196
197 # doorbell
198 0264 00000000 .org 0x280
198 00000000
198 00000000
198 00000000
198 00000000
199 int_280:
200 0280 48000000 b .
201
202 # doorbell critical
203 0284 00000000 .org 0x2A0
203 00000000
203 00000000
203 00000000
203 00000000
204 int_2A0:
205 02a0 48000000 b .
206
207 # doorbell guest
208 02a4 00000000 .org 0x2C0
208 00000000
208 00000000
208 00000000
208 00000000
209 int_2C0:
210 02c0 48000000 b .
211
212 # doorbell guest critical
213 02c4 00000000 .org 0x2E0
213 00000000
213 00000000
213 00000000
213 00000000
214 int_2E0:
215 02e0 48000000 b .
216
217 # hvsc
218 02e4 00000000 .org 0x300
218 00000000
218 00000000
218 00000000
218 00000000
219 int_300:
220 0300 48000000 b .
221
222 # hvpriv
223 0304 00000000 .org 0x320
223 00000000
223 00000000
223 00000000
223 00000000
224 int_320:
225 0320 48000000 b .
226
227 # lrat
228 0324 00000000 .org 0x340
228 00000000
228 00000000
228 00000000
228 00000000
229 int_340:
230 0340 48000000 b .
231
232 # -------------------------------------------------------------------------------------------------
233 # initial translation
234 # both erats:
235 # 00000000 64K: (rom, BE)
236 # 00010000 64K: (ram, BE or LE)
237 #
238 0344 00000000 .org 0x400
238 00000000
238 00000000
238 00000000
238 00000000
239 boot_start:
240
241 0400 7CBE6AA6 mfspr r5,tir # who am i?
242 0404 2C250000 cmpdi r5,0x00 # skip unless T0
243 0408 408200F4 bne init_t123
244
245 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
246
247 # derat 31 @00000000
248 0410 3800001F li r0,0x001F # entry #31
249 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
250 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
251 041c 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
252
253 0420 7C7CFBA6 mtspr mmucr0,r3
254 0424 7C4011A6 eratwe r2,r0,2
255 0428 7C8009A6 eratwe r4,r0,1
256 042c 7D0001A6 eratwe r8,r0,0
257 0430 4C00012C isync
258
259 0434 39400000 load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
259 654A0000
259 614A003F
260
261 # derat 30 @<BIOS_START>
262 0440 3800001E li r0,0x001E # entry #30
263 0444 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
263 64840001
263 60840000
264 0450 39000000 load32 r8,BIOS_START
264 65080001
264 61080000
265 045c 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
266
267 0460 7D4011A6 eratwe r10,r0,2
268 0464 7C8009A6 eratwe r4,r0,1
269 0468 7D0001A6 eratwe r8,r0,0
270 046c 4C00012C isync
271
272 0470 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
273
274 # ierat 15 @00000000
275 0474 3800000F li r0,0x000F # entry #15
276 0478 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
277 047c 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
278 0480 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
279
280 0484 7C7CFBA6 mtspr mmucr0,r3
281 0488 7C4011A6 eratwe r2,r0,2
282 048c 7C8009A6 eratwe r4,r0,1
283 0490 7D0001A6 eratwe r8,r0,0
284 0494 4C00012C isync
285
286 # *** leave the init'd entry 14 for MT access to FFFFFFC0
287 # ierat 13 @<BIOS_START>
288 0498 3800000D li r0,0x000D # entry #13
289 049c 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
289 64840001
289 60840000
290 04a8 39000000 load32 r8,BIOS_START
290 65080001
290 61080000
291 04b4 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
292
293 04b8 7D4011A6 eratwe r10,r0,2
294 04bc 7C8009A6 eratwe r4,r0,1
295 04c0 7D0001A6 eratwe r8,r0,0
296 04c4 4C00012C isync
297
298 04c8 48000004 b init_t0
299
300 # -------------------------------------------------------------------------------------------------
301 # init
302 #
303
304 # T0
305
306 init_t0:
307
308 # set up threads
309 # set thread configuration
310
311 04cc 38200003 li r1,THREAD_ENABLES
312 04d0 7C366BA6 mtspr tens,r1 # 60:63 = tid 3:0 enabled
313 04d4 7C2108F8 not r1,r1
314 04d8 7C376BA6 mtspr tenc,r1 # in case T0 is marked disabled
315 04dc 4C00012C isync
316
317 # set up BIOS msr
318
319 04e0 39400000 load32 r10,BIOS_MSR
319 654A8002
319 614AB000
320 04ec 7D400124 mtmsr r10
321 04f0 4C00012C isync
322 # can't use load32 unless you can .set BIOS_STACK_0 to the linked value
323 # load32 r1,BIOS_STACK_0 # @stack_0
324 # this ignores def
325 # lis r1,_stack_0@h
326 # ori r1,r1,_stack_0@l
327 # this requires data load
328 04f4 80200000 lwz r1,stack_0(r0)
329
330 04f8 48000020 b boot_complete
331
332 # except T0
333
334 init_t123:
335
336 # set up BIOS msr
337
338 04fc 39400000 load32 r10,BIOS_MSR
338 654A8002
338 614AB000
339 0508 7D400124 mtmsr r10
340 050c 4C00012C isync
341 # check tir if more than 2 threads possible
342 0510 80200000 lwz r1,stack_1(r0)
343
344 0514 48000004 b boot_complete
345
346 # -------------------------------------------------------------------------------------------------
347 boot_complete:
348
349 # set up thread and hop to it
350
351 0518 3C600000 lis r3,main@h
352 051c 60630000 ori r3,r3,main@l
353 0520 7C6903A6 mtctr r3
354 0524 7C7E6AA6 mfspr r3,tir # who am i?
355 0528 4E800421 bctrl
356 052c 480002D0 b kernel_return
357
358 # -------------------------------------------------------------------------------------------------
359
360 .ifdef TST_PASSFAIL
361 .global tst_pass
362 .global tst_fail
363
364 0530 00000000 .org 0x7F0
364 00000000
364 00000000
364 00000000
364 00000000
365 tst_pass:
366 07f0 48000000 b .
367
368 .org 0x7F4
369 tst_fail:
370 07f4 48000000 b .
371 .endif
372
373 07f8 00000000 .org 0x7FC
374 kernel_return:
375 07fc 48000000 b .
376
377 # dec
378 .org 0x800
379 int_800:
380 0800 48000000 b .
381
382 # perf
383 0804 00000000 .org 0x820
383 00000000
383 00000000
383 00000000
383 00000000
384 int_820:
385 0820 48000000 b .
386
387 0824 00000000 .org 0x8F0
387 00000000
387 00000000
387 00000000
387 00000000
388 .section .rodata
389 0000 00000000 stack_0: .long BIOS_STACK_0
390 0004 00000000 stack_1: .long BIOS_STACK_1

150
dev/src/test3_smt/defines.s
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# © IBM Corp. 2020
# Licensed under and subject to the terms of the CC-BY 4.0
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
# Additional rights, including the right to physically implement a softcore
# that is compliant with the required sections of the Power ISA
# Specification, will be available at no cost via the OpenPOWER Foundation.
# This README will be updated with additional information when OpenPOWER's
# license is available.

#-----------------------------------------
# Defines
#-----------------------------------------

# Regs

.set r0, 0
.set r1, 1
.set r2, 2
.set r3, 3
.set r4, 4
.set r5, 5
.set r6, 6
.set r7, 7
.set r8, 8
.set r9, 9
.set r10,10
.set r11,11
.set r12,12
.set r13,13
.set r14,14
.set r15,15
.set r16,16
.set r17,17
.set r18,18
.set r19,19
.set r20,20
.set r21,21
.set r22,22
.set r23,23
.set r24,24
.set r25,25
.set r26,26
.set r27,27
.set r28,28
.set r29,29
.set r30,30
.set r31,31

.set f0, 0
.set f1, 1
.set f2, 2
.set f3, 3
.set f4, 4
.set f5, 5
.set f6, 6
.set f7, 7
.set f8, 8
.set f9, 9
.set f10,10
.set f11,11
.set f12,12
.set f13,13
.set f14,14
.set f15,15
.set f16,16
.set f17,17
.set f18,18
.set f19,19
.set f20,20
.set f21,21
.set f22,22
.set f23,23
.set f24,24
.set f25,25
.set f26,26
.set f27,27
.set f28,28
.set f29,29
.set f30,30
.set f31,31

.set cr0, 0
.set cr1, 1
.set cr2, 2
.set cr3, 3
.set cr4, 4
.set cr5, 5
.set cr6, 6
.set cr7, 7

# SPR numbers

.set srr0, 26
.set srr1, 27
.set dar, 19
.set dsisr, 18
.set epcr, 307
.set tar, 815

.set dbsr, 304
.set dbcr0, 308
.set dbcr1, 309
.set dbcr2, 310
.set dbcr3, 848

.set ivpr, 63

.set iucr0, 1011
.set iucr1, 883
.set iucr2, 884

.set iudbg0, 888
.set iudbg1, 889
.set iudbg2, 890
.set iulfsr, 891
.set iullcr, 892

.set mmucr0, 1020
.set mmucr1, 1021
.set mmucr2, 1022
.set mmucr3, 1023

.set tb, 268
.set tbl, 284
.set tbh, 285

.set dec, 22
.set udec, 550
.set tsr, 336
.set tcr, 340

.set xucr0, 1014
.set xucr1, 851
.set xucr2, 1016
.set xucr3, 852
.set xucr4, 853

.set tens, 438
.set tenc, 439
.set tensr, 437

.set pid, 48
.set pir, 286
.set pvr, 287
.set tir, 446

#.set sprg0,
#.set sprg1,
#.set sprg2,
.set sprg3, 259

319
dev/src/test3_smt/fx_alucmpbr.tst
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@ -0,0 +1,319 @@
* OPV
* Testname: fx_alucmpbr.tst

* --------------------------------------------------------------------------------
TEST 1001
INITIALIZATIONS: DATA MEMORY
D 0000000008F00850 0001FFFFFF000007D400000068877812 * PTE Match EPN=0x000000000001 VPN=0x0001FFFFFF000001 RPN=0x000000006887 WIMG=0x2 I TA=0
D 0000000053E6FD70 2000000008F10B02 * Root Table Descriptor , Partition Table Primary Entry for LPID = 0xFD7: HTABORG = 0x0800_0000_023C, HTABSIZE = 0x02, PS = 0x0, Entry Address = 0x0000_0000_53E6_FD70 WIMG=0x2
D 0000000053E6FD78 000618E1E5836C87 * Segmentation On HPT, Process Table Descriptor, Partition Table Secondary Entry for LPID = 0xFD7: PRTB = 0x00_030C_70F2, PTS = 0x07, NUT = 0x0, PTPS = 0x4 WIMG=0x2
D 00000000F0D2D3F0 400AC1CD9CEF56376DF7C045D17603CB * Guest Root Table Descriptor, Process Table Entry for LPID = 0x000 STABORGU = 0x000A_C1CD_9CEF_5637 STABORGL = 0x6 STABSIZE = 0xC B = 0x1 STPS = 0x5
INITIALIZATIONS: INSTRUCTION MEMORY
LEVEL 4 CHIP 0
LEVEL 3 CORE 0
INITIALIZATIONS: REGISTERS
LEVEL 2 PARTITION 0
INITIALIZATIONS: REGISTERS
LEVEL 1 THREAD 0
INITIALIZATIONS: REGISTERS
R CR DBFD3628 * LT:1 GT:1 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R DAR 96A22826D573F45F
R DSISR 48068CFB * TS:0 PF:1 ATT:0 Rsrv35:0 Prot:1 CI:0
* Store:0 Rsrv39_40:0 DAWR:0 VPCK:0
* SMF:0 RADIX:0 RC:1 Guest_Tbl:1
* Rsrv47_61:233E CIX:1 EAO:1
R DEC 0000000005792645
R XER 00002E2289F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:0 LT:1 GT:0 EQ:0 IC:1 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R G0 CC7B4BBA00000000
R G1 F99E00E65822C905
R G3 48577A9C91B6D1A3
R G9 6872DEB47E11EE88
R G11 415D35187FFFFFFF
R G14 BCF163168C20BDE6
R G16 CE83BAA576D0DADF
R G17 06C01CAE15111F42
R G19 4283519E36108E50
R G22 4FA8B87B328A0CED
R G25 9138C732AF224C19
R G28 2F4816B9D624B27A
R IAR 0000000000010000
R MSR 0000000000001104 * SF:0 TA:0 Rsrv2_old_ISF:0 HV:0
* Rsrv4:0 SLE:0 Rsrv6_28:000000 TS:0
* TM:0 Rsrv32_37:00 VMX:0 Rsrv39:0
* VSX:0 S:0 Rsrv42_47:00 EE:0 PR:0 FP:0
* ME:1 FE0:0 SE:0 BE:0 FE1:1 US:0
* Rsrv57_old_IP:0 IR:0 DR:0
* Rsrv60_old_SO:0 PMM:1 RI:0 LE:0

PHASE 0 INSTRUCTIONS
I 0000000068870000 7C61CC14 * EA=0000000000010000 WIMG=2 addco G3,G1,G25 INum:1 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G1 F99E00E65822C905
R G25 9138C732AF224C19
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 0000000000000000 M 0000000000000000 * PTE
TRACE WRITES
R G3 8AD6C8190745151E
R XER 00002E22A9F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:0 LT:1 GT:0 EQ:0 IC:1 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
R IAR 0000000000010004
D 0000000008F00858 D400000068877912 * PTE
I 0000000068870004 7D230595 * EA=0000000000010004 WIMG=2 addzeo. G9,G3 INum:2 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G3 8AD6C8190745151E
R XER 00002E22A9F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:0 LT:1 GT:0 EQ:0 IC:1 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G9 8AD6C8190745151F
R XER 00002E2284F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:0 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R CR 5BFD3628 * LT:0 GT:1 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 0000000000010008
I 0000000068870008 7AC37392 * EA=0000000000010008 WIMG=2 rldcr G3,G22,G14,0x0E INum:3 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G14 BCF163168C20BDE6
R G22 4FA8B87B328A0CED
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G3 A282000000000000
R IAR 000000000001000C
I 000000006887000C 7E094C11 * EA=000000000001000C WIMG=2 subfco. G16,G9,G9 INum:4 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G9 8AD6C8190745151F
R XER 00002E2284F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:0 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G16 0000000000000000
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
R CR 3BFD3628 * LT:0 GT:0 EQ:1 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 0000000000010010
I 0000000068870010 7E1CB115 * EA=0000000000010010 WIMG=2 adde. G16,G28,G22 INum:5 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G28 2F4816B9D624B27A
R G22 4FA8B87B328A0CED
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G16 7EF0CF3508AEBF68
R XER 00002E22B4F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
R CR 5BFD3628 * LT:0 GT:1 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 0000000000010014
I 0000000068870014 7A338886 * EA=0000000000010014 WIMG=2 rldicr G19,G17,0x31,0x02 INum:6 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G17 06C01CAE15111F42
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G19 2000000000000000
R IAR 0000000000010018
I 0000000068870018 7C6004D1 * EA=0000000000010018 WIMG=2 nego. G3,G0 INum:7 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G0 CC7B4BBA00000000
R XER 00002E22B4F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G3 3384B44600000000
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
R CR 3BFD3628 * LT:0 GT:0 EQ:1 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 000000000001001C
I 000000006887001C 7E09B038 * EA=000000000001001C WIMG=2 and G9,G16,G22 INum:8 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G16 7EF0CF3508AEBF68
R G22 4FA8B87B328A0CED
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G9 4EA08831008A0C68
R IAR 0000000000010020
I 0000000068870020 7C360591 * EA=0000000000010020 WIMG=2 subfzeo. G1,G22 INum:9 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G22 4FA8B87B328A0CED
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G1 B0574784CD75F313
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R CR 9BFD3628 * LT:1 GT:0 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 0000000000010024
I 0000000068870024 7E2B00D1 * EA=0000000000010024 WIMG=2 neg. G17,G11 INum:10 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G11 415D35187FFFFFFF
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G17 BEA2CAE780000001
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R CR 9BFD3628 * LT:1 GT:0 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
* FALSE PHASE 0.0 INSTRUCTIONS
R IAR 0000000000010028

EPILOGUE
* Begin macro Epilogue_Sequence
* TRUE
* TRUE
I 0000000068870028 60000000 * EA=0000000000010028 WIMG=2 nop INum:11 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R IAR 000000000001002C
I 000000006887002C 60000000 * EA=000000000001002C WIMG=2 nop_Epilogue INum:12 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R IAR 0000000000010030
I 0000000068870030 60000000 * EA=0000000000010030 WIMG=2 nop_Epilogue INum:13 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R IAR 0000000000010034
I 0000000068870034 24000000 * EA=0000000000010034 WIMG=2 notrace INum:14 PartId:0 ThreadId:0 Phase:0 CoreId:0
* End of macro Epilogue_Sequence
RESULTS: REGISTERS
R CR 9BFD3628 * LT:1 GT:0 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R DAR 96A22826D573F45F
R DSISR 48068CFB * TS:0 PF:1 ATT:0 Rsrv35:0 Prot:1 CI:0
* Store:0 Rsrv39_40:0 DAWR:0 VPCK:0
* SMF:0 RADIX:0 RC:1 Guest_Tbl:1
* Rsrv47_61:233E CIX:1 EAO:1
R DEC 0000000005792645
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R G0 CC7B4BBA00000000
R G1 B0574784CD75F313
R G3 3384B44600000000
R G9 4EA08831008A0C68
R G11 415D35187FFFFFFF
R G14 BCF163168C20BDE6
R G16 7EF0CF3508AEBF68
R G17 BEA2CAE780000001
R G19 2000000000000000
R G22 4FA8B87B328A0CED
R G25 9138C732AF224C19
R G28 2F4816B9D624B27A
R IAR 0000000000010038
R MSR 0000000000001104 * SF:0 TA:0 Rsrv2_old_ISF:0 HV:0
* Rsrv4:0 SLE:0 Rsrv6_28:000000 TS:0
* TM:0 Rsrv32_37:00 VMX:0 Rsrv39:0
* VSX:0 S:0 Rsrv42_47:00 EE:0 PR:0 FP:0
* ME:1 FE0:0 SE:0 BE:0 FE1:1 US:0
* Rsrv57_old_IP:0 IR:0 DR:0
* Rsrv60_old_SO:0 PMM:1 RI:0 LE:0
END_OF_LEVEL 1 THREAD 0
RESULTS: REGISTERS
END_OF_LEVEL 2 PARTITION 0
RESULTS: REGISTERS
END_OF_LEVEL 3 CORE 0
END_OF_LEVEL 4 CHIP 0
RESULTS: DATA MEMORY
D 0000000008F00850 0001FFFFFF000007D400000068877912 * PTE
D 0000000053E6FD70 2000000008F10B02
D 0000000053E6FD78 000618E1E5836C87
D 00000000F0D2D3F0 400AC1CD9CEF56376DF7C045D17603CB
END_OF_TEST

8
dev/src/test3_smt/liblitex.h
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@ -0,0 +1,8 @@
#ifndef _LITEXLIB_
#define _LITEXLIB_

//#include <litex/include/base/console.h>
#include <litex/libbase/console.h>


#endif

94
dev/src/test3_smt/linker.ld
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@ -0,0 +1,94 @@
/* this version puts kernel and bios at rom start

/* define format
INCLUDE output_format.ld */
OUTPUT_FORMAT("elf32-powerpc")

ENTRY(_start)

/* define origin, len of rom, ram, csr */
INCLUDE regions.ld

SECTIONS
{
/* kernel code */
.kernel :
{
/*_fkernel = .; */
*crt0*(.text)
KEEP(*crt0*(.text))
*(.gnu.linkonce.t.*)
_ekernel = .;
} > rom

.rodata :
{
. = ALIGN(8);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
*(.got2 .got2.*)
*(.toc .toc.*)
FILL(0);
. = ALIGN(8);
_erodata = .;
} > rom

/* bios code */
.bios :
{
. = ALIGN(32);
bios.o (.text .text* .gnu.linkonce.t.*)
. = ALIGN(4);
} > rom

/* kernel data to be copied to ram by rom code...*/
.data :
{
. = ALIGN(8);
_fdata = .;
*(.data .data.* .sdata .gnu.linkonce.d.*)
FILL(0);
. = ALIGN(8);
_edata = .;
} > ram AT > rom

/* tst */
.arcitst :
{
. = ALIGN(32);
arcitst.o (.text .text* .gnu.linkonce.t.*)
. = ALIGN(4);
} > rom

.bss :
{
. = 0x0000C000; /*relative to start of ram! ALIGN(16384*4);*/
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
_ebss = .;
_end = .;
} > ram

/DISCARD/ :
{
*(.eh_frame)
*(.comment)
*(.gnu.attributes)
}

}

PROVIDE(_stack_size = 0x00010000);
PROVIDE(_stack_0 = ORIGIN(ram) + LENGTH(ram) - 8);
PROVIDE(_stack_1 = _stack_0 - _stack_size);

PROVIDE(_fdata_rom = LOADADDR(.data));
PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));
PROVIDE(_bios_start = LOADADDR(.bios));

1
dev/src/test3_smt/litex
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@ -0,0 +1 @@
/home/wtf/projects/litex/litex/soc/software

85
dev/src/test3_smt/readme.md
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# test3 - kernel+bios+arci

* gen, convert, and link random tst (fx_alucmpbr.tst), and try to run

```
build

# create mem file for coco sim
cp rom.init test3
```

### methodology

1. produce tst.s (stub code and tst definition) and link with kernel/bios
2. tst init is done in tst.s
3. jmp2tst
4. tst ends (bla through kernel, sc, etc.)
5. tst cleanup is done in tst.s
6. tst checking, etc. is done in bios




### debug

* hanging during results save; itags not executed in cpl queue

![](cpl_hang.png)

* itags 07-0B are dispatched but not marked 'executed' in cplq; they were sent to stq

* not documented completely in spec (CPCR2, CPCR3, CPCR4, CPCR5); 2/3 are for hi-pri and 4/5 for med(?)

```
assign spr_t0_cpcr2_fx0_cnt = cpcr2_l2[0][35:39];
assign spr_t0_cpcr2_fx1_cnt = cpcr2_l2[0][43:47];
assign spr_t0_cpcr2_lq_cnt = cpcr2_l2[0][51:55];
assign spr_t0_cpcr2_sq_cnt = cpcr2_l2[0][59:63];
assign spr_t0_cpcr3_fu0_cnt = cpcr3_l2[0][43:47];
assign spr_t0_cpcr3_fu1_cnt = cpcr3_l2[0][51:55];
assign spr_t0_cpcr3_cp_cnt = cpcr3_l2[0][57:63];
assign spr_t0_cpcr4_fx0_cnt = cpcr4_l2[0][35:39];
assign spr_t0_cpcr4_fx1_cnt = cpcr4_l2[0][43:47];
assign spr_t0_cpcr4_lq_cnt = cpcr4_l2[0][51:55];
assign spr_t0_cpcr4_sq_cnt = cpcr4_l2[0][59:63];
assign spr_t0_cpcr5_fu0_cnt = cpcr5_l2[0][43:47];
assign spr_t0_cpcr5_fu1_cnt = cpcr5_l2[0][51:55];
assign spr_t0_cpcr5_cp_cnt = cpcr5_l2[0][57:63];
```

* verilog violation in iuq_dispatch! unused thread 1 strand bits skipping force to 0, and used later as x's for credit checks which didn't stop dispatch

```
//wtf (THREADS1 is def'd)
// iverilog sez: ../../verilog/work/iuq_dispatch.v:2322: warning: @* found no sensitivities so it will never trigger.
// seems to be correct behavior - block won't be entered without a value change
// make it initial, or a generate?
`ifdef THREADS1
//always @(*)
initial
```


### printf from litex

add putchar function to store to memory buffer

```
/home/wtf/projects/litex/litex/soc/software/libbase/vsnprintf.c

plus at least these:

from /home/wtf/projects/litex/litex/soc/software/include/base/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <ctype.h>
#include <math.h>
#include <stddef.h>

from /home/wtf/projects/litex/litex/soc/software/include/fdlibm
#include <fdlibm.h>
```

6
dev/src/test3_smt/regions.ld
Unescape Escape View File

@ -0,0 +1,6 @@
MEMORY {
rom : ORIGIN = 0x00000000, LENGTH = 0x00010000
tst : ORIGIN = 0x00010000, LENGTH = 0x00002000
ram : ORIGIN = 0x00012000, LENGTH = 0x0000E000
csr : ORIGIN = 0xFFF00000, LENGTH = 0x00010000
}

BIN
dev/src/test3_smt/rom
View File

Binary file not shown.

BIN
dev/src/test3_smt/rom.bin
View File

Binary file not shown.

3608
dev/src/test3_smt/rom.d
View File

File diff suppressed because it is too large Load Diff

3790
dev/src/test3_smt/rom.init
View File

File diff suppressed because it is too large Load Diff

958
dev/src/test3_smt/rom.s
Unescape Escape View File

@ -0,0 +1,958 @@

rom: file format elf32-powerpc

Contents of section .kernel:
0000 48000400 44000002 00000000 00000000 H...D...........
0010 00000000 00000000 00000000 00000000 ................
0020 48001010 00000000 00000000 00000000 H...............
0030 00000000 00000000 00000000 00000000 ................
0040 48000000 00000000 00000000 00000000 H...............
0050 00000000 00000000 00000000 00000000 ................
0060 48000000 00000000 00000000 00000000 H...............
0070 00000000 00000000 00000000 00000000 ................
0080 48000000 00000000 00000000 00000000 H...............
0090 00000000 00000000 00000000 00000000 ................
00a0 48000000 00000000 00000000 00000000 H...............
00b0 00000000 00000000 00000000 00000000 ................
00c0 48000000 00000000 00000000 00000000 H...............
00d0 00000000 00000000 00000000 00000000 ................
00e0 48000000 00000000 00000000 00000000 H...............
00f0 00000000 00000000 00000000 00000000 ................
0100 48000000 00000000 00000000 00000000 H...............
0110 00000000 00000000 00000000 00000000 ................
0120 48001154 00000000 00000000 00000000 H..T............
0130 00000000 00000000 00000000 00000000 ................
0140 48000000 00000000 00000000 00000000 H...............
0150 00000000 00000000 00000000 00000000 ................
0160 48000000 00000000 00000000 00000000 H...............
0170 00000000 00000000 00000000 00000000 ................
0180 48000000 00000000 00000000 00000000 H...............
0190 00000000 00000000 00000000 00000000 ................
01a0 48000000 00000000 00000000 00000000 H...............
01b0 00000000 00000000 00000000 00000000 ................
01c0 48000000 00000000 00000000 00000000 H...............
01d0 00000000 00000000 00000000 00000000 ................
01e0 48000000 00000000 00000000 00000000 H...............
01f0 00000000 00000000 00000000 00000000 ................
0200 48000000 00000000 00000000 00000000 H...............
0210 00000000 00000000 00000000 00000000 ................
0220 48000000 00000000 00000000 00000000 H...............
0230 00000000 00000000 00000000 00000000 ................
0240 48000000 00000000 00000000 00000000 H...............
0250 00000000 00000000 00000000 00000000 ................
0260 48000000 00000000 00000000 00000000 H...............
0270 00000000 00000000 00000000 00000000 ................
0280 48000000 00000000 00000000 00000000 H...............
0290 00000000 00000000 00000000 00000000 ................
02a0 48000000 00000000 00000000 00000000 H...............
02b0 00000000 00000000 00000000 00000000 ................
02c0 48000000 00000000 00000000 00000000 H...............
02d0 00000000 00000000 00000000 00000000 ................
02e0 48000000 00000000 00000000 00000000 H...............
02f0 00000000 00000000 00000000 00000000 ................
0300 48000000 00000000 00000000 00000000 H...............
0310 00000000 00000000 00000000 00000000 ................
0320 48000000 00000000 00000000 00000000 H...............
0330 00000000 00000000 00000000 00000000 ................
0340 48000000 00000000 00000000 00000000 H...............
0350 00000000 00000000 00000000 00000000 ................
0360 00000000 00000000 00000000 00000000 ................
0370 00000000 00000000 00000000 00000000 ................
0380 00000000 00000000 00000000 00000000 ................
0390 00000000 00000000 00000000 00000000 ................
03a0 00000000 00000000 00000000 00000000 ................
03b0 00000000 00000000 00000000 00000000 ................
03c0 00000000 00000000 00000000 00000000 ................
03d0 00000000 00000000 00000000 00000000 ................
03e0 00000000 00000000 00000000 00000000 ................
03f0 00000000 00000000 00000000 00000000 ................
0400 7cbe6aa6 2c250000 408200f4 3c608c00 |.j.,%..@...<`..
0410 3800001f 38400015 38800000 3900023f 8...8@..8...9..?
0420 7c7cfba6 7c4011a6 7c8009a6 7d0001a6 ||..|@..|...}...
0430 4c00012c 39400000 654a0000 614a003f L..,9@..eJ..aJ.?
0440 3800001e 38800000 64840001 60840000 8...8...d...`...
0450 39000000 65080001 61080000 6108023f 9...e...a...a..?
0460 7d4011a6 7c8009a6 7d0001a6 4c00012c }@..|...}...L..,
0470 3c608800 3800000f 3840003f 38800000 <`..8...8@.?8...
0480 3900023f 7c7cfba6 7c4011a6 7c8009a6 9..?||..|@..|...
0490 7d0001a6 4c00012c 3800000d 38800000 }...L..,8...8...
04a0 64840001 60840000 39000000 65080001 d...`...9...e...
04b0 61080000 6108023f 7d4011a6 7c8009a6 a...a..?}@..|...
04c0 7d0001a6 4c00012c 48000004 38200003 }...L..,H...8 ..
04d0 7c366ba6 7c2108f8 7c376ba6 4c00012c |6k.|!..|7k.L..,
04e0 39400000 654a8002 614ab000 7d400124 9@..eJ..aJ..}@.$
04f0 4c00012c 802008fa 48000020 39400000 L..,. ..H.. 9@..
0500 654a8002 614ab000 7d400124 4c00012c eJ..aJ..}@.$L..,
0510 802008fe 48000004 3c600000 60630c34 . ..H...<`..`c.4
0520 7c6903a6 7c7e6aa6 4e800421 480002d0 |i..|~j.N..!H...
0530 00000000 00000000 00000000 00000000 ................
0540 00000000 00000000 00000000 00000000 ................
0550 00000000 00000000 00000000 00000000 ................
0560 00000000 00000000 00000000 00000000 ................
0570 00000000 00000000 00000000 00000000 ................
0580 00000000 00000000 00000000 00000000 ................
0590 00000000 00000000 00000000 00000000 ................
05a0 00000000 00000000 00000000 00000000 ................
05b0 00000000 00000000 00000000 00000000 ................
05c0 00000000 00000000 00000000 00000000 ................
05d0 00000000 00000000 00000000 00000000 ................
05e0 00000000 00000000 00000000 00000000 ................
05f0 00000000 00000000 00000000 00000000 ................
0600 00000000 00000000 00000000 00000000 ................
0610 00000000 00000000 00000000 00000000 ................
0620 00000000 00000000 00000000 00000000 ................
0630 00000000 00000000 00000000 00000000 ................
0640 00000000 00000000 00000000 00000000 ................
0650 00000000 00000000 00000000 00000000 ................
0660 00000000 00000000 00000000 00000000 ................
0670 00000000 00000000 00000000 00000000 ................
0680 00000000 00000000 00000000 00000000 ................
0690 00000000 00000000 00000000 00000000 ................
06a0 00000000 00000000 00000000 00000000 ................
06b0 00000000 00000000 00000000 00000000 ................
06c0 00000000 00000000 00000000 00000000 ................
06d0 00000000 00000000 00000000 00000000 ................
06e0 00000000 00000000 00000000 00000000 ................
06f0 00000000 00000000 00000000 00000000 ................
0700 00000000 00000000 00000000 00000000 ................
0710 00000000 00000000 00000000 00000000 ................
0720 00000000 00000000 00000000 00000000 ................
0730 00000000 00000000 00000000 00000000 ................
0740 00000000 00000000 00000000 00000000 ................
0750 00000000 00000000 00000000 00000000 ................
0760 00000000 00000000 00000000 00000000 ................
0770 00000000 00000000 00000000 00000000 ................
0780 00000000 00000000 00000000 00000000 ................
0790 00000000 00000000 00000000 00000000 ................
07a0 00000000 00000000 00000000 00000000 ................
07b0 00000000 00000000 00000000 00000000 ................
07c0 00000000 00000000 00000000 00000000 ................
07d0 00000000 00000000 00000000 00000000 ................
07e0 00000000 00000000 00000000 00000000 ................
07f0 48000000 48000000 00000000 48000000 H...H.......H...
0800 48000000 00000000 00000000 00000000 H...............
0810 00000000 00000000 00000000 00000000 ................
0820 48000000 00000000 00000000 00000000 H...............
0830 00000000 00000000 00000000 00000000 ................
0840 00000000 00000000 00000000 00000000 ................
0850 00000000 00000000 00000000 00000000 ................
0860 00000000 00000000 00000000 00000000 ................
0870 00000000 00000000 00000000 00000000 ................
0880 00000000 00000000 00000000 00000000 ................
0890 00000000 00000000 00000000 00000000 ................
08a0 00000000 00000000 00000000 00000000 ................
08b0 00000000 00000000 00000000 00000000 ................
08c0 00000000 00000000 00000000 00000000 ................
08d0 00000000 00000000 00000000 00000000 ................
08e0 00000000 00000000 00000000 00000000 ................
Contents of section .rodata:
08f0 6d61696e 28256929 0a000001 fff80000 main(%i)........
0900 fff80000 08080808 08080808 08282828 .............(((
0910 28280808 08080808 08080808 08080808 ((..............
0920 08080808 a0101010 10101010 10101010 ................
0930 10101010 04040404 04040404 04041010 ................
0940 10101010 10414141 41414101 01010101 .....AAAAAA.....
0950 01010101 01010101 01010101 01010110 ................
0960 10101010 10424242 42424202 02020202 .....BBBBBB.....
0970 02020202 02020202 02020202 02020210 ................
0980 10101008 00000000 00000000 00000000 ................
0990 00000000 00000000 00000000 00000000 ................
09a0 00000000 a0101010 10101010 10101010 ................
09b0 10101010 10101010 10101010 10101010 ................
09c0 10101010 01010101 01010101 01010101 ................
09d0 01010101 01010101 01010110 01010101 ................
09e0 01010102 02020202 02020202 02020202 ................
09f0 02020202 02020202 02020210 02020202 ................
0a00 02020202 41626f72 7465642e 00000000 ....Aborted.....
0a10 30313233 34353637 38394142 43444546 0123456789ABCDEF
0a20 4748494a 4b4c4d4e 4f505152 53545556 GHIJKLMNOPQRSTUV
0a30 5758595a 00000000 30313233 34353637 WXYZ....01234567
0a40 38396162 63646566 6768696a 6b6c6d6e 89abcdefghijklmn
0a50 6f707172 73747576 7778797a 00000000 opqrstuvwxyz....
0a60 3c4e554c 4c3e0000 00002180 000021b0 <NULL>....!...!.
0a70 000021b0 00002190 000021b0 000021b0 ..!...!...!...!.
0a80 000021b0 000021b0 000021b0 000021b0 ..!...!...!...!.
0a90 000021b0 00002170 000021b0 00002160 ..!...!p..!...!`
0aa0 000021b0 000021b0 000021a0 000028e8 ..!...!...!...(.
0ab0 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0ac0 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0ad0 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0ae0 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0af0 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0b00 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0b10 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0b20 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0b30 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0b40 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0b50 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0b60 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0b70 00002948 00002948 00002920 00002948 ..)H..)H..) ..)H
0b80 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0b90 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0ba0 00002948 00002424 00002938 00002948 ..)H..$$..)8..)H
0bb0 00002948 00002948 00002948 00002938 ..)H..)H..)H..)8
0bc0 00002948 00002948 00002948 00002948 ..)H..)H..)H..)H
0bd0 0000276c 00002914 000026c4 00002948 ..'l..)...&...)H
0be0 00002948 00002540 00002948 000029c0 ..)H..%@..)H..).
0bf0 00002948 00002948 0000292c 00000000 ..)H..)H..),....
Contents of section .bios:
0c00 9421fff0 7c691b78 99210008 3d200001 .!..|i.x.!..= ..
0c10 81292000 39090001 3d400001 910a2000 .) .9...=@.... .
0c20 89410008 99490000 60000000 38210010 .A...I..`...8!..
0c30 4e800020 9421ffc0 7c0802a6 90010044 N.. .!..|......D
0c40 90610038 3d200001 39292000 9121000c .a.8= ..9) ..!..
0c50 3d200000 39291060 91210010 81210038 = ..9).`.!...!.8
0c60 2c090000 4182000c 3920ffff 48000190 ,...A...9 ..H...
0c70 3d200000 39291034 91210008 48000028 = ..9).4.!..H..(
0c80 8121000c 39490004 9141000c 81410008 .!..9I...A...A..
0c90 814a0000 91490000 81210008 39290004 .J...I...!..9)..
0ca0 91210008 81410008 3d200000 3929103c .!...A..= ..9).<
0cb0 7c0a4840 4180ffcc 3d200002 3929e008 |.H@A...= ..9)..
0cc0 91210008 48000024 81210008 39490004 .!..H..$.!..9I..
0cd0 91410008 39400000 91490000 81210008 .A..9@...I...!..
0ce0 39290004 91210008 81410008 3d200002 9)...!...A..= ..
0cf0 3929e028 7c0a4840 4180ffd0 3d200000 9).(|.H@A...= ..
0d00 38690c00 4cc63182 48002b39 38600077 8i..L.1.H.+98`.w
0d10 48002b81 38600074 48002b79 38600066 H.+.8`.tH.+y8`.f
0d20 48002b71 3860000a 48002b69 80810038 H.+q8`..H.+i...8
0d30 3d200000 386908f0 4cc63182 48002d5d = ..8i..L.1.H.-]
0d40 3d200300 91210034 81210034 7d334ba6 = ...!.4.!.4}3K.
0d50 60000000 39200000 91210030 81210030 `...9 ...!.0.!.0
0d60 7d3603a6 60000000 39200000 9121002c }6..`...9 ...!.,
0d70 8121002c 7d3d43a6 60000000 39200000 .!.,}=C.`...9 ..
0d80 91210028 81210028 7d3c43a6 60000000 .!.(.!.(}<C.`...
0d90 3d20fe00 91210024 81210024 7d3053a6 = ...!.$.!.$}0S.
0da0 60000000 7d36faa6 91210020 81210020 `...}6...!. .!.
0db0 552905ea 9121001c 8121001c 7d36fba6 U)...!...!..}6..
0dc0 60000000 39200000 91210018 81210018 `...9 ...!...!..
0dd0 7d3053a6 60000000 39200000 91210014 }0S.`...9 ...!..
0de0 81210014 7d3453a6 60000000 81210010 .!..}4S.`....!..
0df0 7d234b78 4800038c 48000000 7d234b78 }#KxH...H...}#Kx
0e00 80010044 7c0803a6 38210040 4e800020 ...D|...8!.@N..
0e10 9421ffe0 7c0802a6 90010024 90610018 .!..|......$.a..
0e20 39200001 9121000c 81410018 3d200867 9 ...!...A..= .g
0e30 61295309 7c0a4800 4182000c 3c608000 a)S.|.H.A...<`..
0e40 4bfff9b5 39200000 91210008 4800008c K...9 ...!..H...
0e50 81210008 552a103a 3d200000 39291360 .!..U*.:= ..9).`
0e60 7d2a4a14 81290000 91210010 81210008 }*J..)...!...!..
0e70 552a103a 3d200000 39291400 7d2a4a14 U*.:= ..9)..}*J.
0e80 81290000 91210014 8121000c 2c090000 .)...!...!..,...
0e90 4182001c 81410010 81210014 7c0a4800 A....A...!..|.H.
0ea0 4082000c 39200001 48000008 39200000 @...9 ..H...9 ..
0eb0 9121000c 8121000c 2c090000 40820010 .!...!..,...@...
0ec0 81210008 7d234b78 4bfff92d 81210008 .!..}#KxK..-.!..
0ed0 39290001 91210008 81210008 2809001f 9)...!...!..(...
0ee0 4081ff70 39200021 91210008 81210008 @..p9 .!.!...!..
0ef0 552a103a 3d200000 39291360 7d2a4a14 U*.:= ..9).`}*J.
0f00 81290000 91210010 81210008 552a103a .)...!...!..U*.:
0f10 3d200000 39291400 7d2a4a14 81290000 = ..9)..}*J..)..
0f20 55290644 91210014 8121000c 2c090000 U).D.!...!..,...
0f30 4182001c 81410010 81210014 7c0a4800 A....A...!..|.H.
0f40 4082000c 39200001 48000008 39200000 @...9 ..H...9 ..
0f50 9121000c 8121000c 2c090000 40820010 .!...!..,...@...
0f60 81210008 7d234b78 4bfff88d 39200022 .!..}#KxK...9 ."
0f70 91210008 4800008c 81210008 552a103a .!..H....!..U*.:
0f80 3d200000 39291360 7d2a4a14 81290000 = ..9).`}*J..)..
0f90 91210010 81210008 552a103a 3d200000 .!...!..U*.:= ..
0fa0 39291400 7d2a4a14 81290000 91210014 9)..}*J..)...!..
0fb0 8121000c 2c090000 4182001c 81410010 .!..,...A....A..
0fc0 81210014 7c0a4800 4082000c 39200001 .!..|.H.@...9 ..
0fd0 48000008 39200000 9121000c 8121000c H...9 ...!...!..
0fe0 2c090000 40820010 81210008 7d234b78 ,...@....!..}#Kx
0ff0 4bfff805 81210008 39290001 91210008 K....!..9)...!..
1000 81210008 28090023 4081ff70 4bfff7e5 .!..(..#@..pK...
1010 48000000 9421fff0 90610008 9081000c H....!...a......
1020 48000254 60000000 38210010 4e800020 H..T`...8!..N..
1030 48000000 H...
Contents of section .data:
12000 0001c000 00000000 ........
Contents of section .arcitst:
1040 696e666f 20746578 74006865 61646572 info text.header
1050 20746578 74000000 00000000 00000000 text...........
1060 00000000 5822c905 ffffffff 91b6d1a3 ....X"..........
1070 ffffffff ffffffff ffffffff ffffffff ................
1080 ffffffff 7e11ee88 ffffffff 7fffffff ....~...........
1090 ffffffff ffffffff 8c20bde6 ffffffff ......... ......
10a0 76d0dadf 15111f42 ffffffff 36108e50 v......B....6..P
10b0 ffffffff ffffffff 328a0ced ffffffff ........2.......
10c0 ffffffff af224c19 ffffffff ffffffff ....."L.........
10d0 d624b27a ffffffff ffffffff ffffffff .$.z............
10e0 dbfd3628 89f0006e ffffffff ffffffff ..6(...n........
10f0 ffffffff 00001104 00010000 00000000 ................
1100 0000000d 7c61cc14 7d230595 7ac37392 ....|a..}#..z.s.
1110 7e094c11 7e1cb115 7a338886 7c6004d1 ~.L.~...z3..|`..
1120 7e09b038 7c360591 7e2b00d1 60000000 ~..8|6..~+..`...
1130 60000000 60000000 00010000 00010004 `...`...........
1140 00010008 0001000c 00010010 00010014 ................
1150 00010018 0001001c 00010020 00010024 ........... ...$
1160 00010028 0001002c 00010030 48000014 ...(...,...0H...
1170 60000000 60000000 60000000 60000000 `...`...`...`...
1180 9023009c 802300a0 7c2903a6 382300a4 .#...#..|)..8#..
1190 384300d8 80810000 80a20000 90850000 8C..............
11a0 38210004 38420004 4200ffec 3c804800 8!..8B..B...<.H.
11b0 60840006 90850000 802010f4 7c3b03a6 `........ ..|;..
11c0 80201138 7c3a03a6 80230080 7c2ff120 . .8|:...#..|/.
11d0 80230084 7c2103a6 80230088 7c2903a6 .#..|!...#..|)..
11e0 8023008c 7c2803a6 80230090 7c2fcba6 .#..|(...#..|/..
11f0 80030000 80230004 80430008 80830010 .....#...C......
1200 80a30014 80c30018 80e3001c 81030020 ...............
1210 81230024 81430028 8163002c 81830030 .#.$.C.(.c.,...0
1220 81a30034 81c30038 81e3003c 82030040 ...4...8...<...@
1230 82230044 82430048 8263004c 82830050 .#.D.C.H.c.L...P
1240 82a30054 82c30058 82e3005c 83030060 ...T...X...\...`
1250 83230064 83430068 8363006c 83830070 .#.d.C.h.c.l...p
1260 83a30074 83c30078 83e3007c 8063000c ...t...x...|.c..
1270 4c000064 4800000c 60000000 60000000 L..dH...`...`...
1280 7c2fcba6 3c200000 60211360 90010000 |/..< ..`!.`....
1290 90410008 9061000c 90810010 90a10014 .A...a..........
12a0 90c10018 90e1001c 91010020 91210024 ........... .!.$
12b0 91410028 9161002c 91810030 91a10034 .A.(.a.,...0...4
12c0 91c10038 91e1003c 92010040 92210044 ...8...<...@.!.D
12d0 92410048 9261004c 92810050 92a10054 .A.H.a.L...P...T
12e0 92c10058 92e1005c 93010060 93210064 ...X...\...`.!.d
12f0 93410068 9361006c 93810070 93a10074 .A.h.a.l...p...t
1300 93c10078 93e1007c 7c4fcaa6 90410004 ...x...||O...A..
1310 7c400026 90410080 7c4102a6 90410084 |@.&.A..|A...A..
1320 7c4902a6 90410088 7c4802a6 9041008c |I...A..|H...A..
1330 7c4fcaa6 90410090 3c600000 60631060 |O...A..<`..`c.`
1340 8023009c 3c600867 60635309 48000e13 .#..<`.g`cS.H...
1350 60000000 60000000 60000000 60000000 `...`...`...`...
1360 ffffffff ffffffff ffffffff ffffffff ................
1370 ffffffff ffffffff ffffffff ffffffff ................
1380 ffffffff ffffffff ffffffff ffffffff ................
1390 ffffffff ffffffff ffffffff ffffffff ................
13a0 ffffffff ffffffff ffffffff ffffffff ................
13b0 ffffffff ffffffff ffffffff ffffffff ................
13c0 ffffffff ffffffff ffffffff ffffffff ................
13d0 ffffffff ffffffff ffffffff ffffffff ................
13e0 ffffffff ffffffff ffffffff ffffffff ................
13f0 ffffffff 60000000 60000000 60000000 ....`...`...`...
1400 00000000 cd75f313 ffffffff 00000000 .....u..........
1410 ffffffff ffffffff ffffffff ffffffff ................
1420 ffffffff 008a0c68 ffffffff 7fffffff .......h........
1430 ffffffff ffffffff 8c20bde6 ffffffff ......... ......
1440 08aebf68 80000001 ffffffff 00000000 ...h............
1450 ffffffff ffffffff 328a0ced ffffffff ........2.......
1460 ffffffff af224c19 ffffffff ffffffff ....."L.........
1470 d624b27a ffffffff ffffffff ffffffff .$.z............
1480 9bfd3628 98f0006e ffffffff ffffffff ..6(...n........
1490 ffffffff 00001104 00010038 ...........8
Contents of section .text:
149c 9421fff0 7c691b78 99210008 89210008 .!..|i.x.!...!..
14ac 3d400000 394a0904 7d2a48ae 552907bc =@..9J..}*H.U)..
14bc 2c090000 41820010 89210008 3929ffe0 ,...A....!..9)..
14cc 99210008 89210008 7d234b78 38210010 .!...!..}#Kx8!..
14dc 4e800020 9421fff0 7c691b78 b1210008 N.. .!..|i.x.!..
14ec a1210008 5529402e 7d2a0734 a1210008 .!..U)@.}*.4.!..
14fc 5529c23e 5529043e 7d290734 7d494b78 U).>U).>}).4}IKx
150c 7d290734 5529043e 7d234b78 38210010 }).4U).>}#Kx8!..
151c 4e800020 9421fff0 90610008 81210008 N.. .!...a...!..
152c 552a463e 81210008 5529c23e 5529042e U*F>.!..U).>U)..
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375c 81290004 39090004 81410054 910a0004 .)..9....A.T....
376c 81290000 9121000c 39200000 91210008 .)...!..9 ...!..
377c 81210024 552907bc 2c090000 41820014 .!.$U)..,...A...
378c 8121000c 9121000c 7d29fe70 91210008 .!...!..}).p.!..
379c 8141000c 81210024 8101002c 80e10028 .A...!.$...,...(
37ac 80c10014 7d455378 8081001c 80610018 ....}ESx.....a..
37bc 4bffea09 7c691b78 91210018 81210050 K...|i.x.!...!.P
37cc 39290001 91210050 81210050 89290000 9)...!.P.!.P.)..
37dc 2c090000 4082f358 8121004c 2c090000 ,...@..X.!.L,...
37ec 41820034 81410018 8121001c 7c0a4840 A..4.A...!..|.H@
37fc 40800014 81210018 39400000 99490000 @....!..9@...I..
380c 48000014 8121001c 3929ffff 39400000 H....!..9)..9@..
381c 99490000 81410018 81210048 7d295050 .I...A...!.H})PP
382c 7d234b78 80010064 7c0803a6 38210060 }#Kx...d|...8!.`
383c 4e800020 9421fff0 90610008 3d200002 N.. .!...a..= ..
384c 81410008 9149e018 60000000 38210010 .A...I..`...8!..
385c 4e800020 9421fff0 90610008 9081000c N.. .!...a......
386c 3d200002 81410008 9149e01c 3d200002 = ...A...I..= ..
387c 8141000c 9149e020 60000000 38210010 .A...I. `...8!..
388c 4e800020 9421fff0 7c0802a6 90010014 N.. .!..|.......
389c 90610008 3d200002 8129e018 2c090000 .a..= ...)..,...
38ac 41820020 3d200002 8129e018 81410008 A.. = ...)...A..
38bc 554a063e 7d435378 7d2903a6 4e800421 UJ.>}CSx})..N..!
38cc 81210008 7d234b78 80010014 7c0803a6 .!..}#Kx....|...
38dc 38210010 4e800020 9421fff0 7c0802a6 8!..N.. .!..|...
38ec 90010014 3d200002 8129e020 2c090000 ....= ...). ,...
38fc 4182fff4 3d200002 8129e020 7d2903a6 A...= ...). })..
390c 4e800421 7c691b78 2c090000 4182ffd8 N..!|i.x,...A...
391c 3d200002 8129e01c 7d2903a6 4e800421 = ...)..})..N..!
392c 7c691b78 7d234b78 80010014 7c0803a6 |i.x}#Kx....|...
393c 38210010 4e800020 9421fff0 7c0802a6 8!..N.. .!..|...
394c 90010014 3d200002 8129e020 2c090000 ....= ...). ,...
395c 41820028 3d200002 8129e020 7d2903a6 A..(= ...). })..
396c 4e800421 7c691b78 2c090000 4182000c N..!|i.x,...A...
397c 39200001 48000008 39200000 7d234b78 9 ..H...9 ..}#Kx
398c 80010014 7c0803a6 38210010 4e800020 ....|...8!..N..
399c 9421fff0 7c0802a6 90010014 90610008 .!..|........a..
39ac 80610008 48000025 3860000a 4bfffed9 .a..H..%8`..K...
39bc 39200001 7d234b78 80010014 7c0803a6 9 ..}#Kx....|...
39cc 38210010 4e800020 9421fff0 7c0802a6 8!..N.. .!..|...
39dc 90010014 90610008 48000020 81210008 .....a..H.. .!..
39ec 89290000 7d234b78 4bfffe9d 81210008 .)..}#KxK....!..
39fc 39290001 91210008 81210008 89290000 9)...!...!...)..
3a0c 2c090000 4082ffd8 60000000 60000000 ,...@...`...`...
3a1c 80010014 7c0803a6 38210010 4e800020 ....|...8!..N..
3a2c 9421fee0 7c0802a6 90010124 90610118 .!..|......$.a..
3a3c 9081011c 3921000c 80c1011c 80a10118 ....9!..........
3a4c 38800100 7d234b78 4bffebf9 7c691b78 8...}#KxK...|i.x
3a5c 91210008 3941000c 81210008 7d2a4a14 .!..9A...!..}*J.
3a6c 39400000 99490000 3921000c 7d234b78 9@...I..9!..}#Kx
3a7c 4bffff59 81210008 7d234b78 80010124 K..Y.!..}#Kx...$
3a8c 7c0803a6 38210120 4e800020 9421ff80 |...8!. N.. .!..
3a9c 7c0802a6 90010084 90610018 90810024 |........a.....$
3aac 90a10028 90c1002c 90e10030 91010034 ...(...,...0...4
3abc 91210038 9141003c 40860024 d8210040 .!.8.A.<@..$.!.@
3acc d8410048 d8610050 d8810058 d8a10060 .A.H.a.P...X...`
3adc d8c10068 d8e10070 d9010078 39200001 ...h...p...x9 ..
3aec 9921000c 39200000 9921000d 39210088 .!..9 ...!..9!..
3afc 91210010 39210020 91210014 3921000c .!..9!. .!..9!..
3b0c 7d244b78 80610018 4bffff19 7c691b78 }$Kx.a..K...|i.x
3b1c 91210008 81210008 7d234b78 80010084 .!...!..}#Kx....
3b2c 7c0803a6 38210080 4e800020 |...8!..N..

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dev/src/test3_soc/arcitst.h
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# asmtst.tpl
# powerpc-linux-gnu-as -c arcitst.s

.include "defines.s"

# -------------------------------------------------------------------------------------------------
# c-accessible

.global init_tst
.global tst_start
.global tst_end
.global tst_inits
.global tst_results
.global tst_expects

# -------------------------------------------------------------------------------------------------
tst_misc:

tst_info: .asciz "info text"
tst_header: .asciz "header text"

.set SAVESPR,sprg3
.set MAGIC,0x8675309

# -------------------------------------------------------------------------------------------------
.align 5
tst_inits:

init_r0: .int 0x5EA9536C
init_r1: .int 0x07EC9BA7
init_r2: .int 0xFFFFFFFF
init_r3: .int 0x18FAD811
init_r4: .int 0xFFFFFFFF
init_r5: .int 0xFFFFFFFF
init_r6: .int 0xFFFFFFFF
init_r7: .int 0xFFFFFFFF
init_r8: .int 0xFFFFFFFF
init_r9: .int 0xFFFFFFFF
init_r10: .int 0xB186394A
init_r11: .int 0x07EC9BA7
init_r12: .int 0xFFFFFFFF
init_r13: .int 0xFC9D07CE
init_r14: .int 0x7305868F
init_r15: .int 0xFFFFFFFF
init_r16: .int 0xFFFFFFFF
init_r17: .int 0x6E078D56
init_r18: .int 0xFFFFFFFF
init_r19: .int 0xFFFFFFFF
init_r20: .int 0x0F8F2BB1
init_r21: .int 0xFFFFFFFF
init_r22: .int 0xFFFFFFFF
init_r23: .int 0x9E47F6C0
init_r24: .int 0x46B0FC81
init_r25: .int 0xFFFFFFFF
init_r26: .int 0xFFFFFFFF
init_r27: .int 0x48026438
init_r28: .int 0xEFB046E4
init_r29: .int 0x4B5CBE25
init_r30: .int 0xFFFFFFFF
init_r31: .int 0xFFFFFFFF

init_cr: .int 0xB0215BC8
init_xer: .int 0xBFC0004B
init_ctr: .int 0xF7DA2C8A
init_lr: .int 0x8BC7C22B
init_tar: .int 0xFFFFFFFF
init_msr: .int 0x00001081

init_iar: .int 0x00010000

save_r1: .int 0

codelen: .int 13
ops: .int 0x36E86A7F,0x10748A7F,0x71AE9D7E,0x1C865B55,0xF45EAA7D,0x2000154D,0x50E01B7C,0x4933037B,0x00082B7D,0x36B8317C,0x00000060,0x00000060,0x00000060
iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x0001001C,0x00010020,0x00010024,0x00010028,0x0001002C,0x00010030

# -------------------------------------------------------------------------------------------------
# r3=@tst_inits
.align 5
init_tst:

# save c stuff
stw r1,(save_r1-tst_inits)(r3)

# copy ops
opcopy:
lwz r1,(codelen-tst_inits)(r3)
mtctr r1
opcopy_loop:
la r1,(cops-tst_inits)(r3)
la r2,(iars-tst_inits)(r3)
stw r1,0(r2)
addi r2,r2,4
bdnz opcopy_loop

# init test regs
init_regs:
lwz r1,(init_cr-tst_inits)(r3)
mtcr r1
lwz r1,(init_xer-tst_inits)(r3)
mtxer r1
lwz r1,(init_ctr-tst_inits)(r3)
mtctr r1
lwz r1,(init_lr-tst_inits)(r3)
mtlr r1
lwz r1,(init_tar-tst_inits)(r3)
mtspr tar,r1

lwz r0,(init_r0-tst_inits)(r3)
lwz r1,(init_r1-tst_inits)(r3)
lwz r2,(init_r2-tst_inits)(r3)
lwz r4,(init_r4-tst_inits)(r3)
lwz r5,(init_r5-tst_inits)(r3)
lwz r6,(init_r6-tst_inits)(r3)
lwz r7,(init_r7-tst_inits)(r3)
lwz r8,(init_r8-tst_inits)(r3)
lwz r9,(init_r9-tst_inits)(r3)
lwz r10,(init_r10-tst_inits)(r3)
lwz r11,(init_r11-tst_inits)(r3)
lwz r12,(init_r12-tst_inits)(r3)
lwz r13,(init_r13-tst_inits)(r3)
lwz r14,(init_r14-tst_inits)(r3)
lwz r15,(init_r15-tst_inits)(r3)
lwz r16,(init_r16-tst_inits)(r3)
lwz r17,(init_r17-tst_inits)(r3)
lwz r18,(init_r18-tst_inits)(r3)
lwz r19,(init_r19-tst_inits)(r3)
lwz r20,(init_r20-tst_inits)(r3)
lwz r21,(init_r21-tst_inits)(r3)
lwz r22,(init_r22-tst_inits)(r3)
lwz r23,(init_r23-tst_inits)(r3)
lwz r24,(init_r24-tst_inits)(r3)
lwz r25,(init_r25-tst_inits)(r3)
lwz r26,(init_r26-tst_inits)(r3)
lwz r27,(init_r27-tst_inits)(r3)
lwz r28,(init_r28-tst_inits)(r3)
lwz r29,(init_r29-tst_inits)(r3)
lwz r30,(init_r30-tst_inits)(r3)
lwz r31,(init_r31-tst_inits)(r3)
lwz r3,(init_r3-tst_inits)(r3)

jmp2tst: rfi

# needs to be inserted into epilogue of tst!
#tst_end:
# b save_results

# -------------------------------------------------------------------------------------------------
.align 5
save_results:
# use a designated spr to save (sprgx, ...)
mtspr SAVESPR,r1
lis r1,tst_results@h
ori r1,r1,tst_results@l
stw r0,(rslt_r0-tst_results)(r1)
stw r2,(rslt_r2-tst_results)(r1)
stw r3,(rslt_r3-tst_results)(r1)
stw r4,(rslt_r4-tst_results)(r1)
stw r5,(rslt_r5-tst_results)(r1)
stw r6,(rslt_r6-tst_results)(r1)
stw r7,(rslt_r7-tst_results)(r1)
stw r8,(rslt_r8-tst_results)(r1)
stw r9,(rslt_r9-tst_results)(r1)
stw r10,(rslt_r10-tst_results)(r1)
stw r11,(rslt_r11-tst_results)(r1)
stw r12,(rslt_r12-tst_results)(r1)
stw r13,(rslt_r13-tst_results)(r1)
stw r14,(rslt_r14-tst_results)(r1)
stw r15,(rslt_r15-tst_results)(r1)
stw r16,(rslt_r16-tst_results)(r1)
stw r17,(rslt_r17-tst_results)(r1)
stw r18,(rslt_r18-tst_results)(r1)
stw r19,(rslt_r19-tst_results)(r1)
stw r20,(rslt_r20-tst_results)(r1)
stw r21,(rslt_r21-tst_results)(r1)
stw r22,(rslt_r22-tst_results)(r1)
stw r23,(rslt_r23-tst_results)(r1)
stw r24,(rslt_r24-tst_results)(r1)
stw r25,(rslt_r25-tst_results)(r1)
stw r26,(rslt_r26-tst_results)(r1)
stw r27,(rslt_r27-tst_results)(r1)
stw r28,(rslt_r28-tst_results)(r1)
stw r29,(rslt_r29-tst_results)(r1)
stw r30,(rslt_r30-tst_results)(r1)
stw r31,(rslt_r31-tst_results)(r1)
mfspr r2,SAVESPR
stw r2,(rslt_r1-tst_results)(r1)
mfcr r2
stw r2,(rslt_cr-tst_results)(r1)
mfxer r2
stw r2,(rslt_xer-tst_results)(r1)
mfctr r2
stw r2,(rslt_ctr-tst_results)(r1)
mflr r2
stw r2,(rslt_lr-tst_results)(r1)
mfspr r2,tar
stw r2,(rslt_tar-tst_results)(r1)

tst_cleanup:
# restore c stuff
lis r3,tst_inits@h
ori r3,r3,tst_inits@l
lwz r1,(save_r1-tst_inits)(r3)
lis r3,MAGIC@h
ori r3,r3,MAGIC@l

b tst_done

# -------------------------------------------------------------------------------------------------
.align 5
tst_results:

rslt_r0: .int 0xFFFFFFFF
rslt_r1: .int 0xFFFFFFFF
rslt_r2: .int 0xFFFFFFFF
rslt_r3: .int 0xFFFFFFFF
rslt_r4: .int 0xFFFFFFFF
rslt_r5: .int 0xFFFFFFFF
rslt_r6: .int 0xFFFFFFFF
rslt_r7: .int 0xFFFFFFFF
rslt_r8: .int 0xFFFFFFFF
rslt_r9: .int 0xFFFFFFFF
rslt_r10: .int 0xFFFFFFFF
rslt_r11: .int 0xFFFFFFFF
rslt_r12: .int 0xFFFFFFFF
rslt_r13: .int 0xFFFFFFFF
rslt_r14: .int 0xFFFFFFFF
rslt_r15: .int 0xFFFFFFFF
rslt_r16: .int 0xFFFFFFFF
rslt_r17: .int 0xFFFFFFFF
rslt_r18: .int 0xFFFFFFFF
rslt_r19: .int 0xFFFFFFFF
rslt_r20: .int 0xFFFFFFFF
rslt_r21: .int 0xFFFFFFFF
rslt_r22: .int 0xFFFFFFFF
rslt_r23: .int 0xFFFFFFFF
rslt_r24: .int 0xFFFFFFFF
rslt_r25: .int 0xFFFFFFFF
rslt_r26: .int 0xFFFFFFFF
rslt_r27: .int 0xFFFFFFFF
rslt_r28: .int 0xFFFFFFFF
rslt_r29: .int 0xFFFFFFFF
rslt_r30: .int 0xFFFFFFFF
rslt_r31: .int 0xFFFFFFFF

rslt_cr: .int 0xFFFFFFFF
rslt_xer: .int 0xFFFFFFFF
rslt_ctr: .int 0xFFFFFFFF
rslt_lr: .int 0xFFFFFFFF
rslt_tar: .int 0xFFFFFFFF

# -------------------------------------------------------------------------------------------------
.align 5
tst_expects:

expt_r0: .int 0x7305868F
expt_r1: .int 0x07EC9BA7
expt_r2: .int 0xFFFFFFFF
expt_r3: .int 0xAC3F2040
expt_r4: .int 0xFFFFFFFF
expt_r5: .int 0xFFFFFFFF
expt_r6: .int 0xFFFFFFFF
expt_r7: .int 0xFFFFFFFF
expt_r8: .int 0xFFFFFFFF
expt_r9: .int 0xFFFFFFFF
expt_r10: .int 0xE83E7000
expt_r11: .int 0x07EC9BA7
expt_r12: .int 0xFFFFFFFF
expt_r13: .int 0xFC9D07CE
expt_r14: .int 0x7305868F
expt_r15: .int 0xFFFFFFFF
expt_r16: .int 0xFFFFFFFF
expt_r17: .int 0x00000000
expt_r18: .int 0xFFFFFFFF
expt_r19: .int 0xFFFFFFFF
expt_r20: .int 0x0F8F2BB1
expt_r21: .int 0xFFFFFFFF
expt_r22: .int 0xFFFFFFFF
expt_r23: .int 0x9E47F6C0
expt_r24: .int 0x46B0FC81
expt_r25: .int 0xFFFFFFFF
expt_r26: .int 0xFFFFFFFF
expt_r27: .int 0x00000000
expt_r28: .int 0x7305868F
expt_r29: .int 0x0000007C
expt_r30: .int 0xFFFFFFFF
expt_r31: .int 0xFFFFFFFF

expt_cr: .int 0x90315BC8
expt_xer: .int 0x82C0004B
expt_ctr: .int 0xF7DA2C89
expt_lr: .int 0x8BC7C22B
expt_tar: .int 0xFFFFFFFF
expt_msr: .int 0x00001081

expt_iar: .int 0x00010038

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dev/src/test3_soc/arcitst.lst
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1 # asmtst.tpl
2
3 .include "defines.s"
1 # © IBM Corp. 2020
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 #-----------------------------------------
11 # Defines
12 #-----------------------------------------
13
14 # Regs
15
16 .set r0, 0
17 .set r1, 1
18 .set r2, 2
19 .set r3, 3
20 .set r4, 4
21 .set r5, 5
22 .set r6, 6
23 .set r7, 7
24 .set r8, 8
25 .set r9, 9
26 .set r10,10
27 .set r11,11
28 .set r12,12
29 .set r13,13
30 .set r14,14
31 .set r15,15
32 .set r16,16
33 .set r17,17
34 .set r18,18
35 .set r19,19
36 .set r20,20
37 .set r21,21
38 .set r22,22
39 .set r23,23
40 .set r24,24
41 .set r25,25
42 .set r26,26
43 .set r27,27
44 .set r28,28
45 .set r29,29
46 .set r30,30
47 .set r31,31
48
49 .set f0, 0
50 .set f1, 1
51 .set f2, 2
52 .set f3, 3
53 .set f4, 4
54 .set f5, 5
55 .set f6, 6
56 .set f7, 7
57 .set f8, 8
58 .set f9, 9
59 .set f10,10
60 .set f11,11
61 .set f12,12
62 .set f13,13
63 .set f14,14
64 .set f15,15
65 .set f16,16
66 .set f17,17
67 .set f18,18
68 .set f19,19
69 .set f20,20
70 .set f21,21
71 .set f22,22
72 .set f23,23
73 .set f24,24
74 .set f25,25
75 .set f26,26
76 .set f27,27
77 .set f28,28
78 .set f29,29
79 .set f30,30
80 .set f31,31
81
82 .set cr0, 0
83 .set cr1, 1
84 .set cr2, 2
85 .set cr3, 3
86 .set cr4, 4
87 .set cr5, 5
88 .set cr6, 6
89 .set cr7, 7
90
91 # SPR numbers
92
93 .set srr0, 26
94 .set srr1, 27
95 .set dar, 19
96 .set dsisr, 18
97 .set epcr, 307
98 .set tar, 815
99
100 .set dbsr, 304
101 .set dbcr0, 308
102 .set dbcr1, 309
103 .set dbcr2, 310
104 .set dbcr3, 848
105
106 .set ivpr, 63
107
108 .set iucr0, 1011
109 .set iucr1, 883
110 .set iucr2, 884
111
112 .set iudbg0, 888
113 .set iudbg1, 889
114 .set iudbg2, 890
115 .set iulfsr, 891
116 .set iullcr, 892
117
118 .set mmucr0, 1020
119 .set mmucr1, 1021
120 .set mmucr2, 1022
121 .set mmucr3, 1023
122
123 .set tb, 268
124 .set tbl, 284
125 .set tbh, 285
126
127 .set dec, 22
128 .set udec, 550
129 .set tsr, 336
130 .set tcr, 340
131
132 .set xucr0, 1014
133 .set xucr1, 851
134 .set xucr2, 1016
135 .set xucr3, 852
136 .set xucr4, 853
137
138 .set tens, 438
139 .set tenc, 439
140 .set tensr, 437
141
142 .set pid, 48
143 .set pir, 286
144 .set pvr, 287
145 .set tir, 446
146
147 #.set sprg0,
148 #.set sprg1,
149 #.set sprg2,
150 .set sprg3, 259
4
5 # -------------------------------------------------------------------------------------------------
6 # c-accessible
7
8 .global init_tst
9 .global tst_start
10 .global tst_end
11 .global tst_inits
12 .global tst_results
13 .global tst_expects
14
15 # -------------------------------------------------------------------------------------------------
16 tst_misc:
17
18 0000 696E666F tst_info: .asciz "info text"
18 20746578
18 7400
19 000a 68656164 tst_header: .asciz "header text"
19 65722074
19 65787400
20
21 .set SAVESPR,tar
22 .set MAGIC,0x8675309
23
24 # -------------------------------------------------------------------------------------------------
25 0016 00000000 .align 5
25 00000000
25 0000
26 tst_inits:
27
28 0020 00000000 init_r0: .int 0x00000000
29 0024 5822C905 init_r1: .int 0x5822C905
30 0028 FFFFFFFF init_r2: .int 0xFFFFFFFF
31 002c 91B6D1A3 init_r3: .int 0x91B6D1A3
32 0030 FFFFFFFF init_r4: .int 0xFFFFFFFF
33 0034 FFFFFFFF init_r5: .int 0xFFFFFFFF
34 0038 FFFFFFFF init_r6: .int 0xFFFFFFFF
35 003c FFFFFFFF init_r7: .int 0xFFFFFFFF
36 0040 FFFFFFFF init_r8: .int 0xFFFFFFFF
37 0044 7E11EE88 init_r9: .int 0x7E11EE88
38 0048 FFFFFFFF init_r10: .int 0xFFFFFFFF
39 004c 7FFFFFFF init_r11: .int 0x7FFFFFFF
40 0050 FFFFFFFF init_r12: .int 0xFFFFFFFF
41 0054 FFFFFFFF init_r13: .int 0xFFFFFFFF
42 0058 8C20BDE6 init_r14: .int 0x8C20BDE6
43 005c FFFFFFFF init_r15: .int 0xFFFFFFFF
44 0060 76D0DADF init_r16: .int 0x76D0DADF
45 0064 15111F42 init_r17: .int 0x15111F42
46 0068 FFFFFFFF init_r18: .int 0xFFFFFFFF
47 006c 36108E50 init_r19: .int 0x36108E50
48 0070 FFFFFFFF init_r20: .int 0xFFFFFFFF
49 0074 FFFFFFFF init_r21: .int 0xFFFFFFFF
50 0078 328A0CED init_r22: .int 0x328A0CED
51 007c FFFFFFFF init_r23: .int 0xFFFFFFFF
52 0080 FFFFFFFF init_r24: .int 0xFFFFFFFF
53 0084 AF224C19 init_r25: .int 0xAF224C19
54 0088 FFFFFFFF init_r26: .int 0xFFFFFFFF
55 008c FFFFFFFF init_r27: .int 0xFFFFFFFF
56 0090 D624B27A init_r28: .int 0xD624B27A
57 0094 FFFFFFFF init_r29: .int 0xFFFFFFFF
58 0098 FFFFFFFF init_r30: .int 0xFFFFFFFF
59 009c FFFFFFFF init_r31: .int 0xFFFFFFFF
60
61 00a0 DBFD3628 init_cr: .int 0xDBFD3628
62 00a4 89F0006E init_xer: .int 0x89F0006E
63 00a8 FFFFFFFF init_ctr: .int 0xFFFFFFFF
64 00ac FFFFFFFF init_lr: .int 0xFFFFFFFF
65 00b0 FFFFFFFF init_tar: .int 0xFFFFFFFF
66 00b4 00001104 init_msr: .int 0x00001104
67
68 00b8 00010000 init_iar: .int 0x00010000
69
70 00bc 00000000 save_r1: .int 0
71
72 00c0 0000000D codelen: .int 13
73 00c4 7C61CC14 ops: .int 0x7C61CC14,0x7D230595,0x7AC37392,0x7E094C11,0x7E1CB115,0x7A338886,0x7C6004D1,0x
73 7D230595
73 7AC37392
73 7E094C11
73 7E1CB115
74 00f8 00010000 iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x
74 00010004
74 00010008
74 0001000C
74 00010010
75
76 # -------------------------------------------------------------------------------------------------
77 # r3=@tst_inits
78 012c 48000014 .align 5
78 60000000
78 60000000
78 60000000
78 60000000
79 init_tst:
80
81 # save c stuff
82 0140 9023009C stw r1,(save_r1-tst_inits)(r3)
83
84 # copy ops
85 opcopy:
86 0144 802300A0 lwz r1,(codelen-tst_inits)(r3)
87 0148 7C2903A6 mtctr r1
88 014c 382300A4 la r1,(ops-tst_inits)(r3) # @ ops list
89 0150 384300D8 la r2,(iars-tst_inits)(r3) # @ iars list
90 opcopy_loop:
91 0154 80810000 lwz r4,0(r1) # next op
92 0158 80A20000 lwz r5,0(r2) # next iar
93 015c 90850000 stw r4,0(r5) # store it
94 0160 38210004 addi r1,r1,4 # inc to next
95 0164 38420004 addi r2,r2,4
96 0168 4200FFEC bdnz opcopy_loop
97
98 # add end of test op - could be done here or by builder
99 # ways to end:
100 # ba <fixed_loc> - avoid reloc, target op can then branch to tst_end
101 # trap,sc,scv - branch to tst_end in handler
102 # attn, priv op, etc. - "
103 # overwrite the last epilogue op to avoid any crossing
104 opcopy_eot:
105 016c 3C804800 lis r4,0x4800
106 0170 60840006 ori r4,r4,0x0006 # ba 0x0004
107 0174 90850000 stw r4,0(r5)
108
109 # get tst start
110 0178 80230094 lwz r1,(init_msr-tst_inits)(r3)
111 017c 7C3B03A6 mtsrr1 r1
112 0180 80230098 lwz r1,(init_iar-tst_inits)(r3)
113 0184 7C3A03A6 mtsrr0 r1
114
115 # init test regs
116 init_regs:
117 0188 80230080 lwz r1,(init_cr-tst_inits)(r3)
118 018c 7C2FF120 mtcr r1
119 0190 80230084 lwz r1,(init_xer-tst_inits)(r3)
120 0194 7C2103A6 mtxer r1
121 0198 80230088 lwz r1,(init_ctr-tst_inits)(r3)
122 019c 7C2903A6 mtctr r1
123 01a0 8023008C lwz r1,(init_lr-tst_inits)(r3)
124 01a4 7C2803A6 mtlr r1
125 01a8 80230090 lwz r1,(init_tar-tst_inits)(r3)
126 01ac 7C2FCBA6 mtspr tar,r1
127
128 01b0 80030000 lwz r0,(init_r0-tst_inits)(r3)
129 01b4 80230004 lwz r1,(init_r1-tst_inits)(r3)
130 01b8 80430008 lwz r2,(init_r2-tst_inits)(r3)
131 01bc 80830010 lwz r4,(init_r4-tst_inits)(r3)
132 01c0 80A30014 lwz r5,(init_r5-tst_inits)(r3)
133 01c4 80C30018 lwz r6,(init_r6-tst_inits)(r3)
134 01c8 80E3001C lwz r7,(init_r7-tst_inits)(r3)
135 01cc 81030020 lwz r8,(init_r8-tst_inits)(r3)
136 01d0 81230024 lwz r9,(init_r9-tst_inits)(r3)
137 01d4 81430028 lwz r10,(init_r10-tst_inits)(r3)
138 01d8 8163002C lwz r11,(init_r11-tst_inits)(r3)
139 01dc 81830030 lwz r12,(init_r12-tst_inits)(r3)
140 01e0 81A30034 lwz r13,(init_r13-tst_inits)(r3)
141 01e4 81C30038 lwz r14,(init_r14-tst_inits)(r3)
142 01e8 81E3003C lwz r15,(init_r15-tst_inits)(r3)
143 01ec 82030040 lwz r16,(init_r16-tst_inits)(r3)
144 01f0 82230044 lwz r17,(init_r17-tst_inits)(r3)
145 01f4 82430048 lwz r18,(init_r18-tst_inits)(r3)
146 01f8 8263004C lwz r19,(init_r19-tst_inits)(r3)
147 01fc 82830050 lwz r20,(init_r20-tst_inits)(r3)
148 0200 82A30054 lwz r21,(init_r21-tst_inits)(r3)
149 0204 82C30058 lwz r22,(init_r22-tst_inits)(r3)
150 0208 82E3005C lwz r23,(init_r23-tst_inits)(r3)
151 020c 83030060 lwz r24,(init_r24-tst_inits)(r3)
152 0210 83230064 lwz r25,(init_r25-tst_inits)(r3)
153 0214 83430068 lwz r26,(init_r26-tst_inits)(r3)
154 0218 8363006C lwz r27,(init_r27-tst_inits)(r3)
155 021c 83830070 lwz r28,(init_r28-tst_inits)(r3)
156 0220 83A30074 lwz r29,(init_r29-tst_inits)(r3)
157 0224 83C30078 lwz r30,(init_r30-tst_inits)(r3)
158 0228 83E3007C lwz r31,(init_r31-tst_inits)(r3)
159 022c 8063000C lwz r3,(init_r3-tst_inits)(r3)
160
161 jmp2tst:
162 0230 4C000064 rfi
163 #rfid
164 #ba 0x10000
165
166 tst_end:
167 0234 4800000C b save_results
168
169 # -------------------------------------------------------------------------------------------------
170 0238 60000000 .align 5
170 60000000
171 save_results:
172 # use a designated spr to save (sprgx, ...)
173 0240 7C2FCBA6 mtspr SAVESPR,r1
174 0244 3C200000 lis r1,tst_results@h
175 0248 60210000 ori r1,r1,tst_results@l
176 024c 90010000 stw r0,(rslt_r0-tst_results)(r1)
177 0250 90410008 stw r2,(rslt_r2-tst_results)(r1)
178 0254 9061000C stw r3,(rslt_r3-tst_results)(r1)
179 0258 90810010 stw r4,(rslt_r4-tst_results)(r1)
180 025c 90A10014 stw r5,(rslt_r5-tst_results)(r1)
181 0260 90C10018 stw r6,(rslt_r6-tst_results)(r1)
182 0264 90E1001C stw r7,(rslt_r7-tst_results)(r1)
183 0268 91010020 stw r8,(rslt_r8-tst_results)(r1)
184 026c 91210024 stw r9,(rslt_r9-tst_results)(r1)
185 0270 91410028 stw r10,(rslt_r10-tst_results)(r1)
186 0274 9161002C stw r11,(rslt_r11-tst_results)(r1)
187 0278 91810030 stw r12,(rslt_r12-tst_results)(r1)
188 027c 91A10034 stw r13,(rslt_r13-tst_results)(r1)
189 0280 91C10038 stw r14,(rslt_r14-tst_results)(r1)
190 0284 91E1003C stw r15,(rslt_r15-tst_results)(r1)
191 0288 92010040 stw r16,(rslt_r16-tst_results)(r1)
192 028c 92210044 stw r17,(rslt_r17-tst_results)(r1)
193 0290 92410048 stw r18,(rslt_r18-tst_results)(r1)
194 0294 9261004C stw r19,(rslt_r19-tst_results)(r1)
195 0298 92810050 stw r20,(rslt_r20-tst_results)(r1)
196 029c 92A10054 stw r21,(rslt_r21-tst_results)(r1)
197 02a0 92C10058 stw r22,(rslt_r22-tst_results)(r1)
198 02a4 92E1005C stw r23,(rslt_r23-tst_results)(r1)
199 02a8 93010060 stw r24,(rslt_r24-tst_results)(r1)
200 02ac 93210064 stw r25,(rslt_r25-tst_results)(r1)
201 02b0 93410068 stw r26,(rslt_r26-tst_results)(r1)
202 02b4 9361006C stw r27,(rslt_r27-tst_results)(r1)
203 02b8 93810070 stw r28,(rslt_r28-tst_results)(r1)
204 02bc 93A10074 stw r29,(rslt_r29-tst_results)(r1)
205 02c0 93C10078 stw r30,(rslt_r30-tst_results)(r1)
206 02c4 93E1007C stw r31,(rslt_r31-tst_results)(r1)
207 02c8 7C4FCAA6 mfspr r2,SAVESPR
208 02cc 90410004 stw r2,(rslt_r1-tst_results)(r1)
209 02d0 7C400026 mfcr r2
210 02d4 90410080 stw r2,(rslt_cr-tst_results)(r1)
211 02d8 7C4102A6 mfxer r2
212 02dc 90410084 stw r2,(rslt_xer-tst_results)(r1)
213 02e0 7C4902A6 mfctr r2
214 02e4 90410088 stw r2,(rslt_ctr-tst_results)(r1)
215 02e8 7C4802A6 mflr r2
216 02ec 9041008C stw r2,(rslt_lr-tst_results)(r1)
217 02f0 7C4FCAA6 mfspr r2,tar
218 02f4 90410090 stw r2,(rslt_tar-tst_results)(r1)
219
220 tst_cleanup:
221 # restore c stuff
222 02f8 3C600000 lis r3,tst_inits@h
223 02fc 60630000 ori r3,r3,tst_inits@l
224 0300 8023009C lwz r1,(save_r1-tst_inits)(r3)
225 0304 3C600867 lis r3,MAGIC@h
226 0308 60635309 ori r3,r3,MAGIC@l
227
228 030c 48000003 bla tst_done
229
230 # -------------------------------------------------------------------------------------------------
231 0310 60000000 .align 5
231 60000000
231 60000000
231 60000000
232 tst_results:
233
234 0320 FFFFFFFF rslt_r0: .int 0xFFFFFFFF
235 0324 FFFFFFFF rslt_r1: .int 0xFFFFFFFF
236 0328 FFFFFFFF rslt_r2: .int 0xFFFFFFFF
237 032c FFFFFFFF rslt_r3: .int 0xFFFFFFFF
238 0330 FFFFFFFF rslt_r4: .int 0xFFFFFFFF
239 0334 FFFFFFFF rslt_r5: .int 0xFFFFFFFF
240 0338 FFFFFFFF rslt_r6: .int 0xFFFFFFFF
241 033c FFFFFFFF rslt_r7: .int 0xFFFFFFFF
242 0340 FFFFFFFF rslt_r8: .int 0xFFFFFFFF
243 0344 FFFFFFFF rslt_r9: .int 0xFFFFFFFF
244 0348 FFFFFFFF rslt_r10: .int 0xFFFFFFFF
245 034c FFFFFFFF rslt_r11: .int 0xFFFFFFFF
246 0350 FFFFFFFF rslt_r12: .int 0xFFFFFFFF
247 0354 FFFFFFFF rslt_r13: .int 0xFFFFFFFF
248 0358 FFFFFFFF rslt_r14: .int 0xFFFFFFFF
249 035c FFFFFFFF rslt_r15: .int 0xFFFFFFFF
250 0360 FFFFFFFF rslt_r16: .int 0xFFFFFFFF
251 0364 FFFFFFFF rslt_r17: .int 0xFFFFFFFF
252 0368 FFFFFFFF rslt_r18: .int 0xFFFFFFFF
253 036c FFFFFFFF rslt_r19: .int 0xFFFFFFFF
254 0370 FFFFFFFF rslt_r20: .int 0xFFFFFFFF
255 0374 FFFFFFFF rslt_r21: .int 0xFFFFFFFF
256 0378 FFFFFFFF rslt_r22: .int 0xFFFFFFFF
257 037c FFFFFFFF rslt_r23: .int 0xFFFFFFFF
258 0380 FFFFFFFF rslt_r24: .int 0xFFFFFFFF
259 0384 FFFFFFFF rslt_r25: .int 0xFFFFFFFF
260 0388 FFFFFFFF rslt_r26: .int 0xFFFFFFFF
261 038c FFFFFFFF rslt_r27: .int 0xFFFFFFFF
262 0390 FFFFFFFF rslt_r28: .int 0xFFFFFFFF
263 0394 FFFFFFFF rslt_r29: .int 0xFFFFFFFF
264 0398 FFFFFFFF rslt_r30: .int 0xFFFFFFFF
265 039c FFFFFFFF rslt_r31: .int 0xFFFFFFFF
266
267 03a0 FFFFFFFF rslt_cr: .int 0xFFFFFFFF
268 03a4 FFFFFFFF rslt_xer: .int 0xFFFFFFFF
269 03a8 FFFFFFFF rslt_ctr: .int 0xFFFFFFFF
270 03ac FFFFFFFF rslt_lr: .int 0xFFFFFFFF
271 03b0 FFFFFFFF rslt_tar: .int 0xFFFFFFFF
272
273 # -------------------------------------------------------------------------------------------------
274 03b4 60000000 .align 5
274 60000000
274 60000000
275 tst_expects:
276
277 03c0 00000000 expt_r0: .int 0x00000000
278 03c4 CD75F313 expt_r1: .int 0xCD75F313
279 03c8 FFFFFFFF expt_r2: .int 0xFFFFFFFF
280 03cc 00000000 expt_r3: .int 0x00000000
281 03d0 FFFFFFFF expt_r4: .int 0xFFFFFFFF
282 03d4 FFFFFFFF expt_r5: .int 0xFFFFFFFF
283 03d8 FFFFFFFF expt_r6: .int 0xFFFFFFFF
284 03dc FFFFFFFF expt_r7: .int 0xFFFFFFFF
285 03e0 FFFFFFFF expt_r8: .int 0xFFFFFFFF
286 03e4 008A0C68 expt_r9: .int 0x008A0C68
287 03e8 FFFFFFFF expt_r10: .int 0xFFFFFFFF
288 03ec 7FFFFFFF expt_r11: .int 0x7FFFFFFF
289 03f0 FFFFFFFF expt_r12: .int 0xFFFFFFFF
290 03f4 FFFFFFFF expt_r13: .int 0xFFFFFFFF
291 03f8 8C20BDE6 expt_r14: .int 0x8C20BDE6
292 03fc FFFFFFFF expt_r15: .int 0xFFFFFFFF
293 0400 08AEBF68 expt_r16: .int 0x08AEBF68
294 0404 80000001 expt_r17: .int 0x80000001
295 0408 FFFFFFFF expt_r18: .int 0xFFFFFFFF
296 040c 00000000 expt_r19: .int 0x00000000
297 0410 FFFFFFFF expt_r20: .int 0xFFFFFFFF
298 0414 FFFFFFFF expt_r21: .int 0xFFFFFFFF
299 0418 328A0CED expt_r22: .int 0x328A0CED
300 041c FFFFFFFF expt_r23: .int 0xFFFFFFFF
301 0420 FFFFFFFF expt_r24: .int 0xFFFFFFFF
302 0424 AF224C19 expt_r25: .int 0xAF224C19
303 0428 FFFFFFFF expt_r26: .int 0xFFFFFFFF
304 042c FFFFFFFF expt_r27: .int 0xFFFFFFFF
305 0430 D624B27A expt_r28: .int 0xD624B27A
306 0434 FFFFFFFF expt_r29: .int 0xFFFFFFFF
307 0438 FFFFFFFF expt_r30: .int 0xFFFFFFFF
308 043c FFFFFFFF expt_r31: .int 0xFFFFFFFF
309
310 0440 9BFD3628 expt_cr: .int 0x9BFD3628
311 0444 98F0006E expt_xer: .int 0x98F0006E
312 0448 FFFFFFFF expt_ctr: .int 0xFFFFFFFF
313 044c FFFFFFFF expt_lr: .int 0xFFFFFFFF
314 0450 FFFFFFFF expt_tar: .int 0xFFFFFFFF
315 0454 00001104 expt_msr: .int 0x00001104
316
317 0458 00010038 expt_iar: .int 0x00010038
318

318
dev/src/test3_soc/arcitst.s
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# asmtst.tpl

.include "defines.s"

# -------------------------------------------------------------------------------------------------
# c-accessible

.global init_tst
.global tst_start
.global tst_end
.global tst_inits
.global tst_results
.global tst_expects

# -------------------------------------------------------------------------------------------------
tst_misc:

tst_info: .asciz "info text"
tst_header: .asciz "header text"

.set SAVESPR,tar
.set MAGIC,0x8675309

# -------------------------------------------------------------------------------------------------
.align 5
tst_inits:

init_r0: .int 0x00000000
init_r1: .int 0x5822C905
init_r2: .int 0xFFFFFFFF
init_r3: .int 0x91B6D1A3
init_r4: .int 0xFFFFFFFF
init_r5: .int 0xFFFFFFFF
init_r6: .int 0xFFFFFFFF
init_r7: .int 0xFFFFFFFF
init_r8: .int 0xFFFFFFFF
init_r9: .int 0x7E11EE88
init_r10: .int 0xFFFFFFFF
init_r11: .int 0x7FFFFFFF
init_r12: .int 0xFFFFFFFF
init_r13: .int 0xFFFFFFFF
init_r14: .int 0x8C20BDE6
init_r15: .int 0xFFFFFFFF
init_r16: .int 0x76D0DADF
init_r17: .int 0x15111F42
init_r18: .int 0xFFFFFFFF
init_r19: .int 0x36108E50
init_r20: .int 0xFFFFFFFF
init_r21: .int 0xFFFFFFFF
init_r22: .int 0x328A0CED
init_r23: .int 0xFFFFFFFF
init_r24: .int 0xFFFFFFFF
init_r25: .int 0xAF224C19
init_r26: .int 0xFFFFFFFF
init_r27: .int 0xFFFFFFFF
init_r28: .int 0xD624B27A
init_r29: .int 0xFFFFFFFF
init_r30: .int 0xFFFFFFFF
init_r31: .int 0xFFFFFFFF

init_cr: .int 0xDBFD3628
init_xer: .int 0x89F0006E
init_ctr: .int 0xFFFFFFFF
init_lr: .int 0xFFFFFFFF
init_tar: .int 0xFFFFFFFF
init_msr: .int 0x00001104

init_iar: .int 0x00010000

save_r1: .int 0

codelen: .int 13
ops: .int 0x7C61CC14,0x7D230595,0x7AC37392,0x7E094C11,0x7E1CB115,0x7A338886,0x7C6004D1,0x7E09B038,0x7C360591,0x7E2B00D1,0x60000000,0x60000000,0x60000000
iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x0001001C,0x00010020,0x00010024,0x00010028,0x0001002C,0x00010030

# -------------------------------------------------------------------------------------------------
# r3=@tst_inits
.align 5
init_tst:

# save c stuff
stw r1,(save_r1-tst_inits)(r3)

# copy ops
opcopy:
lwz r1,(codelen-tst_inits)(r3)
mtctr r1
la r1,(ops-tst_inits)(r3) # @ ops list
la r2,(iars-tst_inits)(r3) # @ iars list
opcopy_loop:
lwz r4,0(r1) # next op
lwz r5,0(r2) # next iar
stw r4,0(r5) # store it
addi r1,r1,4 # inc to next
addi r2,r2,4
bdnz opcopy_loop

# add end of test op - could be done here or by builder
# ways to end:
# ba <fixed_loc> - avoid reloc, target op can then branch to tst_end
# trap,sc,scv - branch to tst_end in handler
# attn, priv op, etc. - "
# overwrite the last epilogue op to avoid any crossing
opcopy_eot:
lis r4,0x4800
ori r4,r4,0x0006 # ba 0x0004
stw r4,0(r5)

# get tst start
lwz r1,(init_msr-tst_inits)(r3)
mtsrr1 r1
lwz r1,(init_iar-tst_inits)(r3)
mtsrr0 r1

# init test regs
init_regs:
lwz r1,(init_cr-tst_inits)(r3)
mtcr r1
lwz r1,(init_xer-tst_inits)(r3)
mtxer r1
lwz r1,(init_ctr-tst_inits)(r3)
mtctr r1
lwz r1,(init_lr-tst_inits)(r3)
mtlr r1
lwz r1,(init_tar-tst_inits)(r3)
mtspr tar,r1

lwz r0,(init_r0-tst_inits)(r3)
lwz r1,(init_r1-tst_inits)(r3)
lwz r2,(init_r2-tst_inits)(r3)
lwz r4,(init_r4-tst_inits)(r3)
lwz r5,(init_r5-tst_inits)(r3)
lwz r6,(init_r6-tst_inits)(r3)
lwz r7,(init_r7-tst_inits)(r3)
lwz r8,(init_r8-tst_inits)(r3)
lwz r9,(init_r9-tst_inits)(r3)
lwz r10,(init_r10-tst_inits)(r3)
lwz r11,(init_r11-tst_inits)(r3)
lwz r12,(init_r12-tst_inits)(r3)
lwz r13,(init_r13-tst_inits)(r3)
lwz r14,(init_r14-tst_inits)(r3)
lwz r15,(init_r15-tst_inits)(r3)
lwz r16,(init_r16-tst_inits)(r3)
lwz r17,(init_r17-tst_inits)(r3)
lwz r18,(init_r18-tst_inits)(r3)
lwz r19,(init_r19-tst_inits)(r3)
lwz r20,(init_r20-tst_inits)(r3)
lwz r21,(init_r21-tst_inits)(r3)
lwz r22,(init_r22-tst_inits)(r3)
lwz r23,(init_r23-tst_inits)(r3)
lwz r24,(init_r24-tst_inits)(r3)
lwz r25,(init_r25-tst_inits)(r3)
lwz r26,(init_r26-tst_inits)(r3)
lwz r27,(init_r27-tst_inits)(r3)
lwz r28,(init_r28-tst_inits)(r3)
lwz r29,(init_r29-tst_inits)(r3)
lwz r30,(init_r30-tst_inits)(r3)
lwz r31,(init_r31-tst_inits)(r3)
lwz r3,(init_r3-tst_inits)(r3)

jmp2tst:
rfi
#rfid
#ba 0x10000

tst_end:
b save_results

# -------------------------------------------------------------------------------------------------
.align 5
save_results:
# use a designated spr to save (sprgx, ...)
mtspr SAVESPR,r1
lis r1,tst_results@h
ori r1,r1,tst_results@l
stw r0,(rslt_r0-tst_results)(r1)
stw r2,(rslt_r2-tst_results)(r1)
stw r3,(rslt_r3-tst_results)(r1)
stw r4,(rslt_r4-tst_results)(r1)
stw r5,(rslt_r5-tst_results)(r1)
stw r6,(rslt_r6-tst_results)(r1)
stw r7,(rslt_r7-tst_results)(r1)
stw r8,(rslt_r8-tst_results)(r1)
stw r9,(rslt_r9-tst_results)(r1)
stw r10,(rslt_r10-tst_results)(r1)
stw r11,(rslt_r11-tst_results)(r1)
stw r12,(rslt_r12-tst_results)(r1)
stw r13,(rslt_r13-tst_results)(r1)
stw r14,(rslt_r14-tst_results)(r1)
stw r15,(rslt_r15-tst_results)(r1)
stw r16,(rslt_r16-tst_results)(r1)
stw r17,(rslt_r17-tst_results)(r1)
stw r18,(rslt_r18-tst_results)(r1)
stw r19,(rslt_r19-tst_results)(r1)
stw r20,(rslt_r20-tst_results)(r1)
stw r21,(rslt_r21-tst_results)(r1)
stw r22,(rslt_r22-tst_results)(r1)
stw r23,(rslt_r23-tst_results)(r1)
stw r24,(rslt_r24-tst_results)(r1)
stw r25,(rslt_r25-tst_results)(r1)
stw r26,(rslt_r26-tst_results)(r1)
stw r27,(rslt_r27-tst_results)(r1)
stw r28,(rslt_r28-tst_results)(r1)
stw r29,(rslt_r29-tst_results)(r1)
stw r30,(rslt_r30-tst_results)(r1)
stw r31,(rslt_r31-tst_results)(r1)
mfspr r2,SAVESPR
stw r2,(rslt_r1-tst_results)(r1)
mfcr r2
stw r2,(rslt_cr-tst_results)(r1)
mfxer r2
stw r2,(rslt_xer-tst_results)(r1)
mfctr r2
stw r2,(rslt_ctr-tst_results)(r1)
mflr r2
stw r2,(rslt_lr-tst_results)(r1)
mfspr r2,tar
stw r2,(rslt_tar-tst_results)(r1)

tst_cleanup:
# restore c stuff
lis r3,tst_inits@h
ori r3,r3,tst_inits@l
lwz r1,(save_r1-tst_inits)(r3)
lis r3,MAGIC@h
ori r3,r3,MAGIC@l

bla tst_done

# -------------------------------------------------------------------------------------------------
.align 5
tst_results:

rslt_r0: .int 0xFFFFFFFF
rslt_r1: .int 0xFFFFFFFF
rslt_r2: .int 0xFFFFFFFF
rslt_r3: .int 0xFFFFFFFF
rslt_r4: .int 0xFFFFFFFF
rslt_r5: .int 0xFFFFFFFF
rslt_r6: .int 0xFFFFFFFF
rslt_r7: .int 0xFFFFFFFF
rslt_r8: .int 0xFFFFFFFF
rslt_r9: .int 0xFFFFFFFF
rslt_r10: .int 0xFFFFFFFF
rslt_r11: .int 0xFFFFFFFF
rslt_r12: .int 0xFFFFFFFF
rslt_r13: .int 0xFFFFFFFF
rslt_r14: .int 0xFFFFFFFF
rslt_r15: .int 0xFFFFFFFF
rslt_r16: .int 0xFFFFFFFF
rslt_r17: .int 0xFFFFFFFF
rslt_r18: .int 0xFFFFFFFF
rslt_r19: .int 0xFFFFFFFF
rslt_r20: .int 0xFFFFFFFF
rslt_r21: .int 0xFFFFFFFF
rslt_r22: .int 0xFFFFFFFF
rslt_r23: .int 0xFFFFFFFF
rslt_r24: .int 0xFFFFFFFF
rslt_r25: .int 0xFFFFFFFF
rslt_r26: .int 0xFFFFFFFF
rslt_r27: .int 0xFFFFFFFF
rslt_r28: .int 0xFFFFFFFF
rslt_r29: .int 0xFFFFFFFF
rslt_r30: .int 0xFFFFFFFF
rslt_r31: .int 0xFFFFFFFF

rslt_cr: .int 0xFFFFFFFF
rslt_xer: .int 0xFFFFFFFF
rslt_ctr: .int 0xFFFFFFFF
rslt_lr: .int 0xFFFFFFFF
rslt_tar: .int 0xFFFFFFFF

# -------------------------------------------------------------------------------------------------
.align 5
tst_expects:

expt_r0: .int 0x00000000
expt_r1: .int 0xCD75F313
expt_r2: .int 0xFFFFFFFF
expt_r3: .int 0x00000000
expt_r4: .int 0xFFFFFFFF
expt_r5: .int 0xFFFFFFFF
expt_r6: .int 0xFFFFFFFF
expt_r7: .int 0xFFFFFFFF
expt_r8: .int 0xFFFFFFFF
expt_r9: .int 0x008A0C68
expt_r10: .int 0xFFFFFFFF
expt_r11: .int 0x7FFFFFFF
expt_r12: .int 0xFFFFFFFF
expt_r13: .int 0xFFFFFFFF
expt_r14: .int 0x8C20BDE6
expt_r15: .int 0xFFFFFFFF
expt_r16: .int 0x08AEBF68
expt_r17: .int 0x80000001
expt_r18: .int 0xFFFFFFFF
expt_r19: .int 0x00000000
expt_r20: .int 0xFFFFFFFF
expt_r21: .int 0xFFFFFFFF
expt_r22: .int 0x328A0CED
expt_r23: .int 0xFFFFFFFF
expt_r24: .int 0xFFFFFFFF
expt_r25: .int 0xAF224C19
expt_r26: .int 0xFFFFFFFF
expt_r27: .int 0xFFFFFFFF
expt_r28: .int 0xD624B27A
expt_r29: .int 0xFFFFFFFF
expt_r30: .int 0xFFFFFFFF
expt_r31: .int 0xFFFFFFFF

expt_cr: .int 0x9BFD3628
expt_xer: .int 0x98F0006E
expt_ctr: .int 0xFFFFFFFF
expt_lr: .int 0xFFFFFFFF
expt_tar: .int 0xFFFFFFFF
expt_msr: .int 0x00001104

expt_iar: .int 0x00010038

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../bin

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dev/src/test3_soc/bios.c
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#include <stdint.h>
#include <stdio.h>

#include "bios.h"

#ifdef PRINTF
#include "liblitex.h"

//static char printbuf[1000]; // make this a pointer with address a define
//const char* printbuf = (char *)0x12000;
#ifndef PRINTBUF
#define PRINTBUF 0x0001C000
#endif
//static int printbuf_ptr = 0;
static char *printbuf_ptr = (char *)PRINTBUF;
//wtf needs smt
void putchar_handler(char c) {
//printbuf[printbuf_ptr++] = c;
//*(printbuf + printbuf_ptr++) = c;
*printbuf_ptr++ = c;
}
#endif

// arci stuff
//void tst_done(unsigned int rc);
void tst_done(unsigned int rc);

// in kernel (for constant locs)
extern void tst_pass(void);
extern void tst_fail(int i);
/*
void tst_pass(void);
void tst_fail(int i);

void tst_fail(int i) {
while(1) {}
}

void tst_pass(void) {
while(1) {}
}
*/

//inline unsigned int checkResult(unsigned int r) __attribute__((always_inline));
unsigned int checkResult(unsigned int r);

extern unsigned int tst_start;
extern unsigned int tst_end;
extern unsigned int tst_inits;
extern unsigned int tst_results;
extern unsigned int tst_expects;

int main(int tid) {
int *p;
int *fdata = &_fdata;
unsigned int *inits = &tst_inits;

if (tid != 0) {
return -1;
}

// r/w memory init

// copy
for (p = &_fdata_rom; p < &_edata_rom; p++){
*(fdata++) = *p;
}
// zero
for (p = &_fbss; p < &_ebss; p++) {
*(p++) = 0;
}

#ifdef PRINTF
console_set_write_hook(putchar_handler);
putchar('w');
putchar('t');
putchar('f');
putchar('\n');
printf("main(%i)\n", tid);
#endif

// core init
set_epcr(0x03000000); // icm=gicm=1
set_dec(0);
set_tbh(0);
set_tbl(0);
set_tsr(0xFE000000); // mask: clear enw,wis,wrs,dis,fis,udis
set_xucr0(get_xucr0() & ~0x00000200); // set tcs=0
set_tsr(0);
set_tcr(0); // disable all timers

// thread enable
// set_tens(0x3);

// run a .tst
// danger! once r1 is whacked, any c code like bad int handler, etc. needs
// to make sure it has a safe stack for calls
asm (
"mr 3,%0\n"
//"lis 4,init_tst@h\n"
//"ori 4,4,init_tst@l\n"
//"mtctr 4\n"
//"bcctr\n"
"b init_tst\n"
: // outputs
: "r"(inits) // inputs
: "r3" // clobbers
);

while(1) {}
return 0;
}

#define MAGIC 0x08675309

// r1 has been restored to where it was for 'b init_tst' above
void tst_done(unsigned int rc) {
unsigned int i, ok = 1;
unsigned int act, exp;

if (rc != MAGIC) {
tst_fail(0x80000000);
}

// check GPR & CR
for (i = 0; i < 32; i++) {
act = *(&tst_results + i);
exp = *(&tst_expects + i);
ok = ok && (act == exp);
if (!ok) {
tst_fail(i);
}
}

// check XER - a2o not compliant right now (only so/ov/ca/len)
i = 33;
act = *(&tst_results + i);
exp = *(&tst_expects + i) & 0xE000007F;
ok = ok && (act == exp);
if (!ok) {
tst_fail(i);
}

// check CLT - skip tar, a2o doesn't have usermode sprg to use for save reg, so using tar
//for (i = 34; i < 37; i++) {
for (i = 34; i < 36; i++) {
act = *(&tst_results + i);
exp = *(&tst_expects + i);
ok = ok && (act == exp);
if (!ok) {
tst_fail(i);
}
}

// could get back to kernel
tst_pass();
while (1) {}
}

// these are branched to! but if fun, they assume r1 is stack!!!!

// tst is ended with sc to return to priv mode; then save results
void int_sc(int code, int srr0) {
asm (
"b tst_end\n"
: // outputs
: // inputs
: // clobbers
);
}

void int_unhandled(void) {
while(1) {}
}

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#ifndef _BIOS_H_
#define _BIOS_H_

// need address for linker constants!
extern int _fdata_rom;
extern int _edata_rom;
extern int _fdata;
extern int _fbss;
extern int _ebss;

// printf to mem
void putchar_handler(char c);


void int_sc(int code, int srr0);
void int_unhandled(void);

inline void set_epcr(int v) __attribute__((always_inline));
inline void set_dec(int v) __attribute__((always_inline));
inline void set_tbh(int v) __attribute__((always_inline));
inline void set_tbl(int v) __attribute__((always_inline));
inline void set_tsr(int v) __attribute__((always_inline));
inline void set_tcr(int v) __attribute__((always_inline));
inline void set_tens(int v) __attribute__((always_inline));
inline void set_xucr0(int v) __attribute__((always_inline));
inline int get_xucr0(void) __attribute__((always_inline));

inline void set_epcr(int v) {
asm volatile(
"mtspr 307,%0\n" // epcr
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_dec(int v) {
asm volatile(
"mtspr 22,%0\n" // dec
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tbh(int v) {
asm volatile(
"mtspr 285,%0\n" // tbh
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tbl(int v) {
asm volatile(
"mtspr 284,%0\n" // tbl
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tsr(int v) {
asm volatile(
"mtspr 336,%0\n" // tsr
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tcr(int v) {
asm volatile(
"mtspr 340,%0\n" // tcr
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline int get_xucr0(void) {
int v;
asm volatile(
"mfspr %0,1014\n" // xucr0
: "=r"(v) // outputs
: // inputs
: // clobbers
);
return v;
}

inline void set_xucr0(int v) {
asm volatile(
"mtspr 1014,%0\n" // xucr0
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

inline void set_tens(int v) {
asm volatile(
"mtspr 438,%0\n" // tens
: // outputs
: "r"(v) // inputs
: "r4" // clobbers
);
}

#endif

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# © IBM Corp. 2022
# Licensed under and subject to the terms of the CC-BY 4.0
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
# Additional rights, including the right to physically implement a softcore
# that is compliant with the required sections of the Power ISA
# Specification, will be available at no cost via the OpenPOWER Foundation.
# This README will be updated with additional information when OpenPOWER's
# license is available.

# boot kernel
# resets to 32BE
# set up translations for starting bios (inc. BE/LE)
# copy modifiable rom data to ram - or do in bios?
# set up msr for running bios (inc. 32/64)
# jump to bios


.include "defines.s"

.macro load32 rx,v
li \rx,0
oris \rx,\rx,\v>>16
ori \rx,\rx,\v&0x0000FFFF
.endm

.macro load16swiz rx,v
li \rx,0
ori \rx,\rx,(\v<<8)&0xFF00
ori \rx,\rx,(\v>>8)&0x00FF
.endm

# constants from linker script, or defsym

.ifdef BIOS_32
# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
.set BIOS_MSR,0x0002B000
.else
# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
.set BIOS_MSR,0x8002B000
.endif

#wtf this should to be done in bios based on the tst
# erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
.ifdef BIOS_LE
.set BIOS_ERATW2,0x000000BF
.else
.set BIOS_ERATW2,0x0000003F
.endif

# bios might be able to use one stack during thread startup if careful
.ifndef BIOS_STACK_0
.set BIOS_STACK_0,_stack_0
.endif

.ifndef BIOS_STACK_1
.set BIOS_STACK_1,_stack_1
.endif

#wtf get rid of this and just make the low 1G a single erat entry - it can be fixed up by bios later
.ifndef BIOS_START
.set BIOS_START,0x00010000
.endif

.section .text

.global _start

.org 0x000
_start:
int_000:
b boot_start

.ifdef TST_END
# tst ends with ba here, which switches to priv and jumps to tst_end
sc
.endif

# critical input
.org 0x020
int_020:
.ifdef INT_UNHANDLED
b int_unhandled
.else
b .
.endif

# debug
.org 0x040
int_040:
b .

# dsi
.org 0x060
int_060:
b .

# isi
.org 0x080
int_080:
b .

# external
.org 0x0A0
int_0A0:
b .

# alignment
.org 0x0C0
int_0C0:
b .

# program
.org 0x0E0
int_0E0:
b .

# fp unavailable
.org 0x100
int_100:
b .

# sc
.org 0x120
int_120:
.ifdef TST_END
# tst results haven't been saved yet; if want to call bios, need to save r1, then restore or set stack
b tst_end
.else
.ifdef INT_SC
# lev is in 20:26, but supposed to use scv now
li r3,0
mfsrr0 r4
b int_sc
.else
.ifdef INT_UNHANDLED
b int_unhandled
.else
b .
.endif
.endif
.endif

# apu unavailable
.org 0x140
int_140:
b .

# decrementer
.org 0x160
int_160:
b .

# fit
.org 0x180
int_180:
b .

# watchdog
.org 0x1A0
int_1A0:
b .

# dtlb
.org 0x1C0
int_1C0:
b .

# itlb
.org 0x1E0
int_1E0:
b .

# vector unavailable
.org 0x200
int_200:
b .

#
.org 0x220
int_220:
b .

#
.org 0x240
int_240:
b .

#
.org 0x260
int_260:
b .

# doorbell
.org 0x280
int_280:
b .

# doorbell critical
.org 0x2A0
int_2A0:
b .

# doorbell guest
.org 0x2C0
int_2C0:
b .

# doorbell guest critical
.org 0x2E0
int_2E0:
b .

# hvsc
.org 0x300
int_300:
b .

# hvpriv
.org 0x320
int_320:
b .

# lrat
.org 0x340
int_340:
b .

# ------------------------------------------------------------------------------------------------------------------------------
# initial translation
# both erats:
# 00000000 64K: (rom, BE)
# 00010000 64K: (ram, BE or LE)
#
.org 0x400
boot_start:

mfspr r5,tir # who am i?
cmpdi r5,0x00 # skip unless T0
bne init_t123

lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)

# derat 31 @00000000
li r0,0x001F # entry #31
li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

mtspr mmucr0,r3
eratwe r2,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63

# derat 30 @<BIOS_START>
li r0,0x001E # entry #30
load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
load32 r8,BIOS_START
ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

eratwe r10,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)

# ierat 15 @00000000
li r0,0x000F # entry #15
li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

mtspr mmucr0,r3
eratwe r2,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

# *** leave the init'd entry 14 for MT access to FFFFFFC0
# ierat 13 @<BIOS_START>
li r0,0x000D # entry #13
load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
load32 r8,BIOS_START
ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G

eratwe r10,r0,2
eratwe r4,r0,1
eratwe r8,r0,0
isync

b init_t0

# ------------------------------------------------------------------------------------------------------------------------------
# init
#

# T0

init_t0:

# set up BIOS msr

load32 r10,BIOS_MSR
mtmsr r10
isync
# can't use load32 unless you can .set BIOS_STACK_0 to the linked value
# load32 r1,BIOS_STACK_0 # @stack_0
# this ignores def
# lis r1,_stack_0@h
# ori r1,r1,_stack_0@l
# this requires data load
lwz r1,stack_0(r0)

b boot_complete

# except T0

init_t123:

# set up BIOS msr

load32 r10,BIOS_MSR
mtmsr r10
isync
# check tir if more than 2 threads possible
lwz r1,stack_1(r0)

b boot_complete

# ------------------------------------------------------------------------------------------------------------------------------
boot_complete:

# set up thread and hop to it

lis r3,main@h
ori r3,r3,main@l
mtctr r3
mfspr r3,tir # who am i?
bctrl
b kernel_return

# ------------------------------------------------------------------------------------------------------------------------------

.ifdef TST_PASSFAIL
.global tst_pass
.global tst_fail

.org 0x7F0
tst_pass:
b .

.org 0x7F4
tst_fail:
b .
.endif

.org 0x7FC
kernel_return:
b .

# dec
.org 0x800
int_800:
b .

# perf
.org 0x820
int_820:
b .

.org 0x8F0
.section .rodata
stack_0: .long BIOS_STACK_0
stack_1: .long BIOS_STACK_1

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#!/usr/bin/bash

export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"

#LITEXLIB=
#PRINTF=
LITEXLIB="libc.o vsnprintf.o console.o"
# getting dtlb in vsnprintf
PRINTF="-DPRINTF"

# defines

## define vars to init rom with csr's it uses...

#
#csr_base=`grep '#define CSR_BASE' generated/csr.h | cut -d ' ' -f 3 | cut -c 1-6`
#uart_base=`grep 'CSR_UART_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
#UART_ADDR="${csr_base}${uart_base}"
#defsyms="-defsym $UART_ADDR"
#
#uart_base=`grep 'CSR_UART_1_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
#if [[ "$uart_base" != "" ]] ; then
# UART_1_ADDR="${csr_base}${uart_base}"
# defsyms="$defsyms -defsym $UART_1_ADDR"
#fi
#
#uart_base=`grep 'CSR_UART_2_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
#if [[ "$uart_base" != "" ]] ; then
# UART_2_ADDR="${csr_base}${uart_base}"
# defsyms="$defsyms -defsym $UART_2_ADDR"
#fi
#
#leds_base=`grep 'CSR_LEDS_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
#if [[ "$leds_base" != "" ]] ; then
# LEDS_ADDR="${csr_base}${leds_base}"
# defsyms="$defsyms -defsym $LEDS_ADDR"
#fi
#
#echo "CSR Addresses"
#echo "Console UART: ${UART_ADDR}"
#echo " LEDS: ${LEDS_ADDR}"
#echo " UART_1: ${UART_1_ADDR}"
#echo " UART_2: ${UART_1_ADDR}"

# a2o nanokernel

echo -n "Compiling..."

echo -n "boot.s "
#powerpc-linux-gnu-as -mbig-endian -ma2 -defsym INT_SC=1 -defsym INT_UNHANDLED=1 -I. boot.s -ahlnd -o crt0.o > crt0.lst
powerpc-linux-gnu-as -mbig-endian -ma2 -defsym THREAD_ENABLES=3 -defsym TST_END=1 -defsym INT_UNHANDLED=1 -defsym TST_PASSFAIL=1 -I. boot.s -ahlnd -o crt0.o > crt0.lst

if [ $? -ne 0 ]; then
exit
fi

echo -n "arcitst.s "
#powerpc-linux-gnu-as -defsym UART_ADDR=$UART_ADDR -defsym LEDS_ADDR=$LEDS_ADDR -defsym UNHANDLED=1 -mbig-endian -mpower9 -I./asm asm/cmod7-boot.s -ahlnd -o crt0.o > crt0.lst
powerpc-linux-gnu-as -mbig-endian -ma2 -I. arcitst.s -ahlnd -o arcitst.o > arcitst.lst
if [ $? -ne 0 ]; then
exit
fi

echo ""
echo -n "bios.c "
powerpc-linux-gnu-gcc $PRINTF -c -I. $CFLAGS bios.c
if [ $? -ne 0 ]; then
exit
fi

echo ""
echo "Linking..."
powerpc-linux-gnu-ld -nostdlib -nodefaultlibs -T linker.ld crt0.o bios.o arcitst.o $LITEXLIB -o rom
if [ $? -ne 0 ]; then
exit
fi

powerpc-linux-gnu-objdump -d rom > rom.d #wtf: why not getting labels in asm code?
powerpc-linux-gnu-objdump -s rom > rom.s
#powerpc-linux-gnu-objcopy --change-section-lma .bios=0x10000 -O binary rom rom.bin
powerpc-linux-gnu-objcopy -O binary rom rom.bin

#python3 -m litex.soc.software.memusage rom ./generated/regions.ld powerpc-linux-gnu

# make rom.bin.hex
bin/bin2init rom.bin
mv rom.bin.hex rom.init

echo "Built rom.d, rom.s, rom.init."

romsize=`grep rom regions.ld | cut -d " " -f 8 | cut -c 3-10`

echo "Hardware ROM Size $romsize"
#echo ""
#echo "CSR Addresses"
#echo "Console UART: ${UART_ADDR}"
#echo " LEDS: ${LEDS_ADDR}"
#echo " UART_1: ${UART_1_ADDR}"
#echo " UART_2: ${UART_2_ADDR}"
#

43
dev/src/test3_soc/build_litex_base
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@ -0,0 +1,43 @@
#!/usr/bin/bash

export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"

echo -n "Compiling..."

echo ""

echo -n "libc.c "
powerpc-linux-gnu-gcc -c -Ilitex/include/base -Ilitex/include/flibm $CFLAGS -DNO_FLOAT litex/libbase/libc.c
if [ $? -ne 0 ]; then
exit
fi

echo -n "vsnprintf.c "
# NO_FLOAT gets rid of
#snprintf.c:(.text+0x800): undefined reference to `log10'
#powerpc-linux-gnu-ld: vsnprintf.c:(.text+0x80c): undefined reference to `floor'
#powerpc-linux-gnu-ld: vsnprintf.c:(.text+0x824): undefined reference to `pow'
#powerpc-linux-gnu-ld: vsnprintf.c:(.text+0x898): undefined reference to `fmod'
#powerpc-linux-gnu-ld: vsnprintf.c:(.text+0x950): undefined reference to `fmod'
powerpc-linux-gnu-gcc -c -Ilitex/include/base -Ilitex/include/flibm $CFLAGS -DNO_FLOAT litex/libbase/vsnprintf.c
if [ $? -ne 0 ]; then
exit
fi

echo -n "console.c "
# use hacked console.c to printf to mem instead of uart - use console_set_write_hook(console_write_hook putchar_handler)) to print to buffer
#powerpc-linux-gnu-gcc -c -Ilitex/include/base -Ilitex/include/flibm $CFLAGS litex/libbase/console.c
powerpc-linux-gnu-gcc -nostdlib -nodefaultlibs -c -Ilitex/include/base -Ilitex/include/flibm $CFLAGS console.c

if [ $? -ne 0 ]; then
exit
fi

echo ""

#echo "Linking to test dependencies..."
#powerpc-linux-gnu-ld -nostdlib -nodefaultlibs libc.o vsnprintf.o console.o -o litexlib.o
#if [ $? -ne 0 ]; then
# exit
#fi

113
dev/src/test3_soc/console.c
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// use console_set_write_hook(func) to do putchar() to mem

//#include <uart.h>
#include <console.h>
#include <stdio.h>
#include <stdarg.h>

//#include <generated/csr.h>

FILE *stdin, *stdout, *stderr;

static console_write_hook write_hook;
static console_read_hook read_hook;
static console_read_nonblock_hook read_nonblock_hook;

void console_set_write_hook(console_write_hook h)
{
write_hook = h;
}

void console_set_read_hook(console_read_hook r, console_read_nonblock_hook rn)
{
read_hook = r;
read_nonblock_hook = rn;
}

#ifdef CSR_UART_BASE
int putchar(int c)
{
uart_write(c);
if(write_hook != NULL)
write_hook(c);
if (c == '\n')
putchar('\r');
return c;
}

char readchar(void)
{
while(1) {
if(uart_read_nonblock())
return uart_read();
if((read_nonblock_hook != NULL) && read_nonblock_hook())
return read_hook();
}
}

int readchar_nonblock(void)
{
return (uart_read_nonblock()
|| ((read_nonblock_hook != NULL) && read_nonblock_hook()));
}

#else

int putchar(int c)
{
if(write_hook != NULL)
write_hook(c);
return c;
}

char readchar(void)
{
while(1) {
if((read_nonblock_hook != NULL) && read_nonblock_hook())
return read_hook();
}
}

int readchar_nonblock(void)
{
return ((read_nonblock_hook != NULL) && read_nonblock_hook());
}

#endif

int puts(const char *s)
{
putsnonl(s);
putchar('\n');
return 1;
}

void putsnonl(const char *s)
{
while(*s) {
putchar(*s);
s++;
}
}

#define PRINTF_BUFFER_SIZE 256

int vprintf(const char *fmt, va_list args)
{
int len;
char outbuf[PRINTF_BUFFER_SIZE];
len = vscnprintf(outbuf, sizeof(outbuf), fmt, args);
outbuf[len] = 0;
putsnonl(outbuf);
return len;
}

int printf(const char *fmt, ...)
{
int len;
va_list args;
va_start(args, fmt);
len = vprintf(fmt, args);
va_end(args);
return len;
}

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661
dev/src/test3_soc/crt0.lst
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1 # © IBM Corp. 2022
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 # boot kernel
11 # resets to 32BE
12 # set up translations for starting bios (inc. BE/LE)
13 # copy modifiable rom data to ram - or do in bios?
14 # set up msr for running bios (inc. 32/64)
15 # jump to bios
16
17
18 .include "defines.s"
1 # © IBM Corp. 2020
2 # Licensed under and subject to the terms of the CC-BY 4.0
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
4 # Additional rights, including the right to physically implement a softcore
5 # that is compliant with the required sections of the Power ISA
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
7 # This README will be updated with additional information when OpenPOWER's
8 # license is available.
9
10 #-----------------------------------------
11 # Defines
12 #-----------------------------------------
13
14 # Regs
15
16 .set r0, 0
17 .set r1, 1
18 .set r2, 2
19 .set r3, 3
20 .set r4, 4
21 .set r5, 5
22 .set r6, 6
23 .set r7, 7
24 .set r8, 8
25 .set r9, 9
26 .set r10,10
27 .set r11,11
28 .set r12,12
29 .set r13,13
30 .set r14,14
31 .set r15,15
32 .set r16,16
33 .set r17,17
34 .set r18,18
35 .set r19,19
36 .set r20,20
37 .set r21,21
38 .set r22,22
39 .set r23,23
40 .set r24,24
41 .set r25,25
42 .set r26,26
43 .set r27,27
44 .set r28,28
45 .set r29,29
46 .set r30,30
47 .set r31,31
48
49 .set f0, 0
50 .set f1, 1
51 .set f2, 2
52 .set f3, 3
53 .set f4, 4
54 .set f5, 5
55 .set f6, 6
56 .set f7, 7
57 .set f8, 8
58 .set f9, 9
59 .set f10,10
60 .set f11,11
61 .set f12,12
62 .set f13,13
63 .set f14,14
64 .set f15,15
65 .set f16,16
66 .set f17,17
67 .set f18,18
68 .set f19,19
69 .set f20,20
70 .set f21,21
71 .set f22,22
72 .set f23,23
73 .set f24,24
74 .set f25,25
75 .set f26,26
76 .set f27,27
77 .set f28,28
78 .set f29,29
79 .set f30,30
80 .set f31,31
81
82 .set cr0, 0
83 .set cr1, 1
84 .set cr2, 2
85 .set cr3, 3
86 .set cr4, 4
87 .set cr5, 5
88 .set cr6, 6
89 .set cr7, 7
90
91 # SPR numbers
92
93 .set srr0, 26
94 .set srr1, 27
95 .set dar, 19
96 .set dsisr, 18
97 .set epcr, 307
98 .set tar, 815
99
100 .set dbsr, 304
101 .set dbcr0, 308
102 .set dbcr1, 309
103 .set dbcr2, 310
104 .set dbcr3, 848
105
106 .set ivpr, 63
107
108 .set iucr0, 1011
109 .set iucr1, 883
110 .set iucr2, 884
111
112 .set iudbg0, 888
113 .set iudbg1, 889
114 .set iudbg2, 890
115 .set iulfsr, 891
116 .set iullcr, 892
117
118 .set mmucr0, 1020
119 .set mmucr1, 1021
120 .set mmucr2, 1022
121 .set mmucr3, 1023
122
123 .set tb, 268
124 .set tbl, 284
125 .set tbh, 285
126
127 .set dec, 22
128 .set udec, 550
129 .set tsr, 336
130 .set tcr, 340
131
132 .set xucr0, 1014
133 .set xucr1, 851
134 .set xucr2, 1016
135 .set xucr3, 852
136 .set xucr4, 853
137
138 .set tens, 438
139 .set tenc, 439
140 .set tensr, 437
141
142 .set pid, 48
143 .set pir, 286
144 .set pvr, 287
145 .set tir, 446
146
147 #.set sprg0,
148 #.set sprg1,
149 #.set sprg2,
150 .set sprg3, 259
19
20 .macro load32 rx,v
21 li \rx,0
22 oris \rx,\rx,\v>>16
23 ori \rx,\rx,\v&0x0000FFFF
24 .endm
25
26 .macro load16swiz rx,v
27 li \rx,0
28 ori \rx,\rx,(\v<<8)&0xFF00
29 ori \rx,\rx,(\v>>8)&0x00FF
30 .endm
31
32 # constants from linker script, or defsym
33
34 .ifdef BIOS_32
35 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
36 .set BIOS_MSR,0x0002B000
37 .else
38 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
39 .set BIOS_MSR,0x8002B000
40 .endif
41
42 #wtf this should to be done in bios based on the tst
43 # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw
44 .ifdef BIOS_LE
45 .set BIOS_ERATW2,0x000000BF
46 .else
47 .set BIOS_ERATW2,0x0000003F
48 .endif
49
50 # bios might be able to use one stack during thread startup if careful
51 .ifndef BIOS_STACK_0
52 .set BIOS_STACK_0,_stack_0
53 .endif
54
55 .ifndef BIOS_STACK_1
56 .set BIOS_STACK_1,_stack_1
57 .endif
58
59 #wtf get rid of this and just make the low 1G a single erat entry - it can be fixed up by bios late
60 .ifndef BIOS_START
61 .set BIOS_START,0x00010000
62 .endif
63
64 .section .text
65
66 .global _start
67
68 .org 0x000
69 _start:
70 int_000:
71 0000 48000400 b boot_start
72
73 .ifdef TST_END
74 # tst ends with ba here, which switches to priv and jumps to tst_end
75 0004 44000002 sc
76 .endif
77
78 # critical input
79 0008 00000000 .org 0x020
79 00000000
79 00000000
79 00000000
79 00000000
80 int_020:
81 .ifdef INT_UNHANDLED
82 0020 48000000 b int_unhandled
83 .else
84 b .
85 .endif
86
87 # debug
88 0024 00000000 .org 0x040
88 00000000
88 00000000
88 00000000
88 00000000
89 int_040:
90 0040 48000000 b .
91
92 # dsi
93 0044 00000000 .org 0x060
93 00000000
93 00000000
93 00000000
93 00000000
94 int_060:
95 0060 48000000 b .
96
97 # isi
98 0064 00000000 .org 0x080
98 00000000
98 00000000
98 00000000
98 00000000
99 int_080:
100 0080 48000000 b .
101
102 # external
103 0084 00000000 .org 0x0A0
103 00000000
103 00000000
103 00000000
103 00000000
104 int_0A0:
105 00a0 48000000 b .
106
107 # alignment
108 00a4 00000000 .org 0x0C0
108 00000000
108 00000000
108 00000000
108 00000000
109 int_0C0:
110 00c0 48000000 b .
111
112 # program
113 00c4 00000000 .org 0x0E0
113 00000000
113 00000000
113 00000000
113 00000000
114 int_0E0:
115 00e0 48000000 b .
116
117 # fp unavailable
118 00e4 00000000 .org 0x100
118 00000000
118 00000000
118 00000000
118 00000000
119 int_100:
120 0100 48000000 b .
121
122 # sc
123 0104 00000000 .org 0x120
123 00000000
123 00000000
123 00000000
123 00000000
124 int_120:
125 .ifdef TST_END
126 # tst results haven't been saved yet; if want to call bios, need to save r1, then restore or set st
127 0120 48000000 b tst_end
128 .else
129 .ifdef INT_SC
130 # lev is in 20:26, but supposed to use scv now
131 li r3,0
132 mfsrr0 r4
133 b int_sc
134 .else
135 .ifdef INT_UNHANDLED
136 b int_unhandled
137 .else
138 b .
139 .endif
140 .endif
141 .endif
142
143 # apu unavailable
144 0124 00000000 .org 0x140
144 00000000
144 00000000
144 00000000
144 00000000
145 int_140:
146 0140 48000000 b .
147
148 # decrementer
149 0144 00000000 .org 0x160
149 00000000
149 00000000
149 00000000
149 00000000
150 int_160:
151 0160 48000000 b .
152
153 # fit
154 0164 00000000 .org 0x180
154 00000000
154 00000000
154 00000000
154 00000000
155 int_180:
156 0180 48000000 b .
157
158 # watchdog
159 0184 00000000 .org 0x1A0
159 00000000
159 00000000
159 00000000
159 00000000
160 int_1A0:
161 01a0 48000000 b .
162
163 # dtlb
164 01a4 00000000 .org 0x1C0
164 00000000
164 00000000
164 00000000
164 00000000
165 int_1C0:
166 01c0 48000000 b .
167
168 # itlb
169 01c4 00000000 .org 0x1E0
169 00000000
169 00000000
169 00000000
169 00000000
170 int_1E0:
171 01e0 48000000 b .
172
173 # vector unavailable
174 01e4 00000000 .org 0x200
174 00000000
174 00000000
174 00000000
174 00000000
175 int_200:
176 0200 48000000 b .
177
178 #
179 0204 00000000 .org 0x220
179 00000000
179 00000000
179 00000000
179 00000000
180 int_220:
181 0220 48000000 b .
182
183 #
184 0224 00000000 .org 0x240
184 00000000
184 00000000
184 00000000
184 00000000
185 int_240:
186 0240 48000000 b .
187
188 #
189 0244 00000000 .org 0x260
189 00000000
189 00000000
189 00000000
189 00000000
190 int_260:
191 0260 48000000 b .
192
193 # doorbell
194 0264 00000000 .org 0x280
194 00000000
194 00000000
194 00000000
194 00000000
195 int_280:
196 0280 48000000 b .
197
198 # doorbell critical
199 0284 00000000 .org 0x2A0
199 00000000
199 00000000
199 00000000
199 00000000
200 int_2A0:
201 02a0 48000000 b .
202
203 # doorbell guest
204 02a4 00000000 .org 0x2C0
204 00000000
204 00000000
204 00000000
204 00000000
205 int_2C0:
206 02c0 48000000 b .
207
208 # doorbell guest critical
209 02c4 00000000 .org 0x2E0
209 00000000
209 00000000
209 00000000
209 00000000
210 int_2E0:
211 02e0 48000000 b .
212
213 # hvsc
214 02e4 00000000 .org 0x300
214 00000000
214 00000000
214 00000000
214 00000000
215 int_300:
216 0300 48000000 b .
217
218 # hvpriv
219 0304 00000000 .org 0x320
219 00000000
219 00000000
219 00000000
219 00000000
220 int_320:
221 0320 48000000 b .
222
223 # lrat
224 0324 00000000 .org 0x340
224 00000000
224 00000000
224 00000000
224 00000000
225 int_340:
226 0340 48000000 b .
227
228 # -------------------------------------------------------------------------------------------------
229 # initial translation
230 # both erats:
231 # 00000000 64K: (rom, BE)
232 # 00010000 64K: (ram, BE or LE)
233 #
234 0344 00000000 .org 0x400
234 00000000
234 00000000
234 00000000
234 00000000
235 boot_start:
236
237 0400 7CBE6AA6 mfspr r5,tir # who am i?
238 0404 2C250000 cmpdi r5,0x00 # skip unless T0
239 0408 408200E0 bne init_t123
240
241 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
242
243 # derat 31 @00000000
244 0410 3800001F li r0,0x001F # entry #31
245 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
246 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
247 041c 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
248
249 0420 7C7CFBA6 mtspr mmucr0,r3
250 0424 7C4011A6 eratwe r2,r0,2
251 0428 7C8009A6 eratwe r4,r0,1
252 042c 7D0001A6 eratwe r8,r0,0
253 0430 4C00012C isync
254
255 0434 39400000 load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
255 654A0000
255 614A003F
256
257 # derat 30 @<BIOS_START>
258 0440 3800001E li r0,0x001E # entry #30
259 0444 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
259 64840001
259 60840000
260 0450 39000000 load32 r8,BIOS_START
260 65080001
260 61080000
261 045c 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
262
263 0460 7D4011A6 eratwe r10,r0,2
264 0464 7C8009A6 eratwe r4,r0,1
265 0468 7D0001A6 eratwe r8,r0,0
266 046c 4C00012C isync
267
268 0470 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
269
270 # ierat 15 @00000000
271 0474 3800000F li r0,0x000F # entry #15
272 0478 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
273 047c 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
274 0480 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
275
276 0484 7C7CFBA6 mtspr mmucr0,r3
277 0488 7C4011A6 eratwe r2,r0,2
278 048c 7C8009A6 eratwe r4,r0,1
279 0490 7D0001A6 eratwe r8,r0,0
280 0494 4C00012C isync
281
282 # *** leave the init'd entry 14 for MT access to FFFFFFC0
283 # ierat 13 @<BIOS_START>
284 0498 3800000D li r0,0x000D # entry #13
285 049c 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
285 64840001
285 60840000
286 04a8 39000000 load32 r8,BIOS_START
286 65080001
286 61080000
287 04b4 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
288
289 04b8 7D4011A6 eratwe r10,r0,2
290 04bc 7C8009A6 eratwe r4,r0,1
291 04c0 7D0001A6 eratwe r8,r0,0
292 04c4 4C00012C isync
293
294 04c8 48000004 b init_t0
295
296 # -------------------------------------------------------------------------------------------------
297 # init
298 #
299
300 # T0
301
302 init_t0:
303
304 # set up BIOS msr
305
306 04cc 39400000 load32 r10,BIOS_MSR
306 654A8002
306 614AB000
307 04d8 7D400124 mtmsr r10
308 04dc 4C00012C isync
309 # can't use load32 unless you can .set BIOS_STACK_0 to the linked value
310 # load32 r1,BIOS_STACK_0 # @stack_0
311 # this ignores def
312 # lis r1,_stack_0@h
313 # ori r1,r1,_stack_0@l
314 # this requires data load
315 04e0 80200000 lwz r1,stack_0(r0)
316
317 04e4 48000020 b boot_complete
318
319 # except T0
320
321 init_t123:
322
323 # set up BIOS msr
324
325 04e8 39400000 load32 r10,BIOS_MSR
325 654A8002
325 614AB000
326 04f4 7D400124 mtmsr r10
327 04f8 4C00012C isync
328 # check tir if more than 2 threads possible
329 04fc 80200000 lwz r1,stack_1(r0)
330
331 0500 48000004 b boot_complete
332
333 # -------------------------------------------------------------------------------------------------
334 boot_complete:
335
336 # set up thread and hop to it
337
338 0504 3C600000 lis r3,main@h
339 0508 60630000 ori r3,r3,main@l
340 050c 7C6903A6 mtctr r3
341 0510 7C7E6AA6 mfspr r3,tir # who am i?
342 0514 4E800421 bctrl
343 0518 480002E4 b kernel_return
344
345 # -------------------------------------------------------------------------------------------------
346
347 .ifdef TST_PASSFAIL
348 .global tst_pass
349 .global tst_fail
350
351 051c 00000000 .org 0x7F0
351 00000000
351 00000000
351 00000000
351 00000000
352 tst_pass:
353 07f0 48000000 b .
354
355 .org 0x7F4
356 tst_fail:
357 07f4 48000000 b .
358 .endif
359
360 07f8 00000000 .org 0x7FC
361 kernel_return:
362 07fc 48000000 b .
363
364 # dec
365 .org 0x800
366 int_800:
367 0800 48000000 b .
368
369 # perf
370 0804 00000000 .org 0x820
370 00000000
370 00000000
370 00000000
370 00000000
371 int_820:
372 0820 48000000 b .
373
374 0824 00000000 .org 0x8F0
374 00000000
374 00000000
374 00000000
374 00000000
375 .section .rodata
376 0000 00000000 stack_0: .long BIOS_STACK_0
377 0004 00000000 stack_1: .long BIOS_STACK_1

150
dev/src/test3_soc/defines.s
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# © IBM Corp. 2020
# Licensed under and subject to the terms of the CC-BY 4.0
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
# Additional rights, including the right to physically implement a softcore
# that is compliant with the required sections of the Power ISA
# Specification, will be available at no cost via the OpenPOWER Foundation.
# This README will be updated with additional information when OpenPOWER's
# license is available.

#-----------------------------------------
# Defines
#-----------------------------------------

# Regs

.set r0, 0
.set r1, 1
.set r2, 2
.set r3, 3
.set r4, 4
.set r5, 5
.set r6, 6
.set r7, 7
.set r8, 8
.set r9, 9
.set r10,10
.set r11,11
.set r12,12
.set r13,13
.set r14,14
.set r15,15
.set r16,16
.set r17,17
.set r18,18
.set r19,19
.set r20,20
.set r21,21
.set r22,22
.set r23,23
.set r24,24
.set r25,25
.set r26,26
.set r27,27
.set r28,28
.set r29,29
.set r30,30
.set r31,31

.set f0, 0
.set f1, 1
.set f2, 2
.set f3, 3
.set f4, 4
.set f5, 5
.set f6, 6
.set f7, 7
.set f8, 8
.set f9, 9
.set f10,10
.set f11,11
.set f12,12
.set f13,13
.set f14,14
.set f15,15
.set f16,16
.set f17,17
.set f18,18
.set f19,19
.set f20,20
.set f21,21
.set f22,22
.set f23,23
.set f24,24
.set f25,25
.set f26,26
.set f27,27
.set f28,28
.set f29,29
.set f30,30
.set f31,31

.set cr0, 0
.set cr1, 1
.set cr2, 2
.set cr3, 3
.set cr4, 4
.set cr5, 5
.set cr6, 6
.set cr7, 7

# SPR numbers

.set srr0, 26
.set srr1, 27
.set dar, 19
.set dsisr, 18
.set epcr, 307
.set tar, 815

.set dbsr, 304
.set dbcr0, 308
.set dbcr1, 309
.set dbcr2, 310
.set dbcr3, 848

.set ivpr, 63

.set iucr0, 1011
.set iucr1, 883
.set iucr2, 884

.set iudbg0, 888
.set iudbg1, 889
.set iudbg2, 890
.set iulfsr, 891
.set iullcr, 892

.set mmucr0, 1020
.set mmucr1, 1021
.set mmucr2, 1022
.set mmucr3, 1023

.set tb, 268
.set tbl, 284
.set tbh, 285

.set dec, 22
.set udec, 550
.set tsr, 336
.set tcr, 340

.set xucr0, 1014
.set xucr1, 851
.set xucr2, 1016
.set xucr3, 852
.set xucr4, 853

.set tens, 438
.set tenc, 439
.set tensr, 437

.set pid, 48
.set pir, 286
.set pvr, 287
.set tir, 446

#.set sprg0,
#.set sprg1,
#.set sprg2,
.set sprg3, 259

319
dev/src/test3_soc/fx_alucmpbr.tst
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* OPV
* Testname: fx_alucmpbr.tst

* --------------------------------------------------------------------------------
TEST 1001
INITIALIZATIONS: DATA MEMORY
D 0000000008F00850 0001FFFFFF000007D400000068877812 * PTE Match EPN=0x000000000001 VPN=0x0001FFFFFF000001 RPN=0x000000006887 WIMG=0x2 I TA=0
D 0000000053E6FD70 2000000008F10B02 * Root Table Descriptor , Partition Table Primary Entry for LPID = 0xFD7: HTABORG = 0x0800_0000_023C, HTABSIZE = 0x02, PS = 0x0, Entry Address = 0x0000_0000_53E6_FD70 WIMG=0x2
D 0000000053E6FD78 000618E1E5836C87 * Segmentation On HPT, Process Table Descriptor, Partition Table Secondary Entry for LPID = 0xFD7: PRTB = 0x00_030C_70F2, PTS = 0x07, NUT = 0x0, PTPS = 0x4 WIMG=0x2
D 00000000F0D2D3F0 400AC1CD9CEF56376DF7C045D17603CB * Guest Root Table Descriptor, Process Table Entry for LPID = 0x000 STABORGU = 0x000A_C1CD_9CEF_5637 STABORGL = 0x6 STABSIZE = 0xC B = 0x1 STPS = 0x5
INITIALIZATIONS: INSTRUCTION MEMORY
LEVEL 4 CHIP 0
LEVEL 3 CORE 0
INITIALIZATIONS: REGISTERS
LEVEL 2 PARTITION 0
INITIALIZATIONS: REGISTERS
LEVEL 1 THREAD 0
INITIALIZATIONS: REGISTERS
R CR DBFD3628 * LT:1 GT:1 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R DAR 96A22826D573F45F
R DSISR 48068CFB * TS:0 PF:1 ATT:0 Rsrv35:0 Prot:1 CI:0
* Store:0 Rsrv39_40:0 DAWR:0 VPCK:0
* SMF:0 RADIX:0 RC:1 Guest_Tbl:1
* Rsrv47_61:233E CIX:1 EAO:1
R DEC 0000000005792645
R XER 00002E2289F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:0 LT:1 GT:0 EQ:0 IC:1 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R G0 CC7B4BBA00000000
R G1 F99E00E65822C905
R G3 48577A9C91B6D1A3
R G9 6872DEB47E11EE88
R G11 415D35187FFFFFFF
R G14 BCF163168C20BDE6
R G16 CE83BAA576D0DADF
R G17 06C01CAE15111F42
R G19 4283519E36108E50
R G22 4FA8B87B328A0CED
R G25 9138C732AF224C19
R G28 2F4816B9D624B27A
R IAR 0000000000010000
R MSR 0000000000001104 * SF:0 TA:0 Rsrv2_old_ISF:0 HV:0
* Rsrv4:0 SLE:0 Rsrv6_28:000000 TS:0
* TM:0 Rsrv32_37:00 VMX:0 Rsrv39:0
* VSX:0 S:0 Rsrv42_47:00 EE:0 PR:0 FP:0
* ME:1 FE0:0 SE:0 BE:0 FE1:1 US:0
* Rsrv57_old_IP:0 IR:0 DR:0
* Rsrv60_old_SO:0 PMM:1 RI:0 LE:0

PHASE 0 INSTRUCTIONS
I 0000000068870000 7C61CC14 * EA=0000000000010000 WIMG=2 addco G3,G1,G25 INum:1 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G1 F99E00E65822C905
R G25 9138C732AF224C19
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 0000000000000000 M 0000000000000000 * PTE
TRACE WRITES
R G3 8AD6C8190745151E
R XER 00002E22A9F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:0 LT:1 GT:0 EQ:0 IC:1 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
R IAR 0000000000010004
D 0000000008F00858 D400000068877912 * PTE
I 0000000068870004 7D230595 * EA=0000000000010004 WIMG=2 addzeo. G9,G3 INum:2 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G3 8AD6C8190745151E
R XER 00002E22A9F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:0 LT:1 GT:0 EQ:0 IC:1 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G9 8AD6C8190745151F
R XER 00002E2284F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:0 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R CR 5BFD3628 * LT:0 GT:1 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 0000000000010008
I 0000000068870008 7AC37392 * EA=0000000000010008 WIMG=2 rldcr G3,G22,G14,0x0E INum:3 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G14 BCF163168C20BDE6
R G22 4FA8B87B328A0CED
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G3 A282000000000000
R IAR 000000000001000C
I 000000006887000C 7E094C11 * EA=000000000001000C WIMG=2 subfco. G16,G9,G9 INum:4 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G9 8AD6C8190745151F
R XER 00002E2284F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:0 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G16 0000000000000000
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
R CR 3BFD3628 * LT:0 GT:0 EQ:1 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 0000000000010010
I 0000000068870010 7E1CB115 * EA=0000000000010010 WIMG=2 adde. G16,G28,G22 INum:5 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G28 2F4816B9D624B27A
R G22 4FA8B87B328A0CED
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G16 7EF0CF3508AEBF68
R XER 00002E22B4F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
R CR 5BFD3628 * LT:0 GT:1 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 0000000000010014
I 0000000068870014 7A338886 * EA=0000000000010014 WIMG=2 rldicr G19,G17,0x31,0x02 INum:6 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G17 06C01CAE15111F42
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G19 2000000000000000
R IAR 0000000000010018
I 0000000068870018 7C6004D1 * EA=0000000000010018 WIMG=2 nego. G3,G0 INum:7 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G0 CC7B4BBA00000000
R XER 00002E22B4F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G3 3384B44600000000
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
R CR 3BFD3628 * LT:0 GT:0 EQ:1 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 000000000001001C
I 000000006887001C 7E09B038 * EA=000000000001001C WIMG=2 and G9,G16,G22 INum:8 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G16 7EF0CF3508AEBF68
R G22 4FA8B87B328A0CED
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G9 4EA08831008A0C68
R IAR 0000000000010020
I 0000000068870020 7C360591 * EA=0000000000010020 WIMG=2 subfzeo. G1,G22 INum:9 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G22 4FA8B87B328A0CED
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:1
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G1 B0574784CD75F313
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R CR 9BFD3628 * LT:1 GT:0 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R IAR 0000000000010024
I 0000000068870024 7E2B00D1 * EA=0000000000010024 WIMG=2 neg. G17,G11 INum:10 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
R G11 415D35187FFFFFFF
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R G17 BEA2CAE780000001
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R CR 9BFD3628 * LT:1 GT:0 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
* FALSE PHASE 0.0 INSTRUCTIONS
R IAR 0000000000010028

EPILOGUE
* Begin macro Epilogue_Sequence
* TRUE
* TRUE
I 0000000068870028 60000000 * EA=0000000000010028 WIMG=2 nop INum:11 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R IAR 000000000001002C
I 000000006887002C 60000000 * EA=000000000001002C WIMG=2 nop_Epilogue INum:12 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R IAR 0000000000010030
I 0000000068870030 60000000 * EA=0000000000010030 WIMG=2 nop_Epilogue INum:13 PartId:0 ThreadId:0 Phase:0 CoreId:0

TRACE READS
D 0000000053E6FD70 2000000008F10B02 * RADIX
D 0000000053E6FD78 000618E1E5836C87 * RADIX
D 0000000008F00850 0001FFFFFF000007 * PTE
D 0000000008F00858 D400000068877912 * PTE
TRACE WRITES
R IAR 0000000000010034
I 0000000068870034 24000000 * EA=0000000000010034 WIMG=2 notrace INum:14 PartId:0 ThreadId:0 Phase:0 CoreId:0
* End of macro Epilogue_Sequence
RESULTS: REGISTERS
R CR 9BFD3628 * LT:1 GT:0 EQ:0 SO:1 FX:1 FEX:0 VX:1
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
* CR7:8
R DAR 96A22826D573F45F
R DSISR 48068CFB * TS:0 PF:1 ATT:0 Rsrv35:0 Prot:1 CI:0
* Store:0 Rsrv39_40:0 DAWR:0 VPCK:0
* SMF:0 RADIX:0 RC:1 Guest_Tbl:1
* Rsrv47_61:233E CIX:1 EAO:1
R DEC 0000000005792645
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
* TAG1:1 TAG:1 OV32:0 CA32:0
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
R G0 CC7B4BBA00000000
R G1 B0574784CD75F313
R G3 3384B44600000000
R G9 4EA08831008A0C68
R G11 415D35187FFFFFFF
R G14 BCF163168C20BDE6
R G16 7EF0CF3508AEBF68
R G17 BEA2CAE780000001
R G19 2000000000000000
R G22 4FA8B87B328A0CED
R G25 9138C732AF224C19
R G28 2F4816B9D624B27A
R IAR 0000000000010038
R MSR 0000000000001104 * SF:0 TA:0 Rsrv2_old_ISF:0 HV:0
* Rsrv4:0 SLE:0 Rsrv6_28:000000 TS:0
* TM:0 Rsrv32_37:00 VMX:0 Rsrv39:0
* VSX:0 S:0 Rsrv42_47:00 EE:0 PR:0 FP:0
* ME:1 FE0:0 SE:0 BE:0 FE1:1 US:0
* Rsrv57_old_IP:0 IR:0 DR:0
* Rsrv60_old_SO:0 PMM:1 RI:0 LE:0
END_OF_LEVEL 1 THREAD 0
RESULTS: REGISTERS
END_OF_LEVEL 2 PARTITION 0
RESULTS: REGISTERS
END_OF_LEVEL 3 CORE 0
END_OF_LEVEL 4 CHIP 0
RESULTS: DATA MEMORY
D 0000000008F00850 0001FFFFFF000007D400000068877912 * PTE
D 0000000053E6FD70 2000000008F10B02
D 0000000053E6FD78 000618E1E5836C87
D 00000000F0D2D3F0 400AC1CD9CEF56376DF7C045D17603CB
END_OF_TEST

8
dev/src/test3_soc/liblitex.h
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#ifndef _LITEXLIB_
#define _LITEXLIB_

//#include <litex/include/base/console.h>
#include <litex/libbase/console.h>


#endif

96
dev/src/test3_soc/linker.ld
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/* this version puts kernel and bios at rom start
/* and makes the tst be copied to ram (soc really does have rom memory)

/* define format
INCLUDE output_format.ld */
OUTPUT_FORMAT("elf32-powerpc")

ENTRY(_start)

/* define origin, len of rom, ram, csr */
INCLUDE regions.ld

SECTIONS
{
/* kernel code */
.kernel :
{
/*_fkernel = .; */
*crt0*(.text)
KEEP(*crt0*(.text))
*(.gnu.linkonce.t.*)
_ekernel = .;
} > rom

.rodata :
{
. = ALIGN(8);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
*(.got2 .got2.*)
*(.toc .toc.*)
FILL(0);
. = ALIGN(8);
_erodata = .;
} > rom

/* bios code */
.bios :
{
. = ALIGN(32);
bios.o (.text .text* .gnu.linkonce.t.*)
. = ALIGN(4);
} > rom

/* kernel data to be copied to ram by rom code...*/
.data :
{
. = ALIGN(8);
_fdata = .;
*(.data .data.* .sdata .gnu.linkonce.d.*)
FILL(0);
. = ALIGN(8);
_edata = .;
} > ram AT > rom

/* tst - if statically loaded in rom, must be copied to ram (save/restore) */
/* now if i don't make it .data, linker puts bios after it??? because of .text???*/
.data :
{
. = ALIGN(32);
arcitst.o (.text .text* .gnu.linkonce.t.*)
. = ALIGN(4);
} > ram AT > rom

.bss :
{
/*. = 0x00000000; */
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
_ebss = .;
_end = .;
} > ram

/DISCARD/ :
{
*(.eh_frame)
*(.comment)
*(.gnu.attributes)
}

}

PROVIDE(_stack_size = 0x00010000);
PROVIDE(_stack_0 = ORIGIN(ram) + LENGTH(ram) - 8);
PROVIDE(_stack_1 = _stack_0 - _stack_size);

PROVIDE(_fdata_rom = LOADADDR(.data));
PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));
PROVIDE(_bios_start = LOADADDR(.bios));

1
dev/src/test3_soc/litex
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/home/wtf/projects/litex/litex/soc/software

85
dev/src/test3_soc/readme.md
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# test3 - kernel+bios+arci

* gen, convert, and link random tst (fx_alucmpbr.tst), and try to run

```
build

# create mem file for coco sim
cp rom.init test3
```

### methodology

1. produce tst.s (stub code and tst definition) and link with kernel/bios
2. tst init is done in tst.s
3. jmp2tst
4. tst ends (bla through kernel, sc, etc.)
5. tst cleanup is done in tst.s
6. tst checking, etc. is done in bios




### debug

* hanging during results save; itags not executed in cpl queue

![](cpl_hang.png)

* itags 07-0B are dispatched but not marked 'executed' in cplq; they were sent to stq

* not documented completely in spec (CPCR2, CPCR3, CPCR4, CPCR5); 2/3 are for hi-pri and 4/5 for med(?)

```
assign spr_t0_cpcr2_fx0_cnt = cpcr2_l2[0][35:39];
assign spr_t0_cpcr2_fx1_cnt = cpcr2_l2[0][43:47];
assign spr_t0_cpcr2_lq_cnt = cpcr2_l2[0][51:55];
assign spr_t0_cpcr2_sq_cnt = cpcr2_l2[0][59:63];
assign spr_t0_cpcr3_fu0_cnt = cpcr3_l2[0][43:47];
assign spr_t0_cpcr3_fu1_cnt = cpcr3_l2[0][51:55];
assign spr_t0_cpcr3_cp_cnt = cpcr3_l2[0][57:63];
assign spr_t0_cpcr4_fx0_cnt = cpcr4_l2[0][35:39];
assign spr_t0_cpcr4_fx1_cnt = cpcr4_l2[0][43:47];
assign spr_t0_cpcr4_lq_cnt = cpcr4_l2[0][51:55];
assign spr_t0_cpcr4_sq_cnt = cpcr4_l2[0][59:63];
assign spr_t0_cpcr5_fu0_cnt = cpcr5_l2[0][43:47];
assign spr_t0_cpcr5_fu1_cnt = cpcr5_l2[0][51:55];
assign spr_t0_cpcr5_cp_cnt = cpcr5_l2[0][57:63];
```

* verilog violation in iuq_dispatch! unused thread 1 strand bits skipping force to 0, and used later as x's for credit checks which didn't stop dispatch

```
//wtf (THREADS1 is def'd)
// iverilog sez: ../../verilog/work/iuq_dispatch.v:2322: warning: @* found no sensitivities so it will never trigger.
// seems to be correct behavior - block won't be entered without a value change
// make it initial, or a generate?
`ifdef THREADS1
//always @(*)
initial
```


### printf from litex

add putchar function to store to memory buffer

```
/home/wtf/projects/litex/litex/soc/software/libbase/vsnprintf.c

plus at least these:

from /home/wtf/projects/litex/litex/soc/software/include/base/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <ctype.h>
#include <math.h>
#include <stddef.h>

from /home/wtf/projects/litex/litex/soc/software/include/fdlibm
#include <fdlibm.h>
```

6
dev/src/test3_soc/regions.ld
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MEMORY {
rom : ORIGIN = 0x00000000, LENGTH = 0x00010000
tst : ORIGIN = 0x00010000, LENGTH = 0x00002000
ram : ORIGIN = 0x00012000, LENGTH = 0x0000E000
csr : ORIGIN = 0xFFF00000, LENGTH = 0x00010000
}

BIN
dev/src/test3_soc/rom
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dev/src/test3_soc/rom.s
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rom: file format elf32-powerpc

Contents of section .kernel:
0000 48000400 44000002 00000000 00000000 H...D...........
0010 00000000 00000000 00000000 00000000 ................
0020 48001010 00000000 00000000 00000000 H...............
0030 00000000 00000000 00000000 00000000 ................
0040 48000000 00000000 00000000 00000000 H...............
0050 00000000 00000000 00000000 00000000 ................
0060 48000000 00000000 00000000 00000000 H...............
0070 00000000 00000000 00000000 00000000 ................
0080 48000000 00000000 00000000 00000000 H...............
0090 00000000 00000000 00000000 00000000 ................
00a0 48000000 00000000 00000000 00000000 H...............
00b0 00000000 00000000 00000000 00000000 ................
00c0 48000000 00000000 00000000 00000000 H...............
00d0 00000000 00000000 00000000 00000000 ................
00e0 48000000 00000000 00000000 00000000 H...............
00f0 00000000 00000000 00000000 00000000 ................
0100 48000000 00000000 00000000 00000000 H...............
0110 00000000 00000000 00000000 00000000 ................
0120 48012134 00000000 00000000 00000000 H.!4............
0130 00000000 00000000 00000000 00000000 ................
0140 48000000 00000000 00000000 00000000 H...............
0150 00000000 00000000 00000000 00000000 ................
0160 48000000 00000000 00000000 00000000 H...............
0170 00000000 00000000 00000000 00000000 ................
0180 48000000 00000000 00000000 00000000 H...............
0190 00000000 00000000 00000000 00000000 ................
01a0 48000000 00000000 00000000 00000000 H...............
01b0 00000000 00000000 00000000 00000000 ................
01c0 48000000 00000000 00000000 00000000 H...............
01d0 00000000 00000000 00000000 00000000 ................
01e0 48000000 00000000 00000000 00000000 H...............
01f0 00000000 00000000 00000000 00000000 ................
0200 48000000 00000000 00000000 00000000 H...............
0210 00000000 00000000 00000000 00000000 ................
0220 48000000 00000000 00000000 00000000 H...............
0230 00000000 00000000 00000000 00000000 ................
0240 48000000 00000000 00000000 00000000 H...............
0250 00000000 00000000 00000000 00000000 ................
0260 48000000 00000000 00000000 00000000 H...............
0270 00000000 00000000 00000000 00000000 ................
0280 48000000 00000000 00000000 00000000 H...............
0290 00000000 00000000 00000000 00000000 ................
02a0 48000000 00000000 00000000 00000000 H...............
02b0 00000000 00000000 00000000 00000000 ................
02c0 48000000 00000000 00000000 00000000 H...............
02d0 00000000 00000000 00000000 00000000 ................
02e0 48000000 00000000 00000000 00000000 H...............
02f0 00000000 00000000 00000000 00000000 ................
0300 48000000 00000000 00000000 00000000 H...............
0310 00000000 00000000 00000000 00000000 ................
0320 48000000 00000000 00000000 00000000 H...............
0330 00000000 00000000 00000000 00000000 ................
0340 48000000 00000000 00000000 00000000 H...............
0350 00000000 00000000 00000000 00000000 ................
0360 00000000 00000000 00000000 00000000 ................
0370 00000000 00000000 00000000 00000000 ................
0380 00000000 00000000 00000000 00000000 ................
0390 00000000 00000000 00000000 00000000 ................
03a0 00000000 00000000 00000000 00000000 ................
03b0 00000000 00000000 00000000 00000000 ................
03c0 00000000 00000000 00000000 00000000 ................
03d0 00000000 00000000 00000000 00000000 ................
03e0 00000000 00000000 00000000 00000000 ................
03f0 00000000 00000000 00000000 00000000 ................
0400 7cbe6aa6 2c250000 408200e0 3c608c00 |.j.,%..@...<`..
0410 3800001f 38400015 38800000 3900023f 8...8@..8...9..?
0420 7c7cfba6 7c4011a6 7c8009a6 7d0001a6 ||..|@..|...}...
0430 4c00012c 39400000 654a0000 614a003f L..,9@..eJ..aJ.?
0440 3800001e 38800000 64840001 60840000 8...8...d...`...
0450 39000000 65080001 61080000 6108023f 9...e...a...a..?
0460 7d4011a6 7c8009a6 7d0001a6 4c00012c }@..|...}...L..,
0470 3c608800 3800000f 3840003f 38800000 <`..8...8@.?8...
0480 3900023f 7c7cfba6 7c4011a6 7c8009a6 9..?||..|@..|...
0490 7d0001a6 4c00012c 3800000d 38800000 }...L..,8...8...
04a0 64840001 60840000 39000000 65080001 d...`...9...e...
04b0 61080000 6108023f 7d4011a6 7c8009a6 a...a..?}@..|...
04c0 7d0001a6 4c00012c 48000004 39400000 }...L..,H...9@..
04d0 654a8002 614ab000 7d400124 4c00012c eJ..aJ..}@.$L..,
04e0 802008fa 48000020 39400000 654a8002 . ..H.. 9@..eJ..
04f0 614ab000 7d400124 4c00012c 802008fe aJ..}@.$L..,. ..
0500 48000004 3c600000 60630c34 7c6903a6 H...<`..`c.4|i..
0510 7c7e6aa6 4e800421 480002e4 00000000 |~j.N..!H.......
0520 00000000 00000000 00000000 00000000 ................
0530 00000000 00000000 00000000 00000000 ................
0540 00000000 00000000 00000000 00000000 ................
0550 00000000 00000000 00000000 00000000 ................
0560 00000000 00000000 00000000 00000000 ................
0570 00000000 00000000 00000000 00000000 ................
0580 00000000 00000000 00000000 00000000 ................
0590 00000000 00000000 00000000 00000000 ................
05a0 00000000 00000000 00000000 00000000 ................
05b0 00000000 00000000 00000000 00000000 ................
05c0 00000000 00000000 00000000 00000000 ................
05d0 00000000 00000000 00000000 00000000 ................
05e0 00000000 00000000 00000000 00000000 ................
05f0 00000000 00000000 00000000 00000000 ................
0600 00000000 00000000 00000000 00000000 ................
0610 00000000 00000000 00000000 00000000 ................
0620 00000000 00000000 00000000 00000000 ................
0630 00000000 00000000 00000000 00000000 ................
0640 00000000 00000000 00000000 00000000 ................
0650 00000000 00000000 00000000 00000000 ................
0660 00000000 00000000 00000000 00000000 ................
0670 00000000 00000000 00000000 00000000 ................
0680 00000000 00000000 00000000 00000000 ................
0690 00000000 00000000 00000000 00000000 ................
06a0 00000000 00000000 00000000 00000000 ................
06b0 00000000 00000000 00000000 00000000 ................
06c0 00000000 00000000 00000000 00000000 ................
06d0 00000000 00000000 00000000 00000000 ................
06e0 00000000 00000000 00000000 00000000 ................
06f0 00000000 00000000 00000000 00000000 ................
0700 00000000 00000000 00000000 00000000 ................
0710 00000000 00000000 00000000 00000000 ................
0720 00000000 00000000 00000000 00000000 ................
0730 00000000 00000000 00000000 00000000 ................
0740 00000000 00000000 00000000 00000000 ................
0750 00000000 00000000 00000000 00000000 ................
0760 00000000 00000000 00000000 00000000 ................
0770 00000000 00000000 00000000 00000000 ................
0780 00000000 00000000 00000000 00000000 ................
0790 00000000 00000000 00000000 00000000 ................
07a0 00000000 00000000 00000000 00000000 ................
07b0 00000000 00000000 00000000 00000000 ................
07c0 00000000 00000000 00000000 00000000 ................
07d0 00000000 00000000 00000000 00000000 ................
07e0 00000000 00000000 00000000 00000000 ................
07f0 48000000 48000000 00000000 48000000 H...H.......H...
0800 48000000 00000000 00000000 00000000 H...............
0810 00000000 00000000 00000000 00000000 ................
0820 48000000 00000000 00000000 00000000 H...............
0830 00000000 00000000 00000000 00000000 ................
0840 00000000 00000000 00000000 00000000 ................
0850 00000000 00000000 00000000 00000000 ................
0860 00000000 00000000 00000000 00000000 ................
0870 00000000 00000000 00000000 00000000 ................
0880 00000000 00000000 00000000 00000000 ................
0890 00000000 00000000 00000000 00000000 ................
08a0 00000000 00000000 00000000 00000000 ................
08b0 00000000 00000000 00000000 00000000 ................
08c0 00000000 00000000 00000000 00000000 ................
08d0 00000000 00000000 00000000 00000000 ................
08e0 00000000 00000000 00000000 00000000 ................
Contents of section .rodata:
08f0 6d61696e 28256929 0a000001 fff80000 main(%i)........
0900 fff80000 08080808 08080808 08282828 .............(((
0910 28280808 08080808 08080808 08080808 ((..............
0920 08080808 a0101010 10101010 10101010 ................
0930 10101010 04040404 04040404 04041010 ................
0940 10101010 10414141 41414101 01010101 .....AAAAAA.....
0950 01010101 01010101 01010101 01010110 ................
0960 10101010 10424242 42424202 02020202 .....BBBBBB.....
0970 02020202 02020202 02020202 02020210 ................
0980 10101008 00000000 00000000 00000000 ................
0990 00000000 00000000 00000000 00000000 ................
09a0 00000000 a0101010 10101010 10101010 ................
09b0 10101010 10101010 10101010 10101010 ................
09c0 10101010 01010101 01010101 01010101 ................
09d0 01010101 01010101 01010110 01010101 ................
09e0 01010102 02020202 02020202 02020202 ................
09f0 02020202 02020202 02020210 02020202 ................
0a00 02020202 41626f72 7465642e 00000000 ....Aborted.....
0a10 30313233 34353637 38394142 43444546 0123456789ABCDEF
0a20 4748494a 4b4c4d4e 4f505152 53545556 GHIJKLMNOPQRSTUV
0a30 5758595a 00000000 30313233 34353637 WXYZ....01234567
0a40 38396162 63646566 6768696a 6b6c6d6e 89abcdefghijklmn
0a50 6f707172 73747576 7778797a 00000000 opqrstuvwxyz....
0a60 3c4e554c 4c3e0000 00001d18 00001d48 <NULL>.........H
0a70 00001d48 00001d28 00001d48 00001d48 ...H...(...H...H
0a80 00001d48 00001d48 00001d48 00001d48 ...H...H...H...H
0a90 00001d48 00001d08 00001d48 00001cf8 ...H.......H....
0aa0 00001d48 00001d48 00001d38 00002480 ...H...H...8..$.
0ab0 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0ac0 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0ad0 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0ae0 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0af0 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0b00 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0b10 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0b20 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0b30 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0b40 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0b50 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0b60 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0b70 000024e0 000024e0 000024b8 000024e0 ..$...$...$...$.
0b80 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0b90 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0ba0 000024e0 00001fbc 000024d0 000024e0 ..$.......$...$.
0bb0 000024e0 000024e0 000024e0 000024d0 ..$...$...$...$.
0bc0 000024e0 000024e0 000024e0 000024e0 ..$...$...$...$.
0bd0 00002304 000024ac 0000225c 000024e0 ..#...$..."\..$.
0be0 000024e0 000020d8 000024e0 00002558 ..$... ...$...%X
0bf0 000024e0 000024e0 000024c4 00000000 ..$...$...$.....
Contents of section .bios:
0c00 9421fff0 7c691b78 99210008 3d200001 .!..|i.x.!..= ..
0c10 81292000 39090001 3d400001 910a2000 .) .9...=@.... .
0c20 89410008 99490000 60000000 38210010 .A...I..`...8!..
0c30 4e800020 9421ffc0 7c0802a6 90010044 N.. .!..|......D
0c40 90610038 3d200001 39292000 9121000c .a.8= ..9) ..!..
0c50 3d200001 39292040 91210010 81210038 = ..9) @.!...!.8
0c60 2c090000 4182000c 3920ffff 48000190 ,...A...9 ..H...
0c70 3d200000 392936d0 91210008 48000028 = ..9)6..!..H..(
0c80 8121000c 39490004 9141000c 81410008 .!..9I...A...A..
0c90 814a0000 91490000 81210008 39290004 .J...I...!..9)..
0ca0 91210008 81410008 3d200000 39293b4c .!...A..= ..9);L
0cb0 7c0a4840 4180ffcc 3d200001 3929247c |.H@A...= ..9)$|
0cc0 91210008 48000024 81210008 39490004 .!..H..$.!..9I..
0cd0 91410008 39400000 91490000 81210008 .A..9@...I...!..
0ce0 39290004 91210008 81410008 3d200001 9)...!...A..= ..
0cf0 39292498 7c0a4840 4180ffd0 3d200000 9)$.|.H@A...= ..
0d00 38690c00 4cc63182 480026d1 38600077 8i..L.1.H.&.8`.w
0d10 48002719 38600074 48002711 38600066 H.'.8`.tH.'.8`.f
0d20 48002709 3860000a 48002701 80810038 H.'.8`..H.'....8
0d30 3d200000 386908f0 4cc63182 480028f5 = ..8i..L.1.H.(.
0d40 3d200300 91210034 81210034 7d334ba6 = ...!.4.!.4}3K.
0d50 60000000 39200000 91210030 81210030 `...9 ...!.0.!.0
0d60 7d3603a6 60000000 39200000 9121002c }6..`...9 ...!.,
0d70 8121002c 7d3d43a6 60000000 39200000 .!.,}=C.`...9 ..
0d80 91210028 81210028 7d3c43a6 60000000 .!.(.!.(}<C.`...
0d90 3d20fe00 91210024 81210024 7d3053a6 = ...!.$.!.$}0S.
0da0 60000000 7d36faa6 91210020 81210020 `...}6...!. .!.
0db0 552905ea 9121001c 8121001c 7d36fba6 U)...!...!..}6..
0dc0 60000000 39200000 91210018 81210018 `...9 ...!...!..
0dd0 7d3053a6 60000000 39200000 91210014 }0S.`...9 ...!..
0de0 81210014 7d3453a6 60000000 81210010 .!..}4S.`....!..
0df0 7d234b78 4801136c 48000000 7d234b78 }#KxH..lH...}#Kx
0e00 80010044 7c0803a6 38210040 4e800020 ...D|...8!.@N..
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0ef0 552a103a 3d200001 39292340 7d2a4a14 U*.:= ..9)#@}*J.
0f00 81290000 91210010 81210008 552a103a .)...!...!..U*.:
0f10 3d200001 392923e0 7d2a4a14 81290000 = ..9)#.}*J..)..
0f20 55290644 91210014 8121000c 2c090000 U).D.!...!..,...
0f30 4182001c 81410010 81210014 7c0a4800 A....A...!..|.H.
0f40 4082000c 39200001 48000008 39200000 @...9 ..H...9 ..
0f50 9121000c 8121000c 2c090000 40820010 .!...!..,...@...
0f60 81210008 7d234b78 4bfff88d 39200022 .!..}#KxK...9 ."
0f70 91210008 4800008c 81210008 552a103a .!..H....!..U*.:
0f80 3d200001 39292340 7d2a4a14 81290000 = ..9)#@}*J..)..
0f90 91210010 81210008 552a103a 3d200001 .!...!..U*.:= ..
0fa0 392923e0 7d2a4a14 81290000 91210014 9)#.}*J..)...!..
0fb0 8121000c 2c090000 4182001c 81410010 .!..,...A....A..
0fc0 81210014 7c0a4800 4082000c 39200001 .!..|.H.@...9 ..
0fd0 48000008 39200000 9121000c 8121000c H...9 ...!...!..
0fe0 2c090000 40820010 81210008 7d234b78 ,...@....!..}#Kx
0ff0 4bfff805 81210008 39290001 91210008 K....!..9)...!..
1000 81210008 28090023 4081ff70 4bfff7e5 .!..(..#@..pK...
1010 48000000 9421fff0 90610008 9081000c H....!...a......
1020 48011234 60000000 38210010 4e800020 H..4`...8!..N..
1030 48000000 H...
Contents of section .text:
1034 9421fff0 7c691b78 99210008 89210008 .!..|i.x.!...!..
1044 3d400000 394a0904 7d2a48ae 552907bc =@..9J..}*H.U)..
1054 2c090000 41820010 89210008 3929ffe0 ,...A....!..9)..
1064 99210008 89210008 7d234b78 38210010 .!...!..}#Kx8!..
1074 4e800020 9421fff0 7c691b78 b1210008 N.. .!..|i.x.!..
1084 a1210008 5529402e 7d2a0734 a1210008 .!..U)@.}*.4.!..
1094 5529c23e 5529043e 7d290734 7d494b78 U).>U).>}).4}IKx
10a4 7d290734 5529043e 7d234b78 38210010 }).4U).>}#Kx8!..
10b4 4e800020 9421fff0 90610008 81210008 N.. .!...a...!..
10c4 552a463e 81210008 5529c23e 5529042e U*F>.!..U).>U)..
10d4 7d4a4b78 81210008 5529402e 5529021e }JKx.!..U)@.U)..
10e4 7d4a4b78 81210008 5529c00e 7d494b78 }JKx.!..U)..}IKx
10f4 7d234b78 38210010 4e800020 9421fff0 }#Kx8!..N.. .!..
1104 90610008 9081000c 48000028 81210008 .a......H..(.!..
1114 89290000 2c090000 4082000c 39200000 .)..,...@...9 ..
1124 4800002c 81210008 39290001 91210008 H..,.!..9)...!..
1134 81210008 89490000 8121000c 5529063e .!...I...!..U).>
1144 7c0a4840 4082ffc8 81210008 7d234b78 |.H@@....!..}#Kx
1154 38210010 4e800020 9421ffe0 90610018 8!..N.. .!...a..
1164 9081001c 81210018 91210008 48000058 .....!...!..H..X
1174 8121001c 9121000c 48000030 81210008 .!...!..H..0.!..
1184 89490000 8121000c 89290000 7c0a4840 .I...!...)..|.H@
1194 4082000c 81210008 48000040 8121000c @....!..H..@.!..
11a4 39290001 9121000c 8121000c 89290000 9)...!...!...)..
11b4 2c090000 4082ffc8 81210008 39290001 ,...@....!..9)..
11c4 91210008 81210008 89290000 2c090000 .!...!...)..,...
11d4 4082ffa0 39200000 7d234b78 38210020 @...9 ..}#Kx8!.
11e4 4e800020 9421ffe0 7c0802a6 90010024 N.. .!..|......$
11f4 90610018 9081001c 80610018 480003dd .a.......a..H...
1204 7c6a1b78 81210018 7d295214 91210008 |j.x.!..})R..!..
1214 81210008 89490000 8121001c 5529063e .!...I...!..U).>
1224 7c0a4840 4082000c 81210008 48000024 |.H@@....!..H..$
1234 81210008 3929ffff 91210008 81410008 .!..9)...!...A..
1244 81210018 7c0a4840 4080ffc8 39200000 .!..|.H@@...9 ..
1254 7d234b78 80010024 7c0803a6 38210020 }#Kx...$|...8!.
1264 4e800020 9421ffe0 90610008 9081000c N.. .!...a......
1274 90a10010 48000030 81210008 89490000 ....H..0.!...I..
1284 81210010 5529063e 7c0a4840 4082000c .!..U).>|.H@@...
1294 81210008 48000038 81210008 39290001 .!..H..8.!..9)..
12a4 91210008 8121000c 3949ffff 9141000c .!...!..9I...A..
12b4 2c090000 41820014 81210008 89290000 ,...A....!...)..
12c4 2c090000 4082ffb4 39200000 7d234b78 ,...@...9 ..}#Kx
12d4 38210020 4e800020 9421ffe0 90610018 8!. N.. .!...a..
12e4 9081001c 81210018 91210008 60000000 .....!...!..`...
12f4 8141001c 392a0001 9121001c 81210018 .A..9*...!...!..
1304 39090001 91010018 894a0000 99490000 9........J...I..
1314 89290000 2c090000 4082ffd8 81210008 .)..,...@....!..
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3564 38210010 4e800020 9421fff0 7c0802a6 8!..N.. .!..|...
3574 90010014 90610008 48000020 81210008 .....a..H.. .!..
3584 89290000 7d234b78 4bfffe9d 81210008 .)..}#KxK....!..
3594 39290001 91210008 81210008 89290000 9)...!...!...)..
35a4 2c090000 4082ffd8 60000000 60000000 ,...@...`...`...
35b4 80010014 7c0803a6 38210010 4e800020 ....|...8!..N..
35c4 9421fee0 7c0802a6 90010124 90610118 .!..|......$.a..
35d4 9081011c 3921000c 80c1011c 80a10118 ....9!..........
35e4 38800100 7d234b78 4bffebf9 7c691b78 8...}#KxK...|i.x
35f4 91210008 3941000c 81210008 7d2a4a14 .!..9A...!..}*J.
3604 39400000 99490000 3921000c 7d234b78 9@...I..9!..}#Kx
3614 4bffff59 81210008 7d234b78 80010124 K..Y.!..}#Kx...$
3624 7c0803a6 38210120 4e800020 9421ff80 |...8!. N.. .!..
3634 7c0802a6 90010084 90610018 90810024 |........a.....$
3644 90a10028 90c1002c 90e10030 91010034 ...(...,...0...4
3654 91210038 9141003c 40860024 d8210040 .!.8.A.<@..$.!.@
3664 d8410048 d8610050 d8810058 d8a10060 .A.H.a.P...X...`
3674 d8c10068 d8e10070 d9010078 39200001 ...h...p...x9 ..
3684 9921000c 39200000 9921000d 39210088 .!..9 ...!..9!..
3694 91210010 39210020 91210014 3921000c .!..9!. .!..9!..
36a4 7d244b78 80610018 4bffff19 7c691b78 }$Kx.a..K...|i.x
36b4 91210008 81210008 7d234b78 80010084 .!...!..}#Kx....
36c4 7c0803a6 38210080 4e800020 |...8!..N..
Contents of section .data:
12000 0001c000 00000000 00000000 00000000 ................
12010 00000000 00000000 00000000 00000000 ................
12020 696e666f 20746578 74006865 61646572 info text.header
12030 20746578 74000000 00000000 00000000 text...........
12040 00000000 5822c905 ffffffff 91b6d1a3 ....X"..........
12050 ffffffff ffffffff ffffffff ffffffff ................
12060 ffffffff 7e11ee88 ffffffff 7fffffff ....~...........
12070 ffffffff ffffffff 8c20bde6 ffffffff ......... ......
12080 76d0dadf 15111f42 ffffffff 36108e50 v......B....6..P
12090 ffffffff ffffffff 328a0ced ffffffff ........2.......
120a0 ffffffff af224c19 ffffffff ffffffff ....."L.........
120b0 d624b27a ffffffff ffffffff ffffffff .$.z............
120c0 dbfd3628 89f0006e ffffffff ffffffff ..6(...n........
120d0 ffffffff 00001104 00010000 00000000 ................
120e0 0000000d 7c61cc14 7d230595 7ac37392 ....|a..}#..z.s.
120f0 7e094c11 7e1cb115 7a338886 7c6004d1 ~.L.~...z3..|`..
12100 7e09b038 7c360591 7e2b00d1 60000000 ~..8|6..~+..`...
12110 60000000 60000000 00010000 00010004 `...`...........
12120 00010008 0001000c 00010010 00010014 ................
12130 00010018 0001001c 00010020 00010024 ........... ...$
12140 00010028 0001002c 00010030 48000014 ...(...,...0H...
12150 60000000 60000000 60000000 60000000 `...`...`...`...
12160 9023009c 802300a0 7c2903a6 382300a4 .#...#..|)..8#..
12170 384300d8 80810000 80a20000 90850000 8C..............
12180 38210004 38420004 4200ffec 3c804800 8!..8B..B...<.H.
12190 60840006 90850000 80230094 7c3b03a6 `........#..|;..
121a0 80230098 7c3a03a6 80230080 7c2ff120 .#..|:...#..|/.
121b0 80230084 7c2103a6 80230088 7c2903a6 .#..|!...#..|)..
121c0 8023008c 7c2803a6 80230090 7c2fcba6 .#..|(...#..|/..
121d0 80030000 80230004 80430008 80830010 .....#...C......
121e0 80a30014 80c30018 80e3001c 81030020 ...............
121f0 81230024 81430028 8163002c 81830030 .#.$.C.(.c.,...0
12200 81a30034 81c30038 81e3003c 82030040 ...4...8...<...@
12210 82230044 82430048 8263004c 82830050 .#.D.C.H.c.L...P
12220 82a30054 82c30058 82e3005c 83030060 ...T...X...\...`
12230 83230064 83430068 8363006c 83830070 .#.d.C.h.c.l...p
12240 83a30074 83c30078 83e3007c 8063000c ...t...x...|.c..
12250 4c000064 4800000c 60000000 60000000 L..dH...`...`...
12260 7c2fcba6 3c200001 60212340 90010000 |/..< ..`!#@....
12270 90410008 9061000c 90810010 90a10014 .A...a..........
12280 90c10018 90e1001c 91010020 91210024 ........... .!.$
12290 91410028 9161002c 91810030 91a10034 .A.(.a.,...0...4
122a0 91c10038 91e1003c 92010040 92210044 ...8...<...@.!.D
122b0 92410048 9261004c 92810050 92a10054 .A.H.a.L...P...T
122c0 92c10058 92e1005c 93010060 93210064 ...X...\...`.!.d
122d0 93410068 9361006c 93810070 93a10074 .A.h.a.l...p...t
122e0 93c10078 93e1007c 7c4fcaa6 90410004 ...x...||O...A..
122f0 7c400026 90410080 7c4102a6 90410084 |@.&.A..|A...A..
12300 7c4902a6 90410088 7c4802a6 9041008c |I...A..|H...A..
12310 7c4fcaa6 90410090 3c600001 60632040 |O...A..<`..`c @
12320 8023009c 3c600867 60635309 48000e13 .#..<`.g`cS.H...
12330 60000000 60000000 60000000 60000000 `...`...`...`...
12340 ffffffff ffffffff ffffffff ffffffff ................
12350 ffffffff ffffffff ffffffff ffffffff ................
12360 ffffffff ffffffff ffffffff ffffffff ................
12370 ffffffff ffffffff ffffffff ffffffff ................
12380 ffffffff ffffffff ffffffff ffffffff ................
12390 ffffffff ffffffff ffffffff ffffffff ................
123a0 ffffffff ffffffff ffffffff ffffffff ................
123b0 ffffffff ffffffff ffffffff ffffffff ................
123c0 ffffffff ffffffff ffffffff ffffffff ................
123d0 ffffffff 60000000 60000000 60000000 ....`...`...`...
123e0 00000000 cd75f313 ffffffff 00000000 .....u..........
123f0 ffffffff ffffffff ffffffff ffffffff ................
12400 ffffffff 008a0c68 ffffffff 7fffffff .......h........
12410 ffffffff ffffffff 8c20bde6 ffffffff ......... ......
12420 08aebf68 80000001 ffffffff 00000000 ...h............
12430 ffffffff ffffffff 328a0ced ffffffff ........2.......
12440 ffffffff af224c19 ffffffff ffffffff ....."L.........
12450 d624b27a ffffffff ffffffff ffffffff .$.z............
12460 9bfd3628 98f0006e ffffffff ffffffff ..6(...n........
12470 ffffffff 00001104 00010038 ...........8

1
dev/src/test3_soc/test3
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../../sim/mem/test3
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