* runs simple version of kernel/bios/random test with cocotb (A2L2 interface partially implemented in Python) and Verilog core wrapper (A2L2<->mem interface)
* runs simple version of kernel/bios/random test with cocotb (A2L2 interface partially implemented in Python) and Verilog core wrapper (A2L2<->mem interface)
* wrapper converts A2L2 interface to mem and Wishbone interfaces
* verilator builds, but does not simulate correctly
* verilator builds, but does not simulate correctly
## To Do
## To Do
* continue with cocotb testing
* continue with cocotb testing
* add A2Node bridge to WB, and Litex wrapper
* experiment with parameters to create smaller version(s) for OpenLane
* experiment with parameters to create smaller version(s) for OpenLane
openpowerwtf
2 years ago