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make mem visible in iverilog dump

pd
openpowerwtf 5 months ago
parent
commit
975bb2445d
  1. 12
      dev/verilog/trilib_clk1x/tri_144x78_2r4w.v

12
dev/verilog/trilib_clk1x/tri_144x78_2r4w.v

@ -105,6 +105,18 @@ module tri_144x78_2r4w( @@ -105,6 +105,18 @@ module tri_144x78_2r4w(
mem[i] = 0;
end

//wtf:icarus $dumpvars cannot dump a vpiMemory
generate
genvar j;
for (j = 0; j < 144; j=j+1) begin: loc
wire [64-`GPR_WIDTH:63] dat;
wire [0:7] par;
// 4b0
assign dat = mem[j][64-`GPR_WIDTH:63];
assign par = mem[j][64:63 + `GPR_WIDTH/8];
end
endgenerate

assign r1a_d = r_addr_in_1;
assign r2a_d = r_addr_in_2;


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