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litex

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pull/18/head
openpowerwtf 2 years ago
parent 1562980638
commit 9cca046fa4
4 changed files with 7857 additions and 12314 deletions
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10
dev/sim/coco/A2O.py
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@ -287,28 +287,28 @@ async def A2OMonitor(dut, sim):
for i in range(36): for i in range(36):
good, arch = sim.safeint(gprCompMap[i].value.binstr, 2, rc=True) good, arch = sim.safeint(gprCompMap[i].value.binstr, 2, rc=True)
if good and arch != lastGprCompMap[i]: if good and arch != lastGprCompMap[i]:
sim.msg(f'GPR Update: R{i:02d}={hex(gpr[arch], 16)}') sim.msg(f'C0: GPR Update: R{i:02d}={hex(gpr[arch], 16)}')
lastGprCompMap[i] = arch lastGprCompMap[i] = arch
for i in range(8): for i in range(8):
good, arch = sim.safeint(crCompMap[i].value.binstr, 2, rc=True) good, arch = sim.safeint(crCompMap[i].value.binstr, 2, rc=True)
if good and arch != lastCrCompMap[i]: if good and arch != lastCrCompMap[i]:
sim.msg(f'CR Update: F{i:01d}={hex(cr[arch], 1)}') sim.msg(f'C0: CR Update: F{i:01d}={hex(cr[arch], 1)}')
lastCrCompMap[i] = arch lastCrCompMap[i] = arch
for i in range(1): for i in range(1):
good, arch = sim.safeint(xerCompMap[i].value.binstr, 2, rc=True) good, arch = sim.safeint(xerCompMap[i].value.binstr, 2, rc=True)
if good and arch != lastXerCompMap[i]: if good and arch != lastXerCompMap[i]:
v = xer[arch].value.binstr v = xer[arch].value.binstr
sim.msg(f'XER Update: SO/OV/CA={v[0:3]} LEN={int(v[3:],2):02X}') sim.msg(f'C0: XER Update: SO/OV/CA={v[0:3]} LEN={int(v[3:],2):02X}')
lastXerCompMap[i] = arch lastXerCompMap[i] = arch
for i in range(1): for i in range(1):
good, arch = sim.safeint(ctrCompMap[i].value.binstr, 2, rc=True) good, arch = sim.safeint(ctrCompMap[i].value.binstr, 2, rc=True)
if good and arch != lastCtrCompMap[i]: if good and arch != lastCtrCompMap[i]:
sim.msg(f'CTR Update:{hex(ctr[arch], 16)}') sim.msg(f'C0: CTR Update:{hex(ctr[arch], 16)}')
lastCtrCompMap[i] = arch lastCtrCompMap[i] = arch
for i in range(1): for i in range(1):
good, arch = sim.safeint(lrCompMap[i].value.binstr, 2, rc=True) good, arch = sim.safeint(lrCompMap[i].value.binstr, 2, rc=True)
if good and arch != lastLrCompMap[i]: if good and arch != lastLrCompMap[i]:
sim.msg(f'LR Update:{hex(lr[arch], 16)}') sim.msg(f'C0: LR Update:{hex(lr[arch], 16)}')
lastLrCompMap[i] = arch lastLrCompMap[i] = arch


sim.msg(f'{me}: ended.') sim.msg(f'{me}: ended.')

42
dev/sim/coco/cocotb_litex.v
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@ -5,23 +5,27 @@


module cocotb ( module cocotb (


input clk_1x, input clk_1x,
input clk_2x, input clk_2x,
input rst, input rst,


input timerInterrupt, input [0:31] cfg_dat,
input externalInterrupt, input cfg_wr,
input softwareInterrupt, output [0:31] status,
input externalInterruptS,

input timerInterrupt,
output wb_stb, input externalInterrupt,
output wb_cyc, input softwareInterrupt,
output [31:0] wb_adr, input externalInterruptS,
output wb_we,
output [3:0] wb_sel, output wb_stb,
output [31:0] wb_datw, output wb_cyc,
input wb_ack, output [31:0] wb_adr,
input [31:0] wb_datr output wb_we,
output [3:0] wb_sel,
output [31:0] wb_datw,
input wb_ack,
input [31:0] wb_datr


); );


@ -30,6 +34,10 @@ a2owb c0 (
.clk_2x(clk_2x), .clk_2x(clk_2x),
.rst(rst), .rst(rst),


.cfg_wr(cfg_wr),
.cfg_dat(cfg_dat),
.status(status),

.timerInterrupt(timerInterrupt), .timerInterrupt(timerInterrupt),
.externalInterrupt(externalInterrupt), .externalInterrupt(externalInterrupt),
.softwareInterrupt(softwareInterrupt), .softwareInterrupt(softwareInterrupt),

20099
dev/sim/coco/sim.txt
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File diff suppressed because it is too large Load Diff

20
dev/sim/coco/tb_node.py
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@ -467,6 +467,7 @@ async def tb_litex(dut):
sim = Sim(dut) sim = Sim(dut)
sim.mem = Memory(sim) sim.mem = Memory(sim)
sim.maxCycles = 20000 sim.maxCycles = 20000
sim.resetAddr = None # set to 00000000 in rtl define


# rom+bios+arcitst # rom+bios+arcitst
sim.memFiles = [ sim.memFiles = [
@ -476,7 +477,7 @@ async def tb_litex(dut):
} }
] ]


for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc. for i in range(len(sim.memFiles)):
sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr']) sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])


if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default: if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
@ -484,11 +485,11 @@ async def tb_litex(dut):
sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.') sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')


# init stuff # init stuff
#await init(dut, sim) dut.externalInterrupt.value = 0
dut.externalInterrupt.value = 0; dut.externalInterruptS.value = 0
dut.externalInterruptS.value = 0; dut.timerInterrupt.value = 0
dut.timerInterrupt.value = 0; dut.softwareInterrupt.value = 0
dut.softwareInterrupt.value = 0; dut.cfg_wr.value = 0


# start clocks,reset # start clocks,reset
await cocotb.start(genClocksLitex(dut, sim)) await cocotb.start(genClocksLitex(dut, sim))
@ -550,13 +551,6 @@ async def tb_litex(dut):
await cocotb.start(A2O.checker(dut, sim)) await cocotb.start(A2O.checker(dut, sim))
await cocotb.start(A2O.monitor(dut, sim)) await cocotb.start(A2O.monitor(dut, sim))


#await cocotb.start(checker(dut, sim))

# release thread(s)
#dut.an_ac_pm_thread_stop.value = 0
#await RisingEdge(dut.clk_1x)
#dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')

# should await sim.done # should await sim.done
await Timer((sim.maxCycles+100)*8, units='ns') await Timer((sim.maxCycles+100)*8, units='ns')



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