
4 changed files with 315 additions and 67 deletions
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@@ -0,0 +1,201 @@
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# A2O Core |
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import cocotb |
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from cocotb.triggers import Timer, RisingEdge |
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from cocotb.binary import BinaryValue |
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from cocotb.handle import Force |
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from cocotb.handle import Release |
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from dotmap import DotMap |
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import itertools |
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from OPEnv import * |
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# ------------------------------------------------------------------------------------------------ |
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# Tasks |
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async def A2ODriver(dut, sim): |
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"""A2O Core Driver""" |
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transTypes = { |
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'00': 'IFETCH', |
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'08': 'LOAD', |
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'20': 'STORE' |
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} |
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ok = True |
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readPending = [] |
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countReads = 0 |
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mem = {} |
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sim.msg('A2O Driver: nothing to do.') |
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#while ok and not sim.done: |
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# await RisingEdge(dut.clk_1x) |
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# A2O Checker |
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# check protocol, etc. |
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async def A2OChecker(dut, sim): |
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"""A2O Core Checker """ |
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me = 'A2O Checker' |
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ok = True |
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sim.msg(f'{me}: started.') |
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# errors |
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creditsLdErr = dut.c0.lq0.lsq.arb.ld_cred_err_q |
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creditsStErr = dut.c0.lq0.lsq.arb.st_cred_err_q |
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errors = [ |
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{'name': 'Load Credits', 'sig': creditsLdErr}, |
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{'name': 'Store Credits', 'sig': creditsStErr}, |
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] |
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while ok: |
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await RisingEdge(dut.clk_1x) |
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if not sim.resetDone: |
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continue |
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for i in range(len(errors)): |
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assert errors[i]['sig'].value == 0, f'{me} Error: {errors[i]["name"]}' |
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# A2O Monitor |
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# count transactions, etc. |
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# fail on bad addresses |
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async def A2OMonitor(dut, sim): |
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"""A2O Core Monitor""" |
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me = 'A2O Monitor' |
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ok = True |
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sim.msg(f'{me}: started.') |
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# completions |
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iu0Comp = dut.c0.iu_lq_i0_completed |
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iu0CompIFAR = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar |
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iu1Comp = dut.c0.iu_lq_i1_completed |
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iu1CompIFAR = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar |
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iuCompFlushIFAR = dut.c0.cp_t0_flush_ifar |
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cp3NIA = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp3_nia_q # nia after last cycle's completions |
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# GPR ppol and arch map |
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gprCompMap = [] |
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lastGprCompMap = [] |
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#wtf check what 33:36 are! |
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for i in range(36): |
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gprCompMap.append(dut.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout) |
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lastGprCompMap.append(i) |
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gpr = [] |
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for i in range(144): |
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gpr.append(dut.c0.xu0.gpr.gpr0.loc[i].dat) |
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# CR fields pool and arch map |
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crCompMap = [] |
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lastCrCompMap = [] |
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for i in range(8): |
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crCompMap.append(dut.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.cr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout) |
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lastCrCompMap.append(i) |
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cr = [] |
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for i in range(24): |
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cr.append(dut.c0.xu0.cr.entry[i].reg_latch.dout) |
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# XER pool and arch map |
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xerCompMap = [] |
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lastXerCompMap = [] |
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for i in range(1): |
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xerCompMap.append(dut.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout) |
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lastXerCompMap.append(i) |
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xer = [] |
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for i in range(12): |
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xer.append(dut.c0.xu0.xer.entry[i].reg_latch.dout) |
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# CTR pool and arch map |
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ctrCompMap = [] |
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lastCtrCompMap = [] |
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for i in range(1): |
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ctrCompMap.append(dut.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout) |
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lastCtrCompMap.append(i) |
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ctr = [] |
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for i in range(8): |
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ctr.append(dut.c0.xu0.ctr.entry[i].reg_latch.dout) |
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# LR pool and arch map |
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lrCompMap = [] |
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lastLrCompMap = [] |
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for i in range(1): |
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lrCompMap.append(dut.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.lr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout) |
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lastLrCompMap.append(i) |
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lr = [] |
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for i in range(8): |
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lr.append(dut.c0.xu0.lr.entry[i].reg_latch.dout) |
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while ok: |
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await RisingEdge(dut.clk_1x) |
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if not sim.resetDone: |
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continue |
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comp = '' |
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#wtf seeing something weird here |
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# there are cases where x's are in some bits of comp ifar's; maybe ok (predict array?) but why is completed indicated? |
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if iu0Comp.value == 1: |
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comp = f'0:{sim.safeint(iu0CompIFAR.value.binstr + "00", 2):06X} ' |
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if iu1Comp.value == 1: |
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comp = f'{comp}1:{sim.safeint(iu1CompIFAR.value.binstr + "00", 2):06X} ' |
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if comp != '': |
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comp = f'{comp}{sim.safeint(iuCompFlushIFAR.value.binstr + "00", 2):016X}' |
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sim.msg(f'C0: CP {comp}') |
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if sim.a2o.traceFacUpdates: |
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# renamables |
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for i in range(36): |
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good, arch = sim.safeint(gprCompMap[i].value.binstr, 2, rc=True) |
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if good and arch != lastGprCompMap[i]: |
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sim.msg(f'GPR Update: R{i:02d}={hex(gpr[arch], 16)}') |
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lastGprCompMap[i] = arch |
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for i in range(8): |
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good, arch = sim.safeint(crCompMap[i].value.binstr, 2, rc=True) |
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if good and arch != lastCrCompMap[i]: |
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sim.msg(f'CR Update: F{i:01d}={hex(cr[arch], 1)}') |
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lastCrCompMap[i] = arch |
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for i in range(1): |
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good, arch = sim.safeint(xerCompMap[i].value.binstr, 2, rc=True) |
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if good and arch != lastXerCompMap[i]: |
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v = xer[arch].value.binstr |
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sim.msg(f'XER Update: SO/OV/CA={v[0:3]} LEN={int(v[3:],2):02X}') |
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lastXerCompMap[i] = arch |
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for i in range(1): |
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good, arch = sim.safeint(ctrCompMap[i].value.binstr, 2, rc=True) |
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if good and arch != lastCtrCompMap[i]: |
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sim.msg(f'CTR Update:{hex(ctr[arch], 16)}') |
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lastCtrCompMap[i] = arch |
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for i in range(1): |
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good, arch = sim.safeint(lrCompMap[i].value.binstr, 2, rc=True) |
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if good and arch != lastLrCompMap[i]: |
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sim.msg(f'LR Update:{hex(lr[arch], 16)}') |
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lastLrCompMap[i] = arch |
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# ------------------------------------------------------------------------------------------------ |
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# Classes |
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class A2O: |
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driver = A2ODriver |
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checker = A2OChecker |
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monitor = A2OMonitor |
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def __init__(self, sim): |
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pass |
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class A2OCore(DotMap): |
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def __init__(self, sim): |
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super().__init__() |
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self.sim = sim |
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self.traceFacUpdates = False |
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