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pd
openpowerwtf 1 year ago
parent 7043a1645b
commit b0efaecf46
21 changed files with 61 additions and 60 deletions
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5
dev/verilog/trilib/tri_a2o.vh
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@ -135,9 +135,10 @@

//wtf: change for verilatorsim - didnt help
//`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
//`define INIT_IUCR0 16'h00FA // BP enabled
`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
`define INIT_IUCR0 16'h0000 // BP disabled
//`define INIT_IUCR0 16'h0000 // BP disabled
`define INIT_IUCR0 16'h00FA // BP enabled


`define INIT_MASK 2'b10
`define RELQ_INCLUDE 0 // Reload Queue Included

2
dev/verilog/trilib/tri_bht_512x4_1r1w.v
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@ -216,7 +216,7 @@ module tri_bht_512x4_1r1w(
wire force_t;

wire [0:scan_right] siv;
wire [0:scan_right] sov;
wire [0:scan_right] sov /*verilator split_var*/;

wire tiup;


8
dev/verilog/work/fu_alg_add.v
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@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

@ -118,7 +118,7 @@ module fu_alg_add(

parameter tiup = 1'b1;
parameter tidn = 1'b0;
wire [2:14] ex2_bsha_sim_c;
wire [2:14] ex2_bsha_sim_c /*verilator split_var*/;
wire [1:13] ex2_bsha_sim_p;
wire [2:13] ex2_bsha_sim_g;
wire [1:13] ex2_bsha_sim;

8
dev/verilog/work/fu_hc16pp_lsb.v
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@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

@ -52,7 +52,7 @@ module fu_hc16pp_lsb(
wire [0:12] g01_b;
wire [0:13] t01_b;
wire [0:13] p01_b;
wire [0:13] p01;
wire [0:13] p01 /*verilator split_var*/;

wire [0:5] g01od;
wire [0:6] t01od;

10
dev/verilog/work/fu_oscr.v
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@ -362,7 +362,7 @@ module fu_oscr(
wire [0:23] ex7_mrg;
wire [0:3] ex7_mrg_dfp;
wire [0:3] ex7_fpscr_dfp_din;
wire [0:23] ex7_fpscr_din;
wire [0:23] ex7_fpscr_din /*verilator split_var*/;
wire ex7_fpscr_din1_thr0;
wire ex7_fpscr_din1_thr1;
wire [0:3] ex7_cr_fld;
@ -521,10 +521,10 @@ module fu_oscr(
wire re0_2_thr1;
wire re1_2_thr1;

wire [28:63] cfpscr_thr0_din;
wire [28:63] cfpscr_thr1_din;
wire [28:63] cfpscr_thr0_din_i0;
wire [28:63] cfpscr_thr1_din_i0;
wire [28:63] cfpscr_thr0_din /*verilator split_var*/;
wire [28:63] cfpscr_thr1_din /*verilator split_var*/;
wire [28:63] cfpscr_thr0_din_i0 /*verilator split_var*/;
wire [28:63] cfpscr_thr1_din_i0 /*verilator split_var*/;

wire [28:63] cfpscr_thr0_l2;
wire [28:63] cfpscr_thr1_l2;

8
dev/verilog/work/iuq_bp.v
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@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

@ -795,7 +795,7 @@ wire [0:1] bcache_bh1_hist;
wire [0:1] bcache_bh0_wr_data;
wire [0:1] bcache_bh1_wr_data;
wire [0:11] bcache_wr_addr;
wire [0:15] bcache_data_new;
wire [0:15] bcache_data_new /*verilator split_var*/;
wire [0:15] bcache_data0_d;
wire [0:15] bcache_data0_q;
wire [0:15] bcache_data1_d;

8
dev/verilog/work/iuq_ibuf.v
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@ -127,7 +127,7 @@ module iuq_ibuf(
// buffer latches
reg [0:IBUFF_WIDTH-1] buffer_data_din[0:`IBUFF_DEPTH-1];
reg [0:IBUFF_WIDTH-1] buffer_data_d[0:`IBUFF_DEPTH-1];
reg [0:IBUFF_WIDTH-1] buffer_data_q[0:`IBUFF_DEPTH-1];
reg [0:IBUFF_WIDTH-1] buffer_data_q[0:`IBUFF_DEPTH-1] /*verilator split_var*/;
wire buffer_valid_act;
wire [0:`IBUFF_DEPTH-1] buffer_valid_din;
wire [0:`IBUFF_DEPTH-1] buffer_valid_d;
@ -173,15 +173,15 @@ module iuq_ibuf(

// data/valid out
wire [0:1] valid_int;
wire [0:1] valid_out;
wire [0:1] valid_out /*verilator split_var*/;
wire [0:IDATA_WIDTH-1] data0_out;
wire [0:IDATA_WIDTH-1] data1_out;
wire [0:IBUFF_WIDTH-1] buffer0_ibuff_data;
wire [0:IBUFF_WIDTH-1] buffer1_ibuff_data;
wire [0:IDATA_WIDTH-1] buffer0_data;
wire [0:IDATA_WIDTH-1] buffer1_data;
reg [0:IBUFF_WIDTH-1] buffer0_data_muxed[0:`IBUFF_DEPTH-1];
reg [0:IBUFF_WIDTH-1] buffer1_data_muxed[0:`IBUFF_DEPTH-1];
reg [0:IBUFF_WIDTH-1] buffer0_data_muxed[0:`IBUFF_DEPTH-1] /*verilator split_var*/;
reg [0:IBUFF_WIDTH-1] buffer1_data_muxed[0:`IBUFF_DEPTH-1] /*verilator split_var*/;

// output latches
wire iu4_0_valid_din;

4
dev/verilog/work/iuq_ic.v
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@ -500,8 +500,8 @@ module iuq_ic(

wire [0:scan_right] siv;
wire [0:scan_right] sov;
wire [0:1] tsiv; // time scan path
wire [0:1] tsov; // time scan path
wire [0:1] tsiv /*verilator split_var*/; // time scan path
wire [0:1] tsov /*verilator split_var*/; // time scan path
wire func_scan_in_cam;
wire func_scan_out_cam;


2
dev/verilog/work/iuq_ic_dir.v
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@ -563,7 +563,7 @@ module iuq_ic_dir(
wire stage_abist_g6t_r_wb;

// scan
wire [0:scan_right] siv;
wire [0:scan_right] siv /*verilator split_var*/;
wire [0:scan_right] sov;
wire [0:44] abst_siv;
wire [0:44] abst_sov;

2
dev/verilog/work/iuq_ic_miss.v
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@ -426,7 +426,7 @@ module iuq_ic_miss(
wire miss_thread_has_idle;

wire release_sm;
wire [0:SM_MAX-1] release_sm_hold;
wire [0:SM_MAX-1] release_sm_hold /*verilator split_var*/;

// IU0 inval
wire [0:TAGS_USED-1] iu0_inval_match;

2
dev/verilog/work/iuq_ic_select.v
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@ -397,7 +397,7 @@ module iuq_ic_select(
wire [0:`THREADS-1] iu0_erat_tid;

wire [0:`THREADS-1] need_fetch_reduce;
reg [0:(`IBUFF_DEPTH/4)-1] need_fetch[0:`THREADS-1];
reg [0:(`IBUFF_DEPTH/4)-1] need_fetch[0:`THREADS-1] /*verilator split_var*/;
reg [0:(`IBUFF_DEPTH/4)-1] next_fetch[0:`THREADS-1];
reg [0:(`IBUFF_DEPTH/4)-2] shift1_sent[0:`THREADS-1];
reg [0:`THREADS-1] shift1_sent_reduce;

2
dev/verilog/work/lq_pfetch.v
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@ -426,7 +426,7 @@ module lq_pfetch(
wire [0:1] rpt_rd_act;
wire [0:1] rpt_byp_val;
wire [0:4] rpt_wrt_addr;
wire [0:69] rpt_data_in;
wire [0:69] rpt_data_in /*verilator split_var*/;
wire [0:4] rpt_rd_addr;
wire [0:139] rpt_data_out;
wire [0:69] rpt_byp_dat_d;

2
dev/verilog/work/lq_stq.v
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@ -1347,7 +1347,7 @@ module lq_stq(
wire perf_stq_cmmt_attmpt;
wire perf_stq_cmmt_val;
wire perf_stq_need_hole;
wire [0:15] stq_rotcmp;
wire [0:15] stq_rotcmp /*verilator split_var*/;
wire [0:`STQ_ENTRIES] ex3_agecmp;
wire [0:3] ex4_rot_sel_be[0:`STQ_ENTRIES-1];
wire [0:3] ex4_rot_sel_le[0:`STQ_ENTRIES-1];

6
dev/verilog/work/mmq.v
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@ -585,9 +585,9 @@ module mmq(
wire mm_xu_lsu_ind_sig;
wire mm_xu_lsu_lbit_sig;
wire [64-`RS_DATA_WIDTH:63] xu_mm_ex2_eff_addr_sig;
wire [0:5] repr_scan_int;
wire [0:5] time_scan_int;
wire [0:6] abst_scan_int;
wire [0:5] repr_scan_int /*verilator split_var*/;
wire [0:5] time_scan_int /*verilator split_var*/;
wire [0:6] abst_scan_int /*verilator split_var*/;
wire tlbwe_back_inv_valid_sig;
wire [0:`MM_THREADS-1] tlbwe_back_inv_thdid_sig;
wire [52-`EPN_WIDTH:51] tlbwe_back_inv_addr_sig;

2
dev/verilog/work/mmq_inval.v
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@ -557,7 +557,7 @@ module mmq_inval(
wire [52-`EPN_WIDTH:51] snoop_vpn_clone_q;
wire [0:2] snoop_ack_d;
wire [0:2] snoop_ack_q;
wire [0:4] snoop_coming_d;
wire [0:4] snoop_coming_d /*verilator split_var*/;
wire [0:4] snoop_coming_q;
wire [0:8] an_ac_back_inv_d;
wire [0:8] an_ac_back_inv_q;

12
dev/verilog/work/mmq_tlb_cmp.v
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@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

//********************************************************************
//* TITLE: Memory Management Unit TLB Compare Logic
@ -649,7 +649,7 @@ module mmq_tlb_cmp(
wire [0:`ERAT_REL_DATA_WIDTH-1] tlb_erat_rel_q;
wire [0:`ERAT_REL_DATA_WIDTH-1] tlb_erat_rel_clone_d;
wire [0:`ERAT_REL_DATA_WIDTH-1] tlb_erat_rel_clone_q;
wire [0:2*`THDID_WIDTH+13] tlb_erat_dup_d;
wire [0:2*`THDID_WIDTH+13] tlb_erat_dup_d /*verilator split_var*/;
wire [0:2*`THDID_WIDTH+13] tlb_erat_dup_q;

(* NO_MODIFICATION="TRUE" *)
@ -661,7 +661,7 @@ module mmq_tlb_cmp(
(* NO_MODIFICATION="TRUE" *)
wire [0:`TLB_ADDR_WIDTH-1] lru_wr_addr_q;
(* NO_MODIFICATION="TRUE" *)
wire [0:`LRU_WIDTH-1] lru_datain_d;
wire [0:`LRU_WIDTH-1] lru_datain_d /*verilator split_var*/;
(* NO_MODIFICATION="TRUE" *)
wire [0:`LRU_WIDTH-1] lru_datain_q;

@ -990,7 +990,7 @@ module mmq_tlb_cmp(

// possible eco signals
(* NO_MODIFICATION="TRUE" *)
wire [4:9] lru_datain_alt_d;
wire [4:9] lru_datain_alt_d /*verilator split_var*/;
(* NO_MODIFICATION="TRUE" *)
wire [0:2] lru_update_data_alt;
(* NO_MODIFICATION="TRUE" *)

4
dev/verilog/work/pcq_regs.v
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@ -335,8 +335,8 @@ module pcq_regs(
wire [0:BCFG_RIGHT] bcfg_sov;
wire [0:DCFG_RIGHT] dcfg_siv;
wire [0:DCFG_RIGHT] dcfg_sov;
wire [0:FUNC_RIGHT] func_siv;
wire [0:FUNC_RIGHT] func_sov;
wire [0:FUNC_RIGHT] func_siv /*verilator split_var*/;
wire [0:FUNC_RIGHT] func_sov /*verilator split_var*/;
wire lcb_func_slp_sl_thold_0_b;
wire lcb_cfg_slp_sl_thold_0_b;
wire force_cfgslp;

8
dev/verilog/work/rv_station.v
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@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

@ -658,7 +658,7 @@ module rv_station(

parameter scan_right = dbg_bus_offset + 32;

wire [0:scan_right-1] siv;
wire [0:scan_right-1] siv /*verilator split_var*/;
wire [0:scan_right-1] sov;

genvar n;

10
dev/verilog/work/xu_rf.v
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@ -301,11 +301,11 @@ end
generate
if (BYPASS == 1)
begin : read_bypass
wire [0:10] r0_byp_sel;
wire [0:10] r1_byp_sel;
wire [0:10] r2_byp_sel;
wire [0:10] r3_byp_sel;
wire [0:10] r4_byp_sel;
wire [0:10] r0_byp_sel /*verilator split_var*/;
wire [0:10] r1_byp_sel /*verilator split_var*/;
wire [0:10] r2_byp_sel /*verilator split_var*/;
wire [0:10] r3_byp_sel /*verilator split_var*/;
wire [0:10] r4_byp_sel /*verilator split_var*/;
assign r0_byp_sel[0] = w0e_q & (w0a_q == r0a_q);
assign r0_byp_sel[1] = w1e_q & (w1a_q == r0a_q);
assign r0_byp_sel[2] = w2e_q & (w2a_q == r0a_q);

12
dev/verilog/work/xu_spr.v
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@ -443,20 +443,20 @@ module xu_spr
localparam abist_g8t_bw_0_offset_abst = abist_g8t_bw_1_offset_abst + 1;
localparam scan_right_abst = abist_g8t_bw_0_offset_abst + 2;
// Scanchain Repower
wire [0:scan_right_abst-1] siv_abst;
wire [0:scan_right_abst-1] sov_abst;
wire [0:scan_right_abst-1] siv_abst /*verilator split_var*/;
wire [0:scan_right_abst-1] sov_abst /*verilator split_var*/;
wire [0:2] siv_bcfg;
wire [0:2] sov_bcfg;
wire [0:`THREADS+2] siv_ccfg;
wire [0:`THREADS+2] sov_ccfg;
wire [0:`THREADS+2] siv_dcfg;
wire [0:`THREADS+2] sov_dcfg;
wire [0:2] siv_time;
wire [0:2] sov_time;
wire [0:2] siv_time /*verilator split_var*/;
wire [0:2] sov_time /*verilator split_var*/;
wire [0:2] siv_gptr;
wire [0:2] sov_gptr;
wire [0:2] siv_repr;
wire [0:2] sov_repr;
wire [0:2] siv_repr /*verilator split_var*/;
wire [0:2] sov_repr /*verilator split_var*/;
wire [0:`THREADS+1] func_scan_rpwr_in;
wire [0:`THREADS+1] func_scan_rpwr_out;
wire [0:`THREADS+1] func_scan_gate_out;

4
dev/verilog/work/xu_spr_cspr.v
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@ -36,7 +36,7 @@ module xu_spr_cspr
#(
parameter hvmode = 1,
parameter a2mode = 1,
parameter spr_xucr0_init = 1120
parameter spr_xucr0_init = `INIT_XUCR0
)(
input [0:`NCLK_WIDTH-1] nclk,

@ -370,7 +370,7 @@ module xu_spr_cspr
wire [0:0] ex2_msr_gs_q ; // input=>ex1_msr_gs_q , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1
wire ex2_tenc_we_q, ex1_tenc_we ; // input=>ex1_tenc_we , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1
wire ex2_ccr0_we_q, ex1_ccr0_we ; // input=>ex1_ccr0_we , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1
wire [2-`GPR_WIDTH/32:1] ex2_aspr_re_q, ex1_aspr_re ; // input=>ex1_aspr_re , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1
wire [2-`GPR_WIDTH/32:1] ex2_aspr_re_q, ex1_aspr_re /*verilator split_var*/ ; // input=>ex1_aspr_re , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1
wire ex2_dnh_q, ex1_dnh ; // input=>ex1_dnh , act=>exx_act[1]
wire [0:`THREADS-1] ex3_val_q, ex2_val ; // input=>ex2_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1
wire ex3_val_rd_q, ex3_val_rd_d ; // input=>ex3_val_rd_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1

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