
3 changed files with 60 additions and 10 deletions
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@@ -1,13 +1,36 @@
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#read_verilog ../verilog/unisims |
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# blockbox versions |
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read_verilog ../verilog/unisims_synth |
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read_verilog -I../verilog/trilib ../verilog/trilib/* |
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read_verilog -I../verilog/trilib ../verilog/work/* |
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##### arrays |
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# The blackbox attribute on modules is used to mark empty stub modules |
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# that have the same ports as the real thing but do not contain information |
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# on the internal configuration. This modules are only used by the synthesis |
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# passes to identify input and output ports of cells. The Verilog backend also |
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# does not output blackbox modules on default. read_verilog, unless called with |
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# -noblackbox will automatically set the blackbox attribute on any empty module |
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# it reads. |
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# The whitebox attribute on modules triggers the same behavior as blackbox, but |
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# is for whitebox modules, i.e. library modules that contain a behavioral model |
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# of the cell type. |
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#read_verilog ./verilog/unisims_synth # blockbox versions |
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# this ignores module bodies ands adds blackbox automatically |
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read_verilog -lib ./verilog/unisims |
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##### lib and macros |
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read_verilog -I./verilog/trilib ./verilog/trilib/* |
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read_verilog -I./verilog/trilib ./verilog/work/* |
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##### synth |
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#hierarchy -check -top c # fails with blackbox |
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hierarchy -top c |
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proc; opt; memory -nomap; opt -fast |
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#check -assert |
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#synth -top c |
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#check -assert # some driver errors, lots of array errors cuz blackbox? |
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#synth -top c # fails with blackbox |
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##### map |
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##### finish |
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