openpowerwtf 4 months ago
parent
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  1. 31
      dev/pd/readme.md
  2. 37
      dev/pd/synth/synth.yo
  3. 2
      dev/pd/synth/verilog

31
dev/pd/readme.md

@ -9,9 +9,11 @@ @@ -9,9 +9,11 @@

### test OpenROAD tools

1. attempt unit (or sub-unit) synthesis and static timing, using blackbox arrays amd estimated wiring for some pdk (equivalent to a CI timing script to catch functional changes that break timing)
1. try unit/sub-unit synthesis and static timing, using blackbox arrays amd estimated wiring for some pdk (nangate45?)

* what are the OR steps to do this?
* equivalent to a CI timing script to catch functional changes that break timing

* what are the OR steps to do this? can this be done with only yosys script?s

* floorplan - unbounded?
* pins - no placement if no bounds, and relaxed i/o assertions?
@ -24,3 +26,28 @@ @@ -24,3 +26,28 @@

* are results consistent with expected cycle time?

### Yosys

* blackbox arrays

```
cd synth
yosys -s synth.yo
```

### OpenROAD

* https://openroad.readthedocs.io/en/latest/user/BuildWithDocker.html

* yosys, OpenROAD, LSOracle

```
git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
cd OpenROAD-flow-scripts
./build_openroad.sh [--threads n]
```

```
docker run -it -u $(id -u ${USER}):$(id -g ${USER}) -v $(pwd)/flow/platforms:/OpenROAD-flow-scripts/flow/platforms:ro openroad/flow-scripts
```


37
dev/pd/synth/synth.yo

@ -1,13 +1,36 @@ @@ -1,13 +1,36 @@
#read_verilog ../verilog/unisims
# blockbox versions
read_verilog ../verilog/unisims_synth

read_verilog -I../verilog/trilib ../verilog/trilib/*
read_verilog -I../verilog/trilib ../verilog/work/*
##### arrays

# The blackbox attribute on modules is used to mark empty stub modules
# that have the same ports as the real thing but do not contain information
# on the internal configuration. This modules are only used by the synthesis
# passes to identify input and output ports of cells. The Verilog backend also
# does not output blackbox modules on default. read_verilog, unless called with
# -noblackbox will automatically set the blackbox attribute on any empty module
# it reads.
# The whitebox attribute on modules triggers the same behavior as blackbox, but
# is for whitebox modules, i.e. library modules that contain a behavioral model
# of the cell type.
#read_verilog ./verilog/unisims_synth # blockbox versions

# this ignores module bodies ands adds blackbox automatically
read_verilog -lib ./verilog/unisims

##### lib and macros
read_verilog -I./verilog/trilib ./verilog/trilib/*
read_verilog -I./verilog/trilib ./verilog/work/*

##### synth

#hierarchy -check -top c # fails with blackbox
hierarchy -top c

proc; opt; memory -nomap; opt -fast
#check -assert

#synth -top c
#check -assert # some driver errors, lots of array errors cuz blackbox?
#synth -top c # fails with blackbox

##### map

##### finish


2
dev/pd/synth/verilog

@ -1 +1 @@ @@ -1 +1 @@
../verilog
../../verilog
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