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k410

master
openpowerwtf 4 months ago
parent
commit
e16e2f6c35
  1. 7
      dev/build/litex/a2o.py
  2. 2
      dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/project.wpc
  3. 9
      dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis.wdf
  4. 3
      dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis_details.wdf
  5. 2
      dev/build/litex/build/cmod7/gateware/cmod7.hw/cmod7.lpr
  6. 16
      dev/build/litex/build/cmod7/gateware/cmod7.tcl
  7. 22
      dev/build/litex/build/cmod7/gateware/cmod7.v
  8. 639
      dev/build/litex/build/cmod7/gateware/cmod7.xpr
  9. 8
      dev/build/litex/build/cmod7/gateware/cmod7_mem.init
  10. 2
      dev/build/litex/build/cmod7/software/include/generated/csr.h
  11. 2
      dev/build/litex/build/cmod7/software/include/generated/git.h
  12. 2
      dev/build/litex/build/cmod7/software/include/generated/mem.h
  13. 6
      dev/build/litex/build/cmod7/software/include/generated/soc.h
  14. 4
      dev/build/litex/csr.csv

7
dev/build/litex/a2o.py

@ -1,7 +1,7 @@ @@ -1,7 +1,7 @@
#!/usr/bin/python3

# A2O Test - build with core.py
# a2o.py --csr-csv csr.csv --no-compile-software --build --sys-clk-freq 10e6
# a2o.py --csr-csv csr.csv --no-compile-software --build [--sys-clk-freq 50e6]
#

import os
@ -80,8 +80,9 @@ class BaseSoC(SoCCore): @@ -80,8 +80,9 @@ class BaseSoC(SoCCore):

# try build using different fpga's
#platform = cmod7.Platform()
platform = cmod7.Platform(fpga='xc7a200t-SBG484-1') # arty-200
#platform = cmod7.Platform(fpga='xc7k325t-FFG676-1') #xc7k325t-ffv676-1 ?? need to try it on machine with license
#platform = cmod7.Platform(fpga='xc7a200t-SBG484-1') # arty-200
#platform = cmod7.Platform(fpga='xc7k325t-ffv676-1 ) #
platform = cmod7.Platform(fpga='xc7k410t-ffv676-1') #

SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32,
with_uart=coreUART, integrated_sram_size=0, integrated_rom_size=0,

2
dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/project.wpc vendored

@ -1,3 +1,3 @@ @@ -1,3 +1,3 @@
version:1
6d6f64655f636f756e7465727c54434c4d6f6465:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:

9
dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis.wdf vendored

@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666763637362d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030747362673438342d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:636d6f6437:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@ -11,9 +11,11 @@ version:1 @@ -11,9 +11,11 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
@ -34,7 +36,4 @@ version:1 @@ -34,7 +36,4 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a32333a323773:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:353932312e3035314d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:333733382e3335324d42:00:00
eof:4098139366
eof:2151794815

3
dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis_details.wdf vendored

@ -1,3 +0,0 @@ @@ -1,3 +0,0 @@
version:1
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
eof:2511430288

2
dev/build/litex/build/cmod7/gateware/cmod7.hw/cmod7.lpr

@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.1 (64-bit) -->
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->


16
dev/build/litex/build/cmod7/gateware/cmod7.tcl

@ -1,16 +1,16 @@ @@ -1,16 +1,16 @@

# Create Project

create_project -force -name cmod7 -part xc7a200t-SBG484-1
create_project -force -name cmod7 -part xc7k410t-ffv676-1
set_msg_config -id {Common 17-55} -new_severity {Warning}

# Add Sources

add_files {../../../a2o/verilog/a2o_litex}
add_files {../../../a2o/verilog/trilib}
add_files {../../../a2o/verilog/trilib_clk1x}
add_files {../../../a2o/verilog/work}
read_verilog {../../../build/cmod7/gateware/cmod7.v}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/a2o_litex}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/trilib}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/trilib_clk1x}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/work}
read_verilog {/data/projects/a2o/dev/build/litex/build/cmod7/gateware/cmod7.v}

# Add EDIFs

@ -28,7 +28,7 @@ set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc] @@ -28,7 +28,7 @@ set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc]

# Synthesis

synth_design -directive default -top cmod7 -part xc7k325t-ffv676-1 ;* xc7a200t-SBG484-1
synth_design -directive default -top cmod7 -part xc7k410t-ffv676-1

# Synthesis report

@ -78,4 +78,4 @@ write_bitstream -force cmod7.bit @@ -78,4 +78,4 @@ write_bitstream -force cmod7.bit

# End

quit
quit

22
dev/build/litex/build/cmod7/gateware/cmod7.v

@ -7,9 +7,9 @@ @@ -7,9 +7,9 @@
// https://github.com/enjoy-digital/litex
//
// Filename : cmod7.v
// Device : xc7a200t-SBG484-1
// Device : xc7k410t-ffv676-1
// LiteX sha1 : 6932fc51
// Date : 2022-08-03 07:06:41
// Date : 2022-08-04 07:49:47
//------------------------------------------------------------------------------


@ -290,7 +290,7 @@ reg [1:0] leds_chaser = 2'd0; @@ -290,7 +290,7 @@ reg [1:0] leds_chaser = 2'd0;
reg leds_mode = 1'd0;
wire leds_wait;
wire leds_done;
reg [23:0] leds_count = 24'd12500000;
reg [24:0] leds_count = 25'd25000000;
reg [1:0] leds_leds = 2'd0;
wire [1:0] buttons_status;
wire buttons_we;
@ -1223,9 +1223,9 @@ always @(posedge sys_clk) begin @@ -1223,9 +1223,9 @@ always @(posedge sys_clk) begin
bus_errors <= (bus_errors + 1'd1);
end
end
{tx_tick, tx_phase} <= 24'd9895604;
{tx_tick, tx_phase} <= 23'd4947802;
if (tx_enable) begin
{tx_tick, tx_phase} <= (tx_phase + 24'd9895604);
{tx_tick, tx_phase} <= (tx_phase + 23'd4947802);
end
basesoc_rs232phytx_state <= basesoc_rs232phytx_next_state;
if (tx_count_rs232phytx_next_value_ce0) begin
@ -1240,7 +1240,7 @@ always @(posedge sys_clk) begin @@ -1240,7 +1240,7 @@ always @(posedge sys_clk) begin
rx_rx_d <= rx_rx;
{rx_tick, rx_phase} <= 32'd2147483648;
if (rx_enable) begin
{rx_tick, rx_phase} <= (rx_phase + 24'd9895604);
{rx_tick, rx_phase} <= (rx_phase + 23'd4947802);
end
basesoc_rs232phyrx_state <= basesoc_rs232phyrx_next_state;
if (rx_count_rs232phyrx_next_value_ce0) begin
@ -1345,7 +1345,7 @@ always @(posedge sys_clk) begin @@ -1345,7 +1345,7 @@ always @(posedge sys_clk) begin
leds_count <= (leds_count - 1'd1);
end
end else begin
leds_count <= 24'd12500000;
leds_count <= 25'd25000000;
end
interface1_ram_bus_ack <= 1'd0;
if (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & ((~interface1_ram_bus_ack) | sram1_adr_burst))) begin
@ -1558,7 +1558,7 @@ always @(posedge sys_clk) begin @@ -1558,7 +1558,7 @@ always @(posedge sys_clk) begin
leds_re <= 1'd0;
leds_chaser <= 2'd0;
leds_mode <= 1'd0;
leds_count <= 24'd12500000;
leds_count <= 25'd25000000;
buttons_re <= 1'd0;
interface1_ram_bus_ack <= 1'd0;
slave_sel_r <= 4'd0;
@ -1804,9 +1804,9 @@ MMCME2_ADV #( @@ -1804,9 +1804,9 @@ MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(6'd50),
.CLKIN1_PERIOD(83.33333333333333),
.CLKOUT0_DIVIDE_F(4'd12),
.CLKOUT0_DIVIDE_F(3'd6),
.CLKOUT0_PHASE(1'd0),
.CLKOUT1_DIVIDE(3'd6),
.CLKOUT1_DIVIDE(2'd3),
.CLKOUT1_PHASE(1'd0),
.CLKOUT2_DIVIDE(2'd3),
.CLKOUT2_PHASE(1'd0),
@ -1887,5 +1887,5 @@ MMCME2_ADV #( @@ -1887,5 +1887,5 @@ MMCME2_ADV #(
endmodule

// -----------------------------------------------------------------------------
// Auto-Generated by LiteX on 2022-08-03 07:06:41.
// Auto-Generated by LiteX on 2022-08-04 07:49:47.
//------------------------------------------------------------------------------

639
dev/build/litex/build/cmod7/gateware/cmod7.xpr

File diff suppressed because it is too large Load Diff

8
dev/build/litex/build/cmod7/gateware/cmod7_mem.init

@ -16,14 +16,14 @@ @@ -16,14 +16,14 @@
38
2d
30
33
34
20
30
37
3a
30
36
34
39
3a
34
30
37
00

2
dev/build/litex/build/cmod7/software/include/generated/csr.h

@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41
// Auto-generated by LiteX (6932fc51) on 2022-08-04 07:49:47
//--------------------------------------------------------------------------------
#include <generated/soc.h>
#ifndef __GENERATED_CSR_H

2
dev/build/litex/build/cmod7/software/include/generated/git.h

@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41
// Auto-generated by LiteX (6932fc51) on 2022-08-04 07:49:47
//--------------------------------------------------------------------------------
#ifndef __GENERATED_GIT_H
#define __GENERATED_GIT_H

2
dev/build/litex/build/cmod7/software/include/generated/mem.h

@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41
// Auto-generated by LiteX (6932fc51) on 2022-08-04 07:49:47
//--------------------------------------------------------------------------------
#ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H

6
dev/build/litex/build/cmod7/software/include/generated/soc.h

@ -1,9 +1,9 @@ @@ -1,9 +1,9 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41
// Auto-generated by LiteX (6932fc51) on 2022-08-04 07:49:47
//--------------------------------------------------------------------------------
#ifndef __GENERATED_SOC_H
#define __GENERATED_SOC_H
#define CONFIG_CLOCK_FREQUENCY 50000000
#define CONFIG_CLOCK_FREQUENCY 100000000
#define CONFIG_CPU_HAS_INTERRUPT
#define CONFIG_CPU_RESET_ADDR 0
#define CONFIG_CPU_TYPE_A2O
@ -22,7 +22,7 @@ @@ -22,7 +22,7 @@

#ifndef __ASSEMBLER__
static inline int config_clock_frequency_read(void) {
return 50000000;
return 100000000;
}
static inline int config_cpu_reset_addr_read(void) {
return 0;

4
dev/build/litex/csr.csv

@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
#--------------------------------------------------------------------------------
# Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41
# Auto-generated by LiteX (6932fc51) on 2022-08-04 07:49:47
#--------------------------------------------------------------------------------
csr_base,leds,0xfff01800,,
csr_base,buttons,0xfff02000,,
@ -28,7 +28,7 @@ csr_register,uart_ev_pending,0xfff04010,1,rw @@ -28,7 +28,7 @@ csr_register,uart_ev_pending,0xfff04010,1,rw
csr_register,uart_ev_enable,0xfff04014,1,rw
csr_register,uart_txempty,0xfff04018,1,ro
csr_register,uart_rxfull,0xfff0401c,1,ro
constant,config_clock_frequency,50000000,,
constant,config_clock_frequency,100000000,,
constant,config_cpu_has_interrupt,None,,
constant,config_cpu_reset_addr,0,,
constant,config_cpu_type_a2o,None,,

1 #--------------------------------------------------------------------------------
2 # Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41 # Auto-generated by LiteX (6932fc51) on 2022-08-04 07:49:47
3 #--------------------------------------------------------------------------------
4 csr_base,leds,0xfff01800,,
5 csr_base,buttons,0xfff02000,,
28 csr_register,uart_ev_enable,0xfff04014,1,rw
29 csr_register,uart_txempty,0xfff04018,1,ro
30 csr_register,uart_rxfull,0xfff0401c,1,ro
31 constant,config_clock_frequency,50000000,, constant,config_clock_frequency,100000000,,
32 constant,config_cpu_has_interrupt,None,,
33 constant,config_cpu_reset_addr,0,,
34 constant,config_cpu_type_a2o,None,,
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