Browse Source

kintex experiments

master
William Flynn 4 months ago
parent
commit
8330126c3c
  1. 2
      dev/build/litex/a2o/verilog
  2. 2
      dev/build/litex/build/cmod7/gateware/.Xil/cmod7_propImpl.xdc
  3. 2
      dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/project.wpc
  4. 12
      dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis.wdf
  5. 2
      dev/build/litex/build/cmod7/gateware/cmod7.hw/cmod7.lpr
  6. 14
      dev/build/litex/build/cmod7/gateware/cmod7.tcl
  7. 639
      dev/build/litex/build/cmod7/gateware/cmod7.xpr
  8. 617
      dev/build/litex/build/cmod7/gateware/cmod7_timing_synth.rpt
  9. 18742
      dev/build/litex/build/cmod7/gateware/cmod7_utilization_hierarchical_synth.rpt
  10. 98
      dev/build/litex/build/cmod7/gateware/cmod7_utilization_synth.rpt
  11. 82
      dev/build/litex/build/cmod7/gateware/cmod7_xc7k325t.tcl
  12. 82
      dev/build/litex/build/cmod7/gateware/cmod7_xc7k410t.tcl

2
dev/build/litex/a2o/verilog

@ -1 +1 @@ @@ -1 +1 @@
../../verilog
../../../verilog

2
dev/build/litex/build/cmod7/gateware/.Xil/cmod7_propImpl.xdc

@ -1,4 +1,4 @@ @@ -1,4 +1,4 @@
set_property SRC_FILE_INFO {cfile:/data/projects/a2o/dev/build/litex/build/cmod7/gateware/cmod7.xdc rfile:../cmod7.xdc id:1 order:EARLY} [current_design]
set_property SRC_FILE_INFO {cfile:/afs/apd.pok.ibm.com/projects/eb2020/github-opf/a2o/dev/build/litex/build/cmod7/gateware/cmod7.xdc rfile:../cmod7.xdc id:1 order:EARLY} [current_design]
set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC J18 [get_ports {serial_tx}]
set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design]

2
dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/project.wpc vendored

@ -1,3 +1,3 @@ @@ -1,3 +1,3 @@
version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
6d6f64655f636f756e7465727c54434c4d6f6465:1
eof:

12
dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis.wdf vendored

@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030747362673438342d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666763637362d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:636d6f6437:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@ -11,11 +11,9 @@ version:1 @@ -11,11 +11,9 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
@ -36,7 +34,7 @@ version:1 @@ -36,7 +34,7 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a32393a353873:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:353635382e3230374d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:333337362e3935334d42:00:00
eof:4023463222
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a32333a323773:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:353932312e3035314d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:333733382e3335324d42:00:00
eof:4098139366

2
dev/build/litex/build/cmod7/gateware/cmod7.hw/cmod7.lpr

@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- Product Version: Vivado v2020.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->


14
dev/build/litex/build/cmod7/gateware/cmod7.tcl

@ -6,11 +6,11 @@ set_msg_config -id {Common 17-55} -new_severity {Warning} @@ -6,11 +6,11 @@ set_msg_config -id {Common 17-55} -new_severity {Warning}

# Add Sources

add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/a2o_litex}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/trilib}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/trilib_clk1x}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/work}
read_verilog {/data/projects/a2o/dev/build/litex/build/cmod7/gateware/cmod7.v}
add_files {../../../a2o/verilog/a2o_litex}
add_files {../../../a2o/verilog/trilib}
add_files {../../../a2o/verilog/trilib_clk1x}
add_files {../../../a2o/verilog/work}
read_verilog {../../../build/cmod7/gateware/cmod7.v}

# Add EDIFs

@ -28,7 +28,7 @@ set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc] @@ -28,7 +28,7 @@ set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc]

# Synthesis

synth_design -directive default -top cmod7 -part xc7a200t-SBG484-1
synth_design -directive default -top cmod7 -part xc7k325t-ffv676-1 ;* xc7a200t-SBG484-1

# Synthesis report

@ -78,4 +78,4 @@ write_bitstream -force cmod7.bit @@ -78,4 +78,4 @@ write_bitstream -force cmod7.bit

# End

quit
quit

639
dev/build/litex/build/cmod7/gateware/cmod7.xpr

File diff suppressed because it is too large Load Diff

617
dev/build/litex/build/cmod7/gateware/cmod7_timing_synth.rpt

@ -1,13 +1,13 @@ @@ -1,13 +1,13 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date : Wed Aug 3 07:40:26 2022
| Host : GatorCountry running 64-bit Ubuntu 20.04.4 LTS
--------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
| Date : Wed Aug 3 19:38:35 2022
| Host : gridl294.pok.ibm.com running 64-bit Red Hat Enterprise Linux Workstation release 7.9 (Maipo)
| Command : report_timing_summary -file cmod7_timing_synth.rpt
| Design : cmod7
| Device : 7a200t-sbg484
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------
| Device : 7k410t-ffv676
| Speed File : -1 PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------------------------------

Timing Summary Report

@ -42,7 +42,7 @@ Table of Contents @@ -42,7 +42,7 @@ Table of Contents
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (828)
4. checking unconstrained_internal_endpoints (1624)
5. checking no_input_delay (3)
6. checking no_output_delay (3)
7. checking multiple_clock (0)
@ -67,11 +67,11 @@ Table of Contents @@ -67,11 +67,11 @@ Table of Contents
There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (828)
--------------------------------------------------
4. checking unconstrained_internal_endpoints (1624)
---------------------------------------------------
There are 0 pins that are not constrained for maximum delay.

There are 828 pins that are not constrained for maximum delay due to constant clock. (MEDIUM)
There are 1624 pins that are not constrained for maximum delay due to constant clock. (MEDIUM)


5. checking no_input_delay (3)
@ -128,10 +128,10 @@ Table of Contents @@ -128,10 +128,10 @@ Table of Contents

WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.831 0.000 0 130983 0.011 0.000 0 130983 0.264 0.000 0 90094
1.099 0.000 0 139626 -0.053 -70.544 1378 139626 0.264 0.000 0 97489


All user specified timing constraints are met.
Timing constraints are not met.


------------------------------------------------------------------------------------------------
@ -155,11 +155,11 @@ clk12 {0.000 41.666} 83.333 12.000 @@ -155,11 +155,11 @@ clk12 {0.000 41.666} 83.333 12.000

Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk12 82.121 0.000 0 7 0.150 0.000 0 7 16.667 0.000 0 10
clk12 82.503 0.000 0 7 0.070 0.000 0 7 16.667 0.000 0 10
basesoc_mmcm_fb 16.667 0.000 0 2
crg_clkout0 0.831 0.000 0 130696 0.011 0.000 0 130696 8.750 0.000 0 89885
crg_clkout1 4.643 0.000 0 266 0.201 0.000 0 266 4.500 0.000 0 187
crg_clkout2 0.885 0.000 0 14 0.011 0.000 0 14 0.264 0.000 0 10
crg_clkout0 1.099 0.000 0 139302 -0.053 -70.544 1378 139302 9.090 0.000 0 97260
crg_clkout1 5.647 0.000 0 303 0.102 0.000 0 303 4.650 0.000 0 207
crg_clkout2 1.153 0.000 0 14 0.001 0.000 0 14 0.264 0.000 0 10


------------------------------------------------------------------------------------------------
@ -190,15 +190,15 @@ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing @@ -190,15 +190,15 @@ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing
From Clock: clk12
To Clock: clk12

Setup : 0 Failing Endpoints, Worst Slack 82.121ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.150ns, Total Violation 0.000ns
Setup : 0 Failing Endpoints, Worst Slack 82.503ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 16.667ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 82.121ns (required time - arrival time)
Slack (MET) : 82.503ns (required time - arrival time)
Source: FDCE/C
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Destination: FDCE_1/D
@ -206,12 +206,12 @@ Slack (MET) : 82.121ns (required time - arrival time) @@ -206,12 +206,12 @@ Slack (MET) : 82.121ns (required time - arrival time)
Path Group: clk12
Path Type: Setup (Max at Slow Process Corner)
Requirement: 83.333ns (clk12 rise@83.333ns - clk12 rise@0.000ns)
Data Path Delay: 0.830ns (logic 0.496ns (59.759%) route 0.334ns (40.241%))
Data Path Delay: 0.550ns (logic 0.308ns (56.000%) route 0.242ns (44.000%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.194ns = ( 86.527 - 83.333 )
Source Clock Delay (SCD): 3.623ns
Clock Pessimism Removal (CPR): 0.284ns
Destination Clock Delay (DCD): 3.126ns = ( 86.459 - 83.333 )
Source Clock Delay (SCD): 3.605ns
Clock Pessimism Removal (CPR): 0.334ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
@ -221,39 +221,39 @@ Slack (MET) : 82.121ns (required time - arrival time) @@ -221,39 +221,39 @@ Slack (MET) : 82.121ns (required time - arrival time)
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk12 rise edge) 0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.623 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 1.680 1.680 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.584 2.264 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.120 2.384 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.968 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.053 3.021 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.605 crg_clkin
FDCE r FDCE/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.496 4.119 r FDCE/Q
net (fo=1, unplaced) 0.334 4.453 basesoc_reset0
FDCE (Prop_fdce_C_Q) 0.308 3.913 r FDCE/Q
net (fo=1, unplaced) 0.242 4.155 basesoc_reset0
FDCE r FDCE_1/D
------------------------------------------------------------------- -------------------

(clock clk12 rise edge) 83.333 83.333 r
0.000 83.333 r clk12 (IN)
L17 0.000 83.333 r clk12 (IN)
net (fo=0) 0.000 83.333 clk12
IBUF (Prop_ibuf_I_O) 1.365 84.698 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.760 85.458 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.091 85.549 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 85.988 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.100 86.088 r clk12_inst/O
net (fo=9, unplaced) 0.439 86.527 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 1.539 84.872 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.554 85.426 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.113 85.539 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 85.978 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.042 86.020 r clk12_inst/O
net (fo=9, unplaced) 0.439 86.459 crg_clkin
FDCE r FDCE_1/C
clock pessimism 0.284 86.811
clock uncertainty -0.035 86.776
FDCE (Setup_fdce_C_D) -0.202 86.574 FDCE_1
clock pessimism 0.334 86.793
clock uncertainty -0.035 86.758
FDCE (Setup_fdce_C_D) -0.100 86.658 FDCE_1
-------------------------------------------------------------------
required time 86.574
arrival time -4.453
required time 86.658
arrival time -4.155
-------------------------------------------------------------------
slack 82.121
slack 82.503



@ -261,7 +261,7 @@ Slack (MET) : 82.121ns (required time - arrival time) @@ -261,7 +261,7 @@ Slack (MET) : 82.121ns (required time - arrival time)

Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.150ns (arrival time - required time)
Slack (MET) : 0.070ns (arrival time - required time)
Source: FDCE/C
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Destination: FDCE_1/D
@ -269,48 +269,48 @@ Slack (MET) : 0.150ns (arrival time - required time) @@ -269,48 +269,48 @@ Slack (MET) : 0.150ns (arrival time - required time)
Path Group: clk12
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk12 rise@0.000ns - clk12 rise@0.000ns)
Data Path Delay: 0.299ns (logic 0.158ns (52.880%) route 0.141ns (47.120%))
Data Path Delay: 0.220ns (logic 0.118ns (53.634%) route 0.102ns (46.366%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.349ns
Source Clock Delay (SCD): 0.840ns
Clock Pessimism Removal (CPR): 0.364ns
Destination Clock Delay (DCD): 1.449ns
Source Clock Delay (SCD): 0.940ns
Clock Pessimism Removal (CPR): 0.365ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk12 rise edge) 0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.840 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 0.412 0.412 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.246 0.658 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.684 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.798 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.028 0.826 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.940 crg_clkin
FDCE r FDCE/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.158 0.998 r FDCE/Q
net (fo=1, unplaced) 0.141 1.139 basesoc_reset0
FDCE (Prop_fdce_C_Q) 0.118 1.058 r FDCE/Q
net (fo=1, unplaced) 0.102 1.160 basesoc_reset0
FDCE r FDCE_1/D
------------------------------------------------------------------- -------------------

(clock clk12 rise edge) 0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.349 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 0.607 0.607 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.259 0.866 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.030 0.896 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.155 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.035 1.190 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.449 crg_clkin
FDCE r FDCE_1/C
clock pessimism -0.364 0.985
FDCE (Hold_fdce_C_D) 0.004 0.989 FDCE_1
clock pessimism -0.365 1.085
FDCE (Hold_fdce_C_D) 0.005 1.090 FDCE_1
-------------------------------------------------------------------
required time -0.989
arrival time 1.139
required time -1.090
arrival time 1.160
-------------------------------------------------------------------
slack 0.150
slack 0.070



@ -324,9 +324,9 @@ Period(ns): 83.333 @@ -324,9 +324,9 @@ Period(ns): 83.333
Sources: { clk12 }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 83.333 81.178 clk12_IBUF_BUFG_inst/I
Min Period n/a BUFG/I n/a 1.600 83.333 81.733 clk12_IBUF_BUFG_inst/I
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 83.333 16.667 MMCME2_ADV/CLKIN1
Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 10.000 41.666 31.666 MMCME2_ADV/CLKIN1
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 10.000 41.667 31.667 MMCME2_ADV/CLKIN1
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 10.000 41.666 31.666 MMCME2_ADV/CLKIN1


@ -358,15 +358,15 @@ Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 83.333 @@ -358,15 +358,15 @@ Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 83.333
From Clock: crg_clkout0
To Clock: crg_clkout0

Setup : 0 Failing Endpoints, Worst Slack 0.831ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns
Setup : 0 Failing Endpoints, Worst Slack 1.099ns, Total Violation 0.000ns
Hold : 1378 Failing Endpoints, Worst Slack -0.053ns, Total Violation -70.544ns
PW : 0 Failing Endpoints, Worst Slack 9.090ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.831ns (required time - arrival time)
Slack (MET) : 1.099ns (required time - arrival time)
Source: FDPE/C
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: FDPE_1/D
@ -374,12 +374,12 @@ Slack (MET) : 0.831ns (required time - arrival time) @@ -374,12 +374,12 @@ Slack (MET) : 0.831ns (required time - arrival time)
Path Group: crg_clkout0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.000ns (MaxDelay Path 2.000ns)
Data Path Delay: 0.657ns (logic 0.456ns (69.406%) route 0.201ns (30.594%))
Data Path Delay: 0.425ns (logic 0.281ns (66.118%) route 0.144ns (33.882%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.567ns
Source Clock Delay (SCD): 5.191ns
Clock Pessimism Removal (CPR): 0.479ns
Destination Clock Delay (DCD): 4.315ns
Source Clock Delay (SCD): 4.981ns
Clock Pessimism Removal (CPR): 0.520ns
Clock Uncertainty: 0.300ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.597ns
@ -390,49 +390,49 @@ Slack (MET) : 0.831ns (required time - arrival time) @@ -390,49 +390,49 @@ Slack (MET) : 0.831ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock crg_clkout0 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.623 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 1.680 1.680 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.584 2.264 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.120 2.384 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.968 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.053 3.021 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.605 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.088 3.711 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.800 4.511 crg_clkout0
BUFG (Prop_bufg_I_O) 0.096 4.607 r BUFG/O
net (fo=89883, unplaced) 0.584 5.191 sys_clk
0.088 3.693 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.584 4.277 crg_clkout0
BUFG (Prop_bufg_I_O) 0.120 4.397 r BUFG/O
net (fo=97258, unplaced) 0.584 4.981 sys_clk
FDPE r FDPE/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.456 5.647 r FDPE/Q
net (fo=1, unplaced) 0.201 5.848 xilinxasyncresetsynchronizerimpl0_rst_meta
FDPE (Prop_fdpe_C_Q) 0.281 5.262 r FDPE/Q
net (fo=1, unplaced) 0.144 5.406 xilinxasyncresetsynchronizerimpl0_rst_meta
FDPE r FDPE_1/D
------------------------------------------------------------------- -------------------

max delay 2.000 2.000
0.000 2.000 r clk12 (IN)
L17 0.000 2.000 r clk12 (IN)
net (fo=0) 0.000 2.000 clk12
IBUF (Prop_ibuf_I_O) 1.365 3.365 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.760 4.125 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.091 4.216 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 4.655 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.100 4.755 r clk12_inst/O
net (fo=9, unplaced) 0.439 5.194 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 1.539 3.539 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.554 4.093 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.113 4.206 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 4.645 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.042 4.687 r clk12_inst/O
net (fo=9, unplaced) 0.439 5.126 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 5.277 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.760 6.037 crg_clkout0
BUFG (Prop_bufg_I_O) 0.091 6.128 r BUFG/O
net (fo=89883, unplaced) 0.439 6.567 sys_clk
0.083 5.209 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.554 5.763 crg_clkout0
BUFG (Prop_bufg_I_O) 0.113 5.876 r BUFG/O
net (fo=97258, unplaced) 0.439 6.315 sys_clk
FDPE r FDPE_1/C
clock pessimism 0.479 7.046
clock uncertainty -0.300 6.745
FDPE (Setup_fdpe_C_D) -0.067 6.678 FDPE_1
clock pessimism 0.520 6.836
clock uncertainty -0.300 6.535
FDPE (Setup_fdpe_C_D) -0.031 6.504 FDPE_1
-------------------------------------------------------------------
required time 6.678
arrival time -5.848
required time 6.504
arrival time -5.406
-------------------------------------------------------------------
slack 0.831
slack 1.099



@ -440,68 +440,69 @@ Slack (MET) : 0.831ns (required time - arrival time) @@ -440,68 +440,69 @@ Slack (MET) : 0.831ns (required time - arrival time)

Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.011ns (arrival time - required time)
Source: FDPE/C
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: FDPE_1/D
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Slack (VIOLATED) : -0.053ns (arrival time - required time)
Source: a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_miss0/reld_data_latch/int_dout_reg[31]/C
(rising edge-triggered cell FDRE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/genblk1.aw[0].ax[0].arr/DIADI[0]
(rising edge-triggered cell RAMB36E1 clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: crg_clkout0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (crg_clkout0 rise@0.000ns - crg_clkout0 rise@0.000ns)
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.045ns
Source Clock Delay (SCD): 1.367ns
Clock Pessimism Removal (CPR): 0.533ns
Destination Clock Delay (DCD): 2.050ns
Source Clock Delay (SCD): 1.376ns
Clock Pessimism Removal (CPR): 0.530ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout0 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.840 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 0.412 0.412 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.246 0.658 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.684 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.798 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.028 0.826 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.940 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.050 0.890 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.337 1.227 crg_clkout0
BUFG (Prop_bufg_I_O) 0.026 1.253 r BUFG/O
net (fo=89883, unplaced) 0.114 1.367 sys_clk
FDPE r FDPE/C
0.050 0.990 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.246 1.236 crg_clkout0
BUFG (Prop_bufg_I_O) 0.026 1.262 r BUFG/O
net (fo=97258, unplaced) 0.114 1.376 a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_miss0/reld_data_latch/out
FDRE r a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_miss0/reld_data_latch/int_dout_reg[31]/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.141 1.508 r FDPE/Q
net (fo=1, unplaced) 0.085 1.593 xilinxasyncresetsynchronizerimpl0_rst_meta
FDPE r FDPE_1/D
FDRE (Prop_fdre_C_Q) 0.104 1.480 r a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_miss0/reld_data_latch/int_dout_reg[31]/Q
net (fo=13, unplaced) 0.246 1.726 a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/icm_icd_reload_data[31]
RAMB36E1 r a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/genblk1.aw[0].ax[0].arr/DIADI[0]
------------------------------------------------------------------- -------------------

(clock crg_clkout0 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.349 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 0.607 0.607 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.259 0.866 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.030 0.896 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.155 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.035 1.190 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.449 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 1.402 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.355 1.757 crg_clkout0
BUFG (Prop_bufg_I_O) 0.029 1.786 r BUFG/O
net (fo=89883, unplaced) 0.259 2.045 sys_clk
FDPE r FDPE_1/C
clock pessimism -0.533 1.512
FDPE (Hold_fdpe_C_D) 0.070 1.582 FDPE_1
0.053 1.502 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.259 1.761 crg_clkout0
BUFG (Prop_bufg_I_O) 0.030 1.791 r BUFG/O
net (fo=97258, unplaced) 0.259 2.050 a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/out
RAMB36E1 r a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/genblk1.aw[0].ax[0].arr/CLKARDCLK
clock pessimism -0.530 1.521
RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[0])
0.258 1.779 a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/genblk1.aw[0].ax[0].arr
-------------------------------------------------------------------
required time -1.582
arrival time 1.593
required time -1.779
arrival time 1.726
-------------------------------------------------------------------
slack 0.011
slack -0.053



@ -515,10 +516,10 @@ Period(ns): 20.000 @@ -515,10 +516,10 @@ Period(ns): 20.000
Sources: { MMCME2_ADV/CLKOUT0 }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 a2owb/c0/lq0/ctl/dc32Kdir64B.arr/arr5_F/CLKARDCLK
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 20.000 17.505 a2owb/c0/lq0/dat/dc32K.tridcarr/Nways[6].Narrs[3].wayArr/CLKARDCLK
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 20.000 193.360 MMCME2_ADV/CLKOUT0
Low Pulse Width Slow RAMD64E/CLK n/a 1.250 10.000 8.750 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK
High Pulse Width Fast RAMD64E/CLK n/a 1.250 10.000 8.750 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK
Low Pulse Width Slow RAMD64E/CLK n/a 0.910 10.000 9.090 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK
High Pulse Width Slow RAMD64E/CLK n/a 0.910 10.000 9.090 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK



@ -526,15 +527,15 @@ High Pulse Width Fast RAMD64E/CLK n/a 1.250 10.00 @@ -526,15 +527,15 @@ High Pulse Width Fast RAMD64E/CLK n/a 1.250 10.00
From Clock: crg_clkout1
To Clock: crg_clkout1

Setup : 0 Failing Endpoints, Worst Slack 4.643ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.201ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
Setup : 0 Failing Endpoints, Worst Slack 5.647ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.102ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.650ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 4.643ns (required time - arrival time)
Slack (MET) : 5.647ns (required time - arrival time)
Source: a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
(rising edge-triggered cell RAMB36E1 clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: a2owb/c0/iuq0/bht2/bht0/bram0a/DIADI[16]
@ -542,12 +543,12 @@ Slack (MET) : 4.643ns (required time - arrival time) @@ -542,12 +543,12 @@ Slack (MET) : 4.643ns (required time - arrival time)
Path Group: crg_clkout1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (crg_clkout1 rise@10.000ns - crg_clkout1 rise@0.000ns)
Data Path Delay: 4.203ns (logic 2.604ns (61.949%) route 1.599ns (38.051%))
Data Path Delay: 3.312ns (logic 2.145ns (64.762%) route 1.167ns (35.238%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.567ns = ( 14.567 - 10.000 )
Source Clock Delay (SCD): 5.191ns
Clock Pessimism Removal (CPR): 0.479ns
Destination Clock Delay (DCD): 4.315ns = ( 14.315 - 10.000 )
Source Clock Delay (SCD): 4.981ns
Clock Pessimism Removal (CPR): 0.520ns
Clock Uncertainty: 0.272ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.539ns
@ -557,54 +558,54 @@ Slack (MET) : 4.643ns (required time - arrival time) @@ -557,54 +558,54 @@ Slack (MET) : 4.643ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock crg_clkout1 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.623 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 1.680 1.680 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.584 2.264 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.120 2.384 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.968 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.053 3.021 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.605 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.088 3.711 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.800 4.511 crg_clkout1
BUFG (Prop_bufg_I_O) 0.096 4.607 r BUFG_1/O
net (fo=185, unplaced) 0.584 5.191 a2owb/c0/iuq0/bht2/bht0/sys2x_clk
0.088 3.693 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.584 4.277 crg_clkout1
BUFG (Prop_bufg_I_O) 0.120 4.397 r BUFG_1/O
net (fo=205, unplaced) 0.584 4.981 a2owb/c0/iuq0/bht2/bht0/CLK
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
------------------------------------------------------------------- -------------------
RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[16])
2.454 7.645 r a2owb/c0/iuq0/bht2/bht0/bram0a/DOADO[16]
net (fo=1, unplaced) 0.800 8.445 a2owb/c0/iuq0/bht2/bht0/r_data_out_0_bram[20]
LUT2 (Prop_lut2_I0_O) 0.150 8.595 r a2owb/c0/iuq0/bht2/bht0/bram0a_i_17__1/O
net (fo=1, unplaced) 0.800 9.394 a2owb/c0/iuq0/bht2/bht0/w_data_in_0[15]
2.080 7.061 r a2owb/c0/iuq0/bht2/bht0/bram0a/DOADO[16]
net (fo=1, unplaced) 0.584 7.644 a2owb/c0/iuq0/bht2/bht0/r_data_out_0_bram[20]
LUT2 (Prop_lut2_I0_O) 0.065 7.709 r a2owb/c0/iuq0/bht2/bht0/bram0a_i_17__1/O
net (fo=1, unplaced) 0.584 8.293 a2owb/c0/iuq0/bht2/bht0/w_data_in_0[15]
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/DIADI[16]
------------------------------------------------------------------- -------------------

(clock crg_clkout1 rise edge)
10.000 10.000 r
0.000 10.000 r clk12 (IN)
L17 0.000 10.000 r clk12 (IN)
net (fo=0) 0.000 10.000 clk12
IBUF (Prop_ibuf_I_O) 1.365 11.365 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.760 12.125 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.091 12.216 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 12.655 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.100 12.755 r clk12_inst/O
net (fo=9, unplaced) 0.439 13.194 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 1.539 11.539 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.554 12.093 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.113 12.206 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 12.645 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.042 12.687 r clk12_inst/O
net (fo=9, unplaced) 0.439 13.126 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.083 13.277 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.760 14.037 crg_clkout1
BUFG (Prop_bufg_I_O) 0.091 14.128 r BUFG_1/O
net (fo=185, unplaced) 0.439 14.567 a2owb/c0/iuq0/bht2/bht0/sys2x_clk
0.083 13.209 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.554 13.763 crg_clkout1
BUFG (Prop_bufg_I_O) 0.113 13.876 r BUFG_1/O
net (fo=205, unplaced) 0.439 14.315 a2owb/c0/iuq0/bht2/bht0/CLK
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
clock pessimism 0.479 15.046
clock uncertainty -0.272 14.774
clock pessimism 0.520 14.836
clock uncertainty -0.272 14.564
RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[16])
-0.737 14.037 a2owb/c0/iuq0/bht2/bht0/bram0a
-0.624 13.940 a2owb/c0/iuq0/bht2/bht0/bram0a
-------------------------------------------------------------------
required time 14.037
arrival time -9.394
required time 13.940
arrival time -8.293
-------------------------------------------------------------------
slack 4.643
slack 5.647



@ -612,7 +613,7 @@ Slack (MET) : 4.643ns (required time - arrival time) @@ -612,7 +613,7 @@ Slack (MET) : 4.643ns (required time - arrival time)

Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.201ns (arrival time - required time)
Slack (MET) : 0.102ns (arrival time - required time)
Source: a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/C
(rising edge-triggered cell FDRE clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/D
@ -620,62 +621,62 @@ Slack (MET) : 0.201ns (arrival time - required time) @@ -620,62 +621,62 @@ Slack (MET) : 0.201ns (arrival time - required time)
Path Group: crg_clkout1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (crg_clkout1 rise@0.000ns - crg_clkout1 rise@0.000ns)
Data Path Delay: 0.437ns (logic 0.239ns (54.677%) route 0.198ns (45.323%))
Data Path Delay: 0.316ns (logic 0.168ns (53.243%) route 0.148ns (46.757%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.045ns
Source Clock Delay (SCD): 1.367ns
Clock Pessimism Removal (CPR): 0.533ns
Destination Clock Delay (DCD): 2.050ns
Source Clock Delay (SCD): 1.376ns
Clock Pessimism Removal (CPR): 0.530ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout1 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.840 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 0.412 0.412 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.246 0.658 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.684 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.798 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.028 0.826 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.940 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.050 0.890 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.337 1.227 crg_clkout1
BUFG (Prop_bufg_I_O) 0.026 1.253 r BUFG_1/O
net (fo=185, unplaced) 0.114 1.367 a2owb/c0/iuq0/bht0/bht0/sys2x_clk
0.050 0.990 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.246 1.236 crg_clkout1
BUFG (Prop_bufg_I_O) 0.026 1.262 r BUFG_1/O
net (fo=205, unplaced) 0.114 1.376 a2owb/c0/iuq0/bht0/bht0/CLK
FDRE r a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.141 1.508 r a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/Q
net (fo=1, unplaced) 0.198 1.706 a2owb/c0/iuq0/bht0/bht0/toggle2x_q
LUT2 (Prop_lut2_I0_O) 0.098 1.804 r a2owb/c0/iuq0/bht0/bht0/gate_fq_i_1__1/O
net (fo=1, unplaced) 0.000 1.804 a2owb/c0/iuq0/bht0/bht0/gate_d
FDRE (Prop_fdre_C_Q) 0.104 1.480 r a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/Q
net (fo=1, unplaced) 0.148 1.627 a2owb/c0/iuq0/bht0/bht0/toggle2x_q
LUT2 (Prop_lut2_I0_O) 0.064 1.691 r a2owb/c0/iuq0/bht0/bht0/gate_fq_i_1__1/O
net (fo=1, unplaced) 0.000 1.691 a2owb/c0/iuq0/bht0/bht0/gate_d
FDRE r a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/D
------------------------------------------------------------------- -------------------

(clock crg_clkout1 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.349 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 0.607 0.607 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.259 0.866 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.030 0.896 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.155 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.035 1.190 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.449 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.053 1.402 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.355 1.757 crg_clkout1
BUFG (Prop_bufg_I_O) 0.029 1.786 r BUFG_1/O
net (fo=185, unplaced) 0.259 2.045 a2owb/c0/iuq0/bht0/bht0/sys2x_clk
0.053 1.502 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.259 1.761 crg_clkout1
BUFG (Prop_bufg_I_O) 0.030 1.791 r BUFG_1/O
net (fo=205, unplaced) 0.259 2.050 a2owb/c0/iuq0/bht0/bht0/CLK
FDRE r a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/C
clock pessimism -0.533 1.512
FDRE (Hold_fdre_C_D) 0.091 1.603 a2owb/c0/iuq0/bht0/bht0/gate_fq_reg
clock pessimism -0.530 1.521
FDRE (Hold_fdre_C_D) 0.069 1.590 a2owb/c0/iuq0/bht0/bht0/gate_fq_reg
-------------------------------------------------------------------
required time -1.603
arrival time 1.804
required time -1.590
arrival time 1.691
-------------------------------------------------------------------
slack 0.201
slack 0.102



@ -689,10 +690,10 @@ Period(ns): 10.000 @@ -689,10 +690,10 @@ Period(ns): 10.000
Sources: { MMCME2_ADV/CLKOUT1 }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 10.000 7.424 a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.183 10.000 7.817 a2owb/c0/lq0/ctl/derat/derat_cam/bram0/CLKARDCLK
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 10.000 203.360 MMCME2_ADV/CLKOUT1
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 a2owb/c0/iuq0/bht1/bht0/gate_fq_reg/C
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 a2owb/c0/iuq0/bht1/bht0/gate_fq_reg/C
Low Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 a2owb/c0/mmu0/tlb_gen_instance.lru_array0/gate_fq_reg/C
High Pulse Width Fast FDRE/C n/a 0.350 5.000 4.650 a2owb/c0/mmu0/tlb_gen_instance.lru_array0/gate_fq_reg/C



@ -700,15 +701,15 @@ High Pulse Width Slow FDRE/C n/a 0.500 5.000 @@ -700,15 +701,15 @@ High Pulse Width Slow FDRE/C n/a 0.500 5.000
From Clock: crg_clkout2
To Clock: crg_clkout2

Setup : 0 Failing Endpoints, Worst Slack 0.885ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
Setup : 0 Failing Endpoints, Worst Slack 1.153ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.001ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.885ns (required time - arrival time)
Slack (MET) : 1.153ns (required time - arrival time)
Source: FDPE_4/C
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: FDPE_5/D
@ -716,12 +717,12 @@ Slack (MET) : 0.885ns (required time - arrival time) @@ -716,12 +717,12 @@ Slack (MET) : 0.885ns (required time - arrival time)
Path Group: crg_clkout2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.000ns (MaxDelay Path 2.000ns)
Data Path Delay: 0.657ns (logic 0.456ns (69.406%) route 0.201ns (30.594%))
Data Path Delay: 0.425ns (logic 0.281ns (66.118%) route 0.144ns (33.882%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.567ns
Source Clock Delay (SCD): 5.191ns
Clock Pessimism Removal (CPR): 0.479ns
Destination Clock Delay (DCD): 4.315ns
Source Clock Delay (SCD): 4.981ns
Clock Pessimism Removal (CPR): 0.520ns
Clock Uncertainty: 0.246ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.487ns
@ -732,49 +733,49 @@ Slack (MET) : 0.885ns (required time - arrival time) @@ -732,49 +733,49 @@ Slack (MET) : 0.885ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock crg_clkout2 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.623 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 1.680 1.680 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.584 2.264 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.120 2.384 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.968 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.053 3.021 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.605 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 3.711 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.800 4.511 crg_clkout2
BUFG (Prop_bufg_I_O) 0.096 4.607 r BUFG_2/O
net (fo=8, unplaced) 0.584 5.191 idelay_clk
0.088 3.693 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.584 4.277 crg_clkout2
BUFG (Prop_bufg_I_O) 0.120 4.397 r BUFG_2/O
net (fo=8, unplaced) 0.584 4.981 idelay_clk
FDPE r FDPE_4/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.456 5.647 r FDPE_4/Q
net (fo=1, unplaced) 0.201 5.848 xilinxasyncresetsynchronizerimpl2_rst_meta
FDPE (Prop_fdpe_C_Q) 0.281 5.262 r FDPE_4/Q
net (fo=1, unplaced) 0.144 5.406 xilinxasyncresetsynchronizerimpl2_rst_meta
FDPE r FDPE_5/D
------------------------------------------------------------------- -------------------

max delay 2.000 2.000
0.000 2.000 r clk12 (IN)
L17 0.000 2.000 r clk12 (IN)
net (fo=0) 0.000 2.000 clk12
IBUF (Prop_ibuf_I_O) 1.365 3.365 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.760 4.125 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.091 4.216 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 4.655 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.100 4.755 r clk12_inst/O
net (fo=9, unplaced) 0.439 5.194 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 1.539 3.539 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.554 4.093 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.113 4.206 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 4.645 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.042 4.687 r clk12_inst/O
net (fo=9, unplaced) 0.439 5.126 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 5.277 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.760 6.037 crg_clkout2
BUFG (Prop_bufg_I_O) 0.091 6.128 r BUFG_2/O
net (fo=8, unplaced) 0.439 6.567 idelay_clk
0.083 5.209 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.554 5.763 crg_clkout2
BUFG (Prop_bufg_I_O) 0.113 5.876 r BUFG_2/O
net (fo=8, unplaced) 0.439 6.315 idelay_clk
FDPE r FDPE_5/C
clock pessimism 0.479 7.046
clock uncertainty -0.246 6.800
FDPE (Setup_fdpe_C_D) -0.067 6.733 FDPE_5
clock pessimism 0.520 6.836
clock uncertainty -0.246 6.589
FDPE (Setup_fdpe_C_D) -0.031 6.558 FDPE_5
-------------------------------------------------------------------
required time 6.733
arrival time -5.848
required time 6.558
arrival time -5.406
-------------------------------------------------------------------
slack 0.885
slack 1.153



@ -782,7 +783,7 @@ Slack (MET) : 0.885ns (required time - arrival time) @@ -782,7 +783,7 @@ Slack (MET) : 0.885ns (required time - arrival time)

Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.011ns (arrival time - required time)
Slack (MET) : 0.001ns (arrival time - required time)
Source: FDPE_4/C
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: FDPE_5/D
@ -790,60 +791,60 @@ Slack (MET) : 0.011ns (arrival time - required time) @@ -790,60 +791,60 @@ Slack (MET) : 0.011ns (arrival time - required time)
Path Group: crg_clkout2
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (crg_clkout2 rise@0.000ns - crg_clkout2 rise@0.000ns)
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
Data Path Delay: 0.165ns (logic 0.104ns (63.146%) route 0.061ns (36.854%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.045ns
Source Clock Delay (SCD): 1.367ns
Clock Pessimism Removal (CPR): 0.533ns
Destination Clock Delay (DCD): 2.050ns
Source Clock Delay (SCD): 1.376ns
Clock Pessimism Removal (CPR): 0.530ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout2 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.840 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 0.412 0.412 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.246 0.658 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.684 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.798 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.028 0.826 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.940 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 0.890 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.337 1.227 crg_clkout2
BUFG (Prop_bufg_I_O) 0.026 1.253 r BUFG_2/O
net (fo=8, unplaced) 0.114 1.367 idelay_clk
0.050 0.990 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.246 1.236 crg_clkout2
BUFG (Prop_bufg_I_O) 0.026 1.262 r BUFG_2/O
net (fo=8, unplaced) 0.114 1.376 idelay_clk
FDPE r FDPE_4/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.141 1.508 r FDPE_4/Q
net (fo=1, unplaced) 0.085 1.593 xilinxasyncresetsynchronizerimpl2_rst_meta
FDPE (Prop_fdpe_C_Q) 0.104 1.480 r FDPE_4/Q
net (fo=1, unplaced) 0.061 1.540 xilinxasyncresetsynchronizerimpl2_rst_meta
FDPE r FDPE_5/D
------------------------------------------------------------------- -------------------

(clock crg_clkout2 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.349 crg_clkin
L17 IBUF (Prop_ibuf_I_O) 0.607 0.607 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.259 0.866 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.030 0.896 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.155 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.035 1.190 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.449 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 1.402 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.355 1.757 crg_clkout2
BUFG (Prop_bufg_I_O) 0.029 1.786 r BUFG_2/O
net (fo=8, unplaced) 0.259 2.045 idelay_clk
0.053 1.502 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.259 1.761 crg_clkout2
BUFG (Prop_bufg_I_O) 0.030 1.791 r BUFG_2/O
net (fo=8, unplaced) 0.259 2.050 idelay_clk
FDPE r FDPE_5/C
clock pessimism -0.533 1.512
FDPE (Hold_fdpe_C_D) 0.070 1.582 FDPE_5
clock pessimism -0.530 1.521
FDPE (Hold_fdpe_C_D) 0.019 1.540 FDPE_5
-------------------------------------------------------------------
required time -1.582
arrival time 1.593
required time -1.540
arrival time 1.540
-------------------------------------------------------------------
slack 0.011
slack 0.001



@ -859,8 +860,8 @@ Sources: { MMCME2_ADV/CLKOUT2 } @@ -859,8 +860,8 @@ Sources: { MMCME2_ADV/CLKOUT2 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a IDELAYCTRL/REFCLK n/a 3.225 5.000 1.775 IDELAYCTRL/REFCLK
Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL/REFCLK
Low Pulse Width Fast FDPE/C n/a 0.500 2.500 2.000 FDPE_4/C
High Pulse Width Slow FDPE/C n/a 0.500 2.500 2.000 FDPE_4/C
Low Pulse Width Fast FDPE/C n/a 0.350 2.500 2.150 FDPE_4/C
High Pulse Width Fast FDPE/C n/a 0.350 2.500 2.150 FDPE_4/C




18742
dev/build/litex/build/cmod7/gateware/cmod7_utilization_hierarchical_synth.rpt

File diff suppressed because it is too large Load Diff

98
dev/build/litex/build/cmod7/gateware/cmod7_utilization_synth.rpt

@ -1,13 +1,13 @@ @@ -1,13 +1,13 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date : Wed Aug 3 07:40:33 2022
| Host : GatorCountry running 64-bit Ubuntu 20.04.4 LTS
--------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
| Date : Wed Aug 3 19:38:43 2022
| Host : gridl294.pok.ibm.com running 64-bit Red Hat Enterprise Linux Workstation release 7.9 (Maipo)
| Command : report_utilization -file cmod7_utilization_synth.rpt
| Design : cmod7
| Device : 7a200tsbg484-1
| Device : 7k410tffv676-1
| Design State : Synthesized
------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------

Utilization Design Information

@ -27,20 +27,20 @@ Table of Contents @@ -27,20 +27,20 @@ Table of Contents
1. Slice Logic
--------------

+----------------------------+--------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+--------+-------+-----------+--------+
| Slice LUTs* | 231525 | 0 | 134600 | 172.01 |
| LUT as Logic | 230967 | 0 | 134600 | 171.60 |
| LUT as Memory | 558 | 0 | 46200 | 1.21 |
| LUT as Distributed RAM | 556 | 0 | | |
| LUT as Shift Register | 2 | 0 | | |
| Slice Registers | 89333 | 0 | 269200 | 33.18 |
| Register as Flip Flop | 89333 | 0 | 269200 | 33.18 |
| Register as Latch | 0 | 0 | 269200 | 0.00 |
| F7 Muxes | 8148 | 0 | 67300 | 12.11 |
| F8 Muxes | 3260 | 0 | 33650 | 9.69 |
+----------------------------+--------+-------+-----------+--------+
+----------------------------+--------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+--------+-------+-----------+-------+
| Slice LUTs* | 242181 | 0 | 254200 | 95.27 |
| LUT as Logic | 241623 | 0 | 254200 | 95.05 |
| LUT as Memory | 558 | 0 | 90600 | 0.62 |
| LUT as Distributed RAM | 556 | 0 | | |
| LUT as Shift Register | 2 | 0 | | |
| Slice Registers | 96706 | 0 | 508400 | 19.02 |
| Register as Flip Flop | 96706 | 0 | 508400 | 19.02 |
| Register as Latch | 0 | 0 | 508400 | 0.00 |
| F7 Muxes | 8152 | 0 | 127100 | 6.41 |
| F8 Muxes | 3260 | 0 | 63550 | 5.13 |
+----------------------------+--------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.


@ -58,8 +58,8 @@ Table of Contents @@ -58,8 +58,8 @@ Table of Contents
| 0 | Yes | - | - |
| 4 | Yes | - | Set |
| 8 | Yes | - | Reset |
| 903 | Yes | Set | - |
| 88418 | Yes | Reset | - |
| 968 | Yes | Set | - |
| 95726 | Yes | Reset | - |
+-------+--------------+-------------+--------------+


@ -69,10 +69,10 @@ Table of Contents @@ -69,10 +69,10 @@ Table of Contents
+-------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+-------+-------+-----------+-------+
| Block RAM Tile | 101.5 | 0 | 365 | 27.81 |
| RAMB36/FIFO* | 95 | 0 | 365 | 26.03 |
| RAMB36E1 only | 95 | | | |
| RAMB18 | 13 | 0 | 730 | 1.78 |
| Block RAM Tile | 122.5 | 0 | 795 | 15.41 |
| RAMB36/FIFO* | 116 | 0 | 795 | 14.59 |
| RAMB36E1 only | 116 | | | |
| RAMB18 | 13 | 0 | 1590 | 0.82 |
| RAMB18E1 only | 13 | | | |
+-------------------+-------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@ -84,7 +84,7 @@ Table of Contents @@ -84,7 +84,7 @@ Table of Contents
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 740 | 0.00 |
| DSPs | 0 | 0 | 1540 | 0.00 |
+-----------+------+-------+-----------+-------+


@ -94,24 +94,26 @@ Table of Contents @@ -94,24 +94,26 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 7 | 3 | 285 | 2.46 |
| IOB Master Pads | 1 | | | |
| IOB Slave Pads | 2 | | | |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| Bonded IOB | 7 | 5 | 400 | 1.75 |
| IOB Master Pads | 4 | | | |
| IOB Slave Pads | 1 | | | |
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
| PHASER_REF | 0 | 0 | 10 | 0.00 |
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
| IN_FIFO | 0 | 0 | 40 | 0.00 |
| IDELAYCTRL | 1 | 0 | 10 | 10.00 |
| IBUFDS | 0 | 0 | 274 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 |
| IBUFDS | 0 | 0 | 384 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 2 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 8 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 285 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
| ILOGIC | 0 | 0 | 400 | 0.00 |
| OLOGIC | 0 | 0 | 400 | 0.00 |
+-----------------------------+------+-------+-----------+-------+


@ -126,7 +128,7 @@ Table of Contents @@ -126,7 +128,7 @@ Table of Contents
| MMCME2_ADV | 1 | 0 | 10 | 10.00 |
| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
| BUFMRCE | 0 | 0 | 20 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFHCE | 0 | 0 | 168 | 0.00 |
| BUFR | 0 | 0 | 40 | 0.00 |
+------------+------+-------+-----------+-------+

@ -155,19 +157,19 @@ Table of Contents @@ -155,19 +157,19 @@ Table of Contents
+------------+--------+---------------------+
| Ref Name | Used | Functional Category |
+------------+--------+---------------------+
| LUT6 | 121905 | LUT |
| FDRE | 88418 | Flop & Latch |
| LUT5 | 62878 | LUT |
| LUT4 | 40414 | LUT |
| LUT3 | 14779 | LUT |
| MUXF7 | 8148 | MuxFx |
| LUT2 | 5981 | LUT |
| LUT6 | 127890 | LUT |
| FDRE | 95726 | Flop & Latch |
| LUT5 | 68665 | LUT |
| LUT4 | 38118 | LUT |
| LUT3 | 15941 | LUT |
| MUXF7 | 8152 | MuxFx |
| LUT2 | 6433 | LUT |
| MUXF8 | 3260 | MuxFx |
| FDSE | 903 | Flop & Latch |
| CARRY4 | 751 | CarryLogic |
| CARRY4 | 1119 | CarryLogic |
| FDSE | 968 | Flop & Latch |
| RAMD64E | 540 | Distributed Memory |
| LUT1 | 473 | LUT |
| RAMB36E1 | 95 | Block Memory |
| RAMB36E1 | 116 | Block Memory |
| RAMD32 | 24 | Distributed Memory |
| RAMB18E1 | 13 | Block Memory |
| RAMS32 | 8 | Distributed Memory |

82
dev/build/litex/build/cmod7/gateware/cmod7_xc7k325t.tcl

@ -0,0 +1,82 @@ @@ -0,0 +1,82 @@
# vivado -mode tcl -source cmod7_xc7k325t.tcl

# Create Project

create_project -force -name cmod7 -part xc7k325t-ffv676-1
set_msg_config -id {Common 17-55} -new_severity {Warning}

# Add Sources

add_files {../../../a2o/verilog/a2o_litex}
add_files {../../../a2o/verilog/trilib}
add_files {../../../a2o/verilog/trilib_clk1x}
add_files {../../../a2o/verilog/work}
read_verilog {../../../build/cmod7/gateware/cmod7.v}

# Add EDIFs


# Add IPs


# Add constraints

read_xdc cmod7.xdc
set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc]

# Add pre-synthesis commands


# Synthesis

synth_design -directive default -top cmod7 -part xc7k325t-ffv676-1

# Synthesis report

report_timing_summary -file cmod7_timing_synth.rpt
report_utilization -hierarchical -file cmod7_utilization_hierarchical_synth.rpt
report_utilization -file cmod7_utilization_synth.rpt

# Optimize design

opt_design -directive default

# Add pre-placement commands


# Placement

place_design -directive default

# Placement report

report_utilization -hierarchical -hierarchical_depth 4 -hierarchical_percentages -file cmod7_utilization_hierarchical_place.rpt
report_utilization -file cmod7_utilization_place.rpt
report_io -file cmod7_io.rpt
report_control_sets -verbose -file cmod7_control_sets.rpt
report_clock_utilization -file cmod7_clock_utilization.rpt

# Add pre-routing commands


# Routing

route_design -directive default
phys_opt_design -directive default
write_checkpoint -force cmod7_route.dcp

# Routing report

report_timing_summary -no_header -no_detailed_paths
report_route_status -file cmod7_route_status.rpt
report_drc -file cmod7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file cmod7_timing.rpt
report_power -file cmod7_power.rpt

# Bitstream generation

write_bitstream -force cmod7.bit

# End

quit

82
dev/build/litex/build/cmod7/gateware/cmod7_xc7k410t.tcl

@ -0,0 +1,82 @@ @@ -0,0 +1,82 @@
# vivado -mode tcl -source cmod7_xc7k410t.tcl

# Create Project

create_project -force -name cmod7 -part xc7k410t-ffv676-1
set_msg_config -id {Common 17-55} -new_severity {Warning}

# Add Sources

add_files {../../../a2o/verilog/a2o_litex}
add_files {../../../a2o/verilog/trilib}
add_files {../../../a2o/verilog/trilib_clk1x}
add_files {../../../a2o/verilog/work}
read_verilog {../../../build/cmod7/gateware/cmod7.v}

# Add EDIFs


# Add IPs


# Add constraints

read_xdc cmod7.xdc
set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc]

# Add pre-synthesis commands


# Synthesis

synth_design -directive default -top cmod7 -part xc7k410t-ffv676-1

# Synthesis report

report_timing_summary -file cmod7_timing_synth.rpt
report_utilization -hierarchical -file cmod7_utilization_hierarchical_synth.rpt
report_utilization -file cmod7_utilization_synth.rpt

# Optimize design

opt_design -directive default

# Add pre-placement commands


# Placement

place_design -directive default

# Placement report

report_utilization -hierarchical -hierarchical_depth 4 -hierarchical_percentages -file cmod7_utilization_hierarchical_place.rpt
report_utilization -file cmod7_utilization_place.rpt
report_io -file cmod7_io.rpt
report_control_sets -verbose -file cmod7_control_sets.rpt
report_clock_utilization -file cmod7_clock_utilization.rpt

# Add pre-routing commands


# Routing

route_design -directive default
phys_opt_design -directive default
write_checkpoint -force cmod7_route.dcp

# Routing report

report_timing_summary -no_header -no_detailed_paths
report_route_status -file cmod7_route_status.rpt
report_drc -file cmod7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file cmod7_timing.rpt
report_power -file cmod7_power.rpt

# Bitstream generation

write_bitstream -force cmod7.bit

# End

quit
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