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litex

master
openpowerwtf 4 months ago
parent
commit
35b0e7ee69
  1. 15
      dev/build/litex/build/cmod7/gateware/.Xil/cmod7_propImpl.xdc
  2. 3
      dev/build/litex/build/cmod7/gateware/build_cmod7.sh
  3. 3
      dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/project.wpc
  4. 42
      dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis.wdf
  5. 3
      dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis_details.wdf
  6. 6
      dev/build/litex/build/cmod7/gateware/cmod7.hw/cmod7.lpr
  7. 81
      dev/build/litex/build/cmod7/gateware/cmod7.tcl
  8. 1891
      dev/build/litex/build/cmod7/gateware/cmod7.v
  9. 54
      dev/build/litex/build/cmod7/gateware/cmod7.xdc
  10. 2352
      dev/build/litex/build/cmod7/gateware/cmod7.xpr
  11. 0
      dev/build/litex/build/cmod7/gateware/cmod7_main_ram.init
  12. 29
      dev/build/litex/build/cmod7/gateware/cmod7_mem.init
  13. 3790
      dev/build/litex/build/cmod7/gateware/cmod7_rom.init
  14. 0
      dev/build/litex/build/cmod7/gateware/cmod7_sram.init
  15. 866
      dev/build/litex/build/cmod7/gateware/cmod7_timing_synth.rpt
  16. 9897
      dev/build/litex/build/cmod7/gateware/cmod7_utilization_hierarchical_synth.rpt
  17. 200
      dev/build/litex/build/cmod7/gateware/cmod7_utilization_synth.rpt
  18. 357
      dev/build/litex/build/cmod7/software/include/generated/csr.h
  19. 8
      dev/build/litex/build/cmod7/software/include/generated/git.h
  20. 30
      dev/build/litex/build/cmod7/software/include/generated/mem.h
  21. 1
      dev/build/litex/build/cmod7/software/include/generated/output_format.ld
  22. 6
      dev/build/litex/build/cmod7/software/include/generated/regions.ld
  23. 65
      dev/build/litex/build/cmod7/software/include/generated/soc.h
  24. 26
      dev/build/litex/build/cmod7/software/include/generated/variables.mak
  25. 1
      dev/build/verilog

15
dev/build/litex/build/cmod7/gateware/.Xil/cmod7_propImpl.xdc

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set_property SRC_FILE_INFO {cfile:/data/projects/a2o/dev/build/litex/build/cmod7/gateware/cmod7.xdc rfile:../cmod7.xdc id:1 order:EARLY} [current_design]
set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC J18 [get_ports {serial_tx}]
set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC J17 [get_ports {serial_rx}]
set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC L17 [get_ports {clk12}]
set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC A17 [get_ports {user_led0}]
set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC C16 [get_ports {user_led1}]
set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC A18 [get_ports {user_btn0}]
set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC B18 [get_ports {user_btn1}]

3
dev/build/litex/build/cmod7/gateware/build_cmod7.sh

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# Autogenerated by LiteX / git: 6932fc51
set -e
vivado -mode batch -source cmod7.tcl

3
dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/project.wpc vendored

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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:

42
dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis.wdf vendored

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version:1
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eof:4023463222

3
dev/build/litex/build/cmod7/gateware/cmod7.cache/wt/synthesis_details.wdf vendored

@ -0,0 +1,3 @@ @@ -0,0 +1,3 @@
version:1
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
eof:2511430288

6
dev/build/litex/build/cmod7/gateware/cmod7.hw/cmod7.lpr

@ -0,0 +1,6 @@ @@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->

<labtools version="1" minor="0"/>

81
dev/build/litex/build/cmod7/gateware/cmod7.tcl

@ -0,0 +1,81 @@ @@ -0,0 +1,81 @@

# Create Project

create_project -force -name cmod7 -part xc7a200t-SBG484-1
set_msg_config -id {Common 17-55} -new_severity {Warning}

# Add Sources

add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/a2o_litex}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/trilib}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/trilib_clk1x}
add_files {/data/projects/a2o/dev/build/litex/a2o/verilog/work}
read_verilog {/data/projects/a2o/dev/build/litex/build/cmod7/gateware/cmod7.v}

# Add EDIFs


# Add IPs


# Add constraints

read_xdc cmod7.xdc
set_property PROCESSING_ORDER EARLY [get_files cmod7.xdc]

# Add pre-synthesis commands


# Synthesis

synth_design -directive default -top cmod7 -part xc7a200t-SBG484-1

# Synthesis report

report_timing_summary -file cmod7_timing_synth.rpt
report_utilization -hierarchical -file cmod7_utilization_hierarchical_synth.rpt
report_utilization -file cmod7_utilization_synth.rpt

# Optimize design

opt_design -directive default

# Add pre-placement commands


# Placement

place_design -directive default

# Placement report

report_utilization -hierarchical -file cmod7_utilization_hierarchical_place.rpt
report_utilization -file cmod7_utilization_place.rpt
report_io -file cmod7_io.rpt
report_control_sets -verbose -file cmod7_control_sets.rpt
report_clock_utilization -file cmod7_clock_utilization.rpt

# Add pre-routing commands


# Routing

route_design -directive default
phys_opt_design -directive default
write_checkpoint -force cmod7_route.dcp

# Routing report

report_timing_summary -no_header -no_detailed_paths
report_route_status -file cmod7_route_status.rpt
report_drc -file cmod7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file cmod7_timing.rpt
report_power -file cmod7_power.rpt

# Bitstream generation

write_bitstream -force cmod7.bit

# End

quit

1891
dev/build/litex/build/cmod7/gateware/cmod7.v

File diff suppressed because it is too large Load Diff

54
dev/build/litex/build/cmod7/gateware/cmod7.xdc

@ -0,0 +1,54 @@ @@ -0,0 +1,54 @@
################################################################################
# IO constraints
################################################################################
# serial:0.tx
set_property LOC J18 [get_ports {serial_tx}]
set_property IOSTANDARD LVCMOS33 [get_ports {serial_tx}]

# serial:0.rx
set_property LOC J17 [get_ports {serial_rx}]
set_property IOSTANDARD LVCMOS33 [get_ports {serial_rx}]

# clk12:0
set_property LOC L17 [get_ports {clk12}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk12}]

# user_led:0
set_property LOC A17 [get_ports {user_led0}]
set_property IOSTANDARD LVCMOS33 [get_ports {user_led0}]

# user_led:1
set_property LOC C16 [get_ports {user_led1}]
set_property IOSTANDARD LVCMOS33 [get_ports {user_led1}]

# user_btn:0
set_property LOC A18 [get_ports {user_btn0}]
set_property IOSTANDARD LVCMOS33 [get_ports {user_btn0}]

# user_btn:1
set_property LOC B18 [get_ports {user_btn1}]
set_property IOSTANDARD LVCMOS33 [get_ports {user_btn1}]

################################################################################
# Design constraints
################################################################################

################################################################################
# Clock constraints
################################################################################


create_clock -name clk12 -period 83.333 [get_ports clk12]

set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets crg_clkin]] -asynchronous

################################################################################
# False path constraints
################################################################################


set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]

set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]

set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]

2352
dev/build/litex/build/cmod7/gateware/cmod7.xpr

File diff suppressed because it is too large Load Diff

0
dev/build/litex/build/cmod7/gateware/cmod7_main_ram.init

29
dev/build/litex/build/cmod7/gateware/cmod7_mem.init

@ -0,0 +1,29 @@ @@ -0,0 +1,29 @@
41
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2d
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2d
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20
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3a
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3a
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30
00

3790
dev/build/litex/build/cmod7/gateware/cmod7_rom.init

File diff suppressed because it is too large Load Diff

0
dev/build/litex/build/cmod7/gateware/cmod7_sram.init

866
dev/build/litex/build/cmod7/gateware/cmod7_timing_synth.rpt

@ -0,0 +1,866 @@ @@ -0,0 +1,866 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date : Wed Aug 3 07:40:26 2022
| Host : GatorCountry running 64-bit Ubuntu 20.04.4 LTS
| Command : report_timing_summary -file cmod7_timing_synth.rpt
| Design : cmod7
| Device : 7a200t-sbg484
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes

Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (828)
5. checking no_input_delay (3)
6. checking no_output_delay (3)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (828)
--------------------------------------------------
There are 0 pins that are not constrained for maximum delay.

There are 828 pins that are not constrained for maximum delay due to constant clock. (MEDIUM)


5. checking no_input_delay (3)
------------------------------
There are 3 input ports with no input delay specified. (HIGH)

There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (3)
-------------------------------
There are 3 ports with no output delay specified. (HIGH)

There are 0 ports with no output delay but user has a false path constraint

There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.831 0.000 0 130983 0.011 0.000 0 130983 0.264 0.000 0 90094


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk12 {0.000 41.666} 83.333 12.000
basesoc_mmcm_fb {0.000 41.666} 83.333 12.000
crg_clkout0 {0.000 10.000} 20.000 50.000
crg_clkout1 {0.000 5.000} 10.000 100.000
crg_clkout2 {0.000 2.500} 5.000 200.001


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk12 82.121 0.000 0 7 0.150 0.000 0 7 16.667 0.000 0 10
basesoc_mmcm_fb 16.667 0.000 0 2
crg_clkout0 0.831 0.000 0 130696 0.011 0.000 0 130696 8.750 0.000 0 89885
crg_clkout1 4.643 0.000 0 266 0.201 0.000 0 266 4.500 0.000 0 187
crg_clkout2 0.885 0.000 0 14 0.011 0.000 0 14 0.264 0.000 0 10


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock: clk12
To Clock: clk12

Setup : 0 Failing Endpoints, Worst Slack 82.121ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.150ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 16.667ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 82.121ns (required time - arrival time)
Source: FDCE/C
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Destination: FDCE_1/D
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Path Group: clk12
Path Type: Setup (Max at Slow Process Corner)
Requirement: 83.333ns (clk12 rise@83.333ns - clk12 rise@0.000ns)
Data Path Delay: 0.830ns (logic 0.496ns (59.759%) route 0.334ns (40.241%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.194ns = ( 86.527 - 83.333 )
Source Clock Delay (SCD): 3.623ns
Clock Pessimism Removal (CPR): 0.284ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk12 rise edge) 0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.623 crg_clkin
FDCE r FDCE/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.496 4.119 r FDCE/Q
net (fo=1, unplaced) 0.334 4.453 basesoc_reset0
FDCE r FDCE_1/D
------------------------------------------------------------------- -------------------

(clock clk12 rise edge) 83.333 83.333 r
0.000 83.333 r clk12 (IN)
net (fo=0) 0.000 83.333 clk12
IBUF (Prop_ibuf_I_O) 1.365 84.698 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.760 85.458 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.091 85.549 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 85.988 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.100 86.088 r clk12_inst/O
net (fo=9, unplaced) 0.439 86.527 crg_clkin
FDCE r FDCE_1/C
clock pessimism 0.284 86.811
clock uncertainty -0.035 86.776
FDCE (Setup_fdce_C_D) -0.202 86.574 FDCE_1
-------------------------------------------------------------------
required time 86.574
arrival time -4.453
-------------------------------------------------------------------
slack 82.121





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.150ns (arrival time - required time)
Source: FDCE/C
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Destination: FDCE_1/D
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Path Group: clk12
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk12 rise@0.000ns - clk12 rise@0.000ns)
Data Path Delay: 0.299ns (logic 0.158ns (52.880%) route 0.141ns (47.120%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.349ns
Source Clock Delay (SCD): 0.840ns
Clock Pessimism Removal (CPR): 0.364ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk12 rise edge) 0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.840 crg_clkin
FDCE r FDCE/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.158 0.998 r FDCE/Q
net (fo=1, unplaced) 0.141 1.139 basesoc_reset0
FDCE r FDCE_1/D
------------------------------------------------------------------- -------------------

(clock clk12 rise edge) 0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.349 crg_clkin
FDCE r FDCE_1/C
clock pessimism -0.364 0.985
FDCE (Hold_fdce_C_D) 0.004 0.989 FDCE_1
-------------------------------------------------------------------
required time -0.989
arrival time 1.139
-------------------------------------------------------------------
slack 0.150





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk12
Waveform(ns): { 0.000 41.667 }
Period(ns): 83.333
Sources: { clk12 }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 83.333 81.178 clk12_IBUF_BUFG_inst/I
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 83.333 16.667 MMCME2_ADV/CLKIN1
Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 10.000 41.666 31.666 MMCME2_ADV/CLKIN1
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 10.000 41.666 31.666 MMCME2_ADV/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock: basesoc_mmcm_fb
To Clock: basesoc_mmcm_fb

Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 16.667ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: basesoc_mmcm_fb
Waveform(ns): { 0.000 41.667 }
Period(ns): 83.333
Sources: { MMCME2_ADV/CLKFBOUT }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 83.333 82.084 MMCME2_ADV/CLKFBOUT
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 83.333 16.667 MMCME2_ADV/CLKFBIN



---------------------------------------------------------------------------------------------------
From Clock: crg_clkout0
To Clock: crg_clkout0

Setup : 0 Failing Endpoints, Worst Slack 0.831ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.831ns (required time - arrival time)
Source: FDPE/C
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: FDPE_1/D
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: crg_clkout0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.000ns (MaxDelay Path 2.000ns)
Data Path Delay: 0.657ns (logic 0.456ns (69.406%) route 0.201ns (30.594%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.567ns
Source Clock Delay (SCD): 5.191ns
Clock Pessimism Removal (CPR): 0.479ns
Clock Uncertainty: 0.300ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.597ns
Phase Error (PE): 0.000ns
Timing Exception: MaxDelay Path 2.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout0 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.623 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.088 3.711 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.800 4.511 crg_clkout0
BUFG (Prop_bufg_I_O) 0.096 4.607 r BUFG/O
net (fo=89883, unplaced) 0.584 5.191 sys_clk
FDPE r FDPE/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.456 5.647 r FDPE/Q
net (fo=1, unplaced) 0.201 5.848 xilinxasyncresetsynchronizerimpl0_rst_meta
FDPE r FDPE_1/D
------------------------------------------------------------------- -------------------

max delay 2.000 2.000
0.000 2.000 r clk12 (IN)
net (fo=0) 0.000 2.000 clk12
IBUF (Prop_ibuf_I_O) 1.365 3.365 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.760 4.125 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.091 4.216 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 4.655 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.100 4.755 r clk12_inst/O
net (fo=9, unplaced) 0.439 5.194 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 5.277 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.760 6.037 crg_clkout0
BUFG (Prop_bufg_I_O) 0.091 6.128 r BUFG/O
net (fo=89883, unplaced) 0.439 6.567 sys_clk
FDPE r FDPE_1/C
clock pessimism 0.479 7.046
clock uncertainty -0.300 6.745
FDPE (Setup_fdpe_C_D) -0.067 6.678 FDPE_1
-------------------------------------------------------------------
required time 6.678
arrival time -5.848
-------------------------------------------------------------------
slack 0.831





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.011ns (arrival time - required time)
Source: FDPE/C
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: FDPE_1/D
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: crg_clkout0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (crg_clkout0 rise@0.000ns - crg_clkout0 rise@0.000ns)
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.045ns
Source Clock Delay (SCD): 1.367ns
Clock Pessimism Removal (CPR): 0.533ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout0 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.840 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.050 0.890 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.337 1.227 crg_clkout0
BUFG (Prop_bufg_I_O) 0.026 1.253 r BUFG/O
net (fo=89883, unplaced) 0.114 1.367 sys_clk
FDPE r FDPE/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.141 1.508 r FDPE/Q
net (fo=1, unplaced) 0.085 1.593 xilinxasyncresetsynchronizerimpl0_rst_meta
FDPE r FDPE_1/D
------------------------------------------------------------------- -------------------

(clock crg_clkout0 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.349 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 1.402 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.355 1.757 crg_clkout0
BUFG (Prop_bufg_I_O) 0.029 1.786 r BUFG/O
net (fo=89883, unplaced) 0.259 2.045 sys_clk
FDPE r FDPE_1/C
clock pessimism -0.533 1.512
FDPE (Hold_fdpe_C_D) 0.070 1.582 FDPE_1
-------------------------------------------------------------------
required time -1.582
arrival time 1.593
-------------------------------------------------------------------
slack 0.011





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: crg_clkout0
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { MMCME2_ADV/CLKOUT0 }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 a2owb/c0/lq0/ctl/dc32Kdir64B.arr/arr5_F/CLKARDCLK
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 20.000 193.360 MMCME2_ADV/CLKOUT0
Low Pulse Width Slow RAMD64E/CLK n/a 1.250 10.000 8.750 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK
High Pulse Width Fast RAMD64E/CLK n/a 1.250 10.000 8.750 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK



---------------------------------------------------------------------------------------------------
From Clock: crg_clkout1
To Clock: crg_clkout1

Setup : 0 Failing Endpoints, Worst Slack 4.643ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.201ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 4.643ns (required time - arrival time)
Source: a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
(rising edge-triggered cell RAMB36E1 clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: a2owb/c0/iuq0/bht2/bht0/bram0a/DIADI[16]
(rising edge-triggered cell RAMB36E1 clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: crg_clkout1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (crg_clkout1 rise@10.000ns - crg_clkout1 rise@0.000ns)
Data Path Delay: 4.203ns (logic 2.604ns (61.949%) route 1.599ns (38.051%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.567ns = ( 14.567 - 10.000 )
Source Clock Delay (SCD): 5.191ns
Clock Pessimism Removal (CPR): 0.479ns
Clock Uncertainty: 0.272ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.539ns
Phase Error (PE): 0.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout1 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.623 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.088 3.711 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.800 4.511 crg_clkout1
BUFG (Prop_bufg_I_O) 0.096 4.607 r BUFG_1/O
net (fo=185, unplaced) 0.584 5.191 a2owb/c0/iuq0/bht2/bht0/sys2x_clk
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
------------------------------------------------------------------- -------------------
RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[16])
2.454 7.645 r a2owb/c0/iuq0/bht2/bht0/bram0a/DOADO[16]
net (fo=1, unplaced) 0.800 8.445 a2owb/c0/iuq0/bht2/bht0/r_data_out_0_bram[20]
LUT2 (Prop_lut2_I0_O) 0.150 8.595 r a2owb/c0/iuq0/bht2/bht0/bram0a_i_17__1/O
net (fo=1, unplaced) 0.800 9.394 a2owb/c0/iuq0/bht2/bht0/w_data_in_0[15]
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/DIADI[16]
------------------------------------------------------------------- -------------------

(clock crg_clkout1 rise edge)
10.000 10.000 r
0.000 10.000 r clk12 (IN)
net (fo=0) 0.000 10.000 clk12
IBUF (Prop_ibuf_I_O) 1.365 11.365 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.760 12.125 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.091 12.216 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 12.655 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.100 12.755 r clk12_inst/O
net (fo=9, unplaced) 0.439 13.194 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.083 13.277 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.760 14.037 crg_clkout1
BUFG (Prop_bufg_I_O) 0.091 14.128 r BUFG_1/O
net (fo=185, unplaced) 0.439 14.567 a2owb/c0/iuq0/bht2/bht0/sys2x_clk
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
clock pessimism 0.479 15.046
clock uncertainty -0.272 14.774
RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[16])
-0.737 14.037 a2owb/c0/iuq0/bht2/bht0/bram0a
-------------------------------------------------------------------
required time 14.037
arrival time -9.394
-------------------------------------------------------------------
slack 4.643





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.201ns (arrival time - required time)
Source: a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/C
(rising edge-triggered cell FDRE clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/D
(rising edge-triggered cell FDRE clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: crg_clkout1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (crg_clkout1 rise@0.000ns - crg_clkout1 rise@0.000ns)
Data Path Delay: 0.437ns (logic 0.239ns (54.677%) route 0.198ns (45.323%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.045ns
Source Clock Delay (SCD): 1.367ns
Clock Pessimism Removal (CPR): 0.533ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout1 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.840 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.050 0.890 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.337 1.227 crg_clkout1
BUFG (Prop_bufg_I_O) 0.026 1.253 r BUFG_1/O
net (fo=185, unplaced) 0.114 1.367 a2owb/c0/iuq0/bht0/bht0/sys2x_clk
FDRE r a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.141 1.508 r a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/Q
net (fo=1, unplaced) 0.198 1.706 a2owb/c0/iuq0/bht0/bht0/toggle2x_q
LUT2 (Prop_lut2_I0_O) 0.098 1.804 r a2owb/c0/iuq0/bht0/bht0/gate_fq_i_1__1/O
net (fo=1, unplaced) 0.000 1.804 a2owb/c0/iuq0/bht0/bht0/gate_d
FDRE r a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/D
------------------------------------------------------------------- -------------------

(clock crg_clkout1 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.349 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.053 1.402 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.355 1.757 crg_clkout1
BUFG (Prop_bufg_I_O) 0.029 1.786 r BUFG_1/O
net (fo=185, unplaced) 0.259 2.045 a2owb/c0/iuq0/bht0/bht0/sys2x_clk
FDRE r a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/C
clock pessimism -0.533 1.512
FDRE (Hold_fdre_C_D) 0.091 1.603 a2owb/c0/iuq0/bht0/bht0/gate_fq_reg
-------------------------------------------------------------------
required time -1.603
arrival time 1.804
-------------------------------------------------------------------
slack 0.201





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: crg_clkout1
Waveform(ns): { 0.000 5.000 }
Period(ns): 10.000
Sources: { MMCME2_ADV/CLKOUT1 }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 10.000 7.424 a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 10.000 203.360 MMCME2_ADV/CLKOUT1
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 a2owb/c0/iuq0/bht1/bht0/gate_fq_reg/C
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 a2owb/c0/iuq0/bht1/bht0/gate_fq_reg/C



---------------------------------------------------------------------------------------------------
From Clock: crg_clkout2
To Clock: crg_clkout2

Setup : 0 Failing Endpoints, Worst Slack 0.885ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.885ns (required time - arrival time)
Source: FDPE_4/C
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: FDPE_5/D
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: crg_clkout2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.000ns (MaxDelay Path 2.000ns)
Data Path Delay: 0.657ns (logic 0.456ns (69.406%) route 0.201ns (30.594%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.567ns
Source Clock Delay (SCD): 5.191ns
Clock Pessimism Removal (CPR): 0.479ns
Clock Uncertainty: 0.246ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.487ns
Phase Error (PE): 0.000ns
Timing Exception: MaxDelay Path 2.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout2 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 1.435 1.435 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.800 2.235 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.096 2.331 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.915 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.124 3.039 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.623 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 3.711 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.800 4.511 crg_clkout2
BUFG (Prop_bufg_I_O) 0.096 4.607 r BUFG_2/O
net (fo=8, unplaced) 0.584 5.191 idelay_clk
FDPE r FDPE_4/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.456 5.647 r FDPE_4/Q
net (fo=1, unplaced) 0.201 5.848 xilinxasyncresetsynchronizerimpl2_rst_meta
FDPE r FDPE_5/D
------------------------------------------------------------------- -------------------

max delay 2.000 2.000
0.000 2.000 r clk12 (IN)
net (fo=0) 0.000 2.000 clk12
IBUF (Prop_ibuf_I_O) 1.365 3.365 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.760 4.125 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.091 4.216 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 4.655 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.100 4.755 r clk12_inst/O
net (fo=9, unplaced) 0.439 5.194 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 5.277 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.760 6.037 crg_clkout2
BUFG (Prop_bufg_I_O) 0.091 6.128 r BUFG_2/O
net (fo=8, unplaced) 0.439 6.567 idelay_clk
FDPE r FDPE_5/C
clock pessimism 0.479 7.046
clock uncertainty -0.246 6.800
FDPE (Setup_fdpe_C_D) -0.067 6.733 FDPE_5
-------------------------------------------------------------------
required time 6.733
arrival time -5.848
-------------------------------------------------------------------
slack 0.885





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.011ns (arrival time - required time)
Source: FDPE_4/C
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: FDPE_5/D
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: crg_clkout2
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (crg_clkout2 rise@0.000ns - crg_clkout2 rise@0.000ns)
Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.045ns
Source Clock Delay (SCD): 1.367ns
Clock Pessimism Removal (CPR): 0.533ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout2 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.204 0.204 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.541 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.567 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.681 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.045 0.726 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.840 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 0.890 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.337 1.227 crg_clkout2
BUFG (Prop_bufg_I_O) 0.026 1.253 r BUFG_2/O
net (fo=8, unplaced) 0.114 1.367 idelay_clk
FDPE r FDPE_4/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.141 1.508 r FDPE_4/Q
net (fo=1, unplaced) 0.085 1.593 xilinxasyncresetsynchronizerimpl2_rst_meta
FDPE r FDPE_5/D
------------------------------------------------------------------- -------------------

(clock crg_clkout2 rise edge)
0.000 0.000 r
0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
IBUF (Prop_ibuf_I_O) 0.391 0.391 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.746 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.029 0.775 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.034 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.056 1.090 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.349 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 1.402 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.355 1.757 crg_clkout2
BUFG (Prop_bufg_I_O) 0.029 1.786 r BUFG_2/O
net (fo=8, unplaced) 0.259 2.045 idelay_clk
FDPE r FDPE_5/C
clock pessimism -0.533 1.512
FDPE (Hold_fdpe_C_D) 0.070 1.582 FDPE_5
-------------------------------------------------------------------
required time -1.582
arrival time 1.593
-------------------------------------------------------------------
slack 0.011





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: crg_clkout2
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { MMCME2_ADV/CLKOUT2 }

Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a IDELAYCTRL/REFCLK n/a 3.225 5.000 1.775 IDELAYCTRL/REFCLK
Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL/REFCLK
Low Pulse Width Fast FDPE/C n/a 0.500 2.500 2.000 FDPE_4/C
High Pulse Width Slow FDPE/C n/a 0.500 2.500 2.000 FDPE_4/C



9897
dev/build/litex/build/cmod7/gateware/cmod7_utilization_hierarchical_synth.rpt

File diff suppressed because it is too large Load Diff

200
dev/build/litex/build/cmod7/gateware/cmod7_utilization_synth.rpt

@ -0,0 +1,200 @@ @@ -0,0 +1,200 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date : Wed Aug 3 07:40:33 2022
| Host : GatorCountry running 64-bit Ubuntu 20.04.4 LTS
| Command : report_utilization -file cmod7_utilization_synth.rpt
| Design : cmod7
| Device : 7a200tsbg484-1
| Design State : Synthesized
------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists

1. Slice Logic
--------------

+----------------------------+--------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+--------+-------+-----------+--------+
| Slice LUTs* | 231525 | 0 | 134600 | 172.01 |
| LUT as Logic | 230967 | 0 | 134600 | 171.60 |
| LUT as Memory | 558 | 0 | 46200 | 1.21 |
| LUT as Distributed RAM | 556 | 0 | | |
| LUT as Shift Register | 2 | 0 | | |
| Slice Registers | 89333 | 0 | 269200 | 33.18 |
| Register as Flip Flop | 89333 | 0 | 269200 | 33.18 |
| Register as Latch | 0 | 0 | 269200 | 0.00 |
| F7 Muxes | 8148 | 0 | 67300 | 12.11 |
| F8 Muxes | 3260 | 0 | 33650 | 9.69 |
+----------------------------+--------+-------+-----------+--------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 4 | Yes | - | Set |
| 8 | Yes | - | Reset |
| 903 | Yes | Set | - |
| 88418 | Yes | Reset | - |
+-------+--------------+-------------+--------------+


2. Memory
---------

+-------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+-------+-------+-----------+-------+
| Block RAM Tile | 101.5 | 0 | 365 | 27.81 |
| RAMB36/FIFO* | 95 | 0 | 365 | 26.03 |
| RAMB36E1 only | 95 | | | |
| RAMB18 | 13 | 0 | 730 | 1.78 |
| RAMB18E1 only | 13 | | | |
+-------------------+-------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


3. DSP
------

+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+-----------+-------+


4. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 7 | 3 | 285 | 2.46 |
| IOB Master Pads | 1 | | | |
| IOB Slave Pads | 2 | | | |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
| PHASER_REF | 0 | 0 | 10 | 0.00 |
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
| IN_FIFO | 0 | 0 | 40 | 0.00 |
| IDELAYCTRL | 1 | 0 | 10 | 10.00 |
| IBUFDS | 0 | 0 | 274 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+-----------+-------+


5. Clocking
-----------

+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
| BUFIO | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 1 | 0 | 10 | 10.00 |
| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
| BUFMRCE | 0 | 0 | 20 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 40 | 0.00 |
+------------+------+-------+-----------+-------+


6. Specific Feature
-------------------

+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+


7. Primitives
-------------

+------------+--------+---------------------+
| Ref Name | Used | Functional Category |
+------------+--------+---------------------+
| LUT6 | 121905 | LUT |
| FDRE | 88418 | Flop & Latch |
| LUT5 | 62878 | LUT |
| LUT4 | 40414 | LUT |
| LUT3 | 14779 | LUT |
| MUXF7 | 8148 | MuxFx |
| LUT2 | 5981 | LUT |
| MUXF8 | 3260 | MuxFx |
| FDSE | 903 | Flop & Latch |
| CARRY4 | 751 | CarryLogic |
| RAMD64E | 540 | Distributed Memory |
| LUT1 | 473 | LUT |
| RAMB36E1 | 95 | Block Memory |
| RAMD32 | 24 | Distributed Memory |
| RAMB18E1 | 13 | Block Memory |
| RAMS32 | 8 | Distributed Memory |
| FDCE | 8 | Flop & Latch |
| IBUF | 4 | IO |
| FDPE | 4 | Flop & Latch |
| BUFG | 4 | Clock |
| OBUF | 3 | IO |
| SRL16E | 2 | Distributed Memory |
| MMCME2_ADV | 1 | Clock |
| IDELAYCTRL | 1 | IO |
+------------+--------+---------------------+


8. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


9. Instantiated Netlists
------------------------

+----------+------+
| Ref Name | Used |
+----------+------+


357
dev/build/litex/build/cmod7/software/include/generated/csr.h

@ -0,0 +1,357 @@ @@ -0,0 +1,357 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41
//--------------------------------------------------------------------------------
#include <generated/soc.h>
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
#include <stdint.h>
#include <system.h>
#ifndef CSR_ACCESSORS_DEFINED
#include <hw/common.h>
#endif /* ! CSR_ACCESSORS_DEFINED */
#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#endif

/* leds */
#define CSR_LEDS_BASE (CSR_BASE + 0x1800L)
#define CSR_LEDS_OUT_ADDR (CSR_BASE + 0x1800L)
#define CSR_LEDS_OUT_SIZE 1
static inline uint32_t leds_out_read(void) {
return csr_read_simple((CSR_BASE + 0x1800L));
}
static inline void leds_out_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x1800L));
}

/* buttons */
#define CSR_BUTTONS_BASE (CSR_BASE + 0x2000L)
#define CSR_BUTTONS_IN_ADDR (CSR_BASE + 0x2000L)
#define CSR_BUTTONS_IN_SIZE 1
static inline uint32_t buttons_in_read(void) {
return csr_read_simple((CSR_BASE + 0x2000L));
}

/* ctrl */
#define CSR_CTRL_BASE (CSR_BASE + 0x2800L)
#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x2800L)
#define CSR_CTRL_RESET_SIZE 1
static inline uint32_t ctrl_reset_read(void) {
return csr_read_simple((CSR_BASE + 0x2800L));
}
static inline void ctrl_reset_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x2800L));
}
#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
#define CSR_CTRL_RESET_SOC_RST_SIZE 1
static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t ctrl_reset_soc_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_soc_rst_extract(word);
}
static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
#define CSR_CTRL_RESET_CPU_RST_SIZE 1
static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t ctrl_reset_cpu_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_cpu_rst_extract(word);
}
static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x2804L)
#define CSR_CTRL_SCRATCH_SIZE 1
static inline uint32_t ctrl_scratch_read(void) {
return csr_read_simple((CSR_BASE + 0x2804L));
}
static inline void ctrl_scratch_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x2804L));
}
#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x2808L)
#define CSR_CTRL_BUS_ERRORS_SIZE 1
static inline uint32_t ctrl_bus_errors_read(void) {
return csr_read_simple((CSR_BASE + 0x2808L));
}

/* identifier_mem */
#define CSR_IDENTIFIER_MEM_BASE (CSR_BASE + 0x3000L)

/* timer0 */
#define CSR_TIMER0_BASE (CSR_BASE + 0x3800L)
#define CSR_TIMER0_LOAD_ADDR (CSR_BASE + 0x3800L)
#define CSR_TIMER0_LOAD_SIZE 1
static inline uint32_t timer0_load_read(void) {
return csr_read_simple((CSR_BASE + 0x3800L));
}
static inline void timer0_load_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x3800L));
}
#define CSR_TIMER0_RELOAD_ADDR (CSR_BASE + 0x3804L)
#define CSR_TIMER0_RELOAD_SIZE 1
static inline uint32_t timer0_reload_read(void) {
return csr_read_simple((CSR_BASE + 0x3804L));
}
static inline void timer0_reload_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x3804L));
}
#define CSR_TIMER0_EN_ADDR (CSR_BASE + 0x3808L)
#define CSR_TIMER0_EN_SIZE 1
static inline uint32_t timer0_en_read(void) {
return csr_read_simple((CSR_BASE + 0x3808L));
}
static inline void timer0_en_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x3808L));
}
#define CSR_TIMER0_UPDATE_VALUE_ADDR (CSR_BASE + 0x380cL)
#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
static inline uint32_t timer0_update_value_read(void) {
return csr_read_simple((CSR_BASE + 0x380cL));
}
static inline void timer0_update_value_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x380cL));
}
#define CSR_TIMER0_VALUE_ADDR (CSR_BASE + 0x3810L)
#define CSR_TIMER0_VALUE_SIZE 1
static inline uint32_t timer0_value_read(void) {
return csr_read_simple((CSR_BASE + 0x3810L));
}
#define CSR_TIMER0_EV_STATUS_ADDR (CSR_BASE + 0x3814L)
#define CSR_TIMER0_EV_STATUS_SIZE 1
static inline uint32_t timer0_ev_status_read(void) {
return csr_read_simple((CSR_BASE + 0x3814L));
}
#define CSR_TIMER0_EV_STATUS_ZERO_OFFSET 0
#define CSR_TIMER0_EV_STATUS_ZERO_SIZE 1
static inline uint32_t timer0_ev_status_zero_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_status_zero_read(void) {
uint32_t word = timer0_ev_status_read();
return timer0_ev_status_zero_extract(word);
}
#define CSR_TIMER0_EV_PENDING_ADDR (CSR_BASE + 0x3818L)
#define CSR_TIMER0_EV_PENDING_SIZE 1
static inline uint32_t timer0_ev_pending_read(void) {
return csr_read_simple((CSR_BASE + 0x3818L));
}
static inline void timer0_ev_pending_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x3818L));
}
#define CSR_TIMER0_EV_PENDING_ZERO_OFFSET 0
#define CSR_TIMER0_EV_PENDING_ZERO_SIZE 1
static inline uint32_t timer0_ev_pending_zero_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_pending_zero_read(void) {
uint32_t word = timer0_ev_pending_read();
return timer0_ev_pending_zero_extract(word);
}
static inline uint32_t timer0_ev_pending_zero_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void timer0_ev_pending_zero_write(uint32_t plain_value) {
uint32_t oldword = timer0_ev_pending_read();
uint32_t newword = timer0_ev_pending_zero_replace(oldword, plain_value);
timer0_ev_pending_write(newword);
}
#define CSR_TIMER0_EV_ENABLE_ADDR (CSR_BASE + 0x381cL)
#define CSR_TIMER0_EV_ENABLE_SIZE 1
static inline uint32_t timer0_ev_enable_read(void) {
return csr_read_simple((CSR_BASE + 0x381cL));
}
static inline void timer0_ev_enable_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x381cL));
}
#define CSR_TIMER0_EV_ENABLE_ZERO_OFFSET 0
#define CSR_TIMER0_EV_ENABLE_ZERO_SIZE 1
static inline uint32_t timer0_ev_enable_zero_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_enable_zero_read(void) {
uint32_t word = timer0_ev_enable_read();
return timer0_ev_enable_zero_extract(word);
}
static inline uint32_t timer0_ev_enable_zero_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void timer0_ev_enable_zero_write(uint32_t plain_value) {
uint32_t oldword = timer0_ev_enable_read();
uint32_t newword = timer0_ev_enable_zero_replace(oldword, plain_value);
timer0_ev_enable_write(newword);
}

/* uart */
#define CSR_UART_BASE (CSR_BASE + 0x4000L)
#define CSR_UART_RXTX_ADDR (CSR_BASE + 0x4000L)
#define CSR_UART_RXTX_SIZE 1
static inline uint32_t uart_rxtx_read(void) {
return csr_read_simple((CSR_BASE + 0x4000L));
}
static inline void uart_rxtx_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x4000L));
}
#define CSR_UART_TXFULL_ADDR (CSR_BASE + 0x4004L)
#define CSR_UART_TXFULL_SIZE 1
static inline uint32_t uart_txfull_read(void) {
return csr_read_simple((CSR_BASE + 0x4004L));
}
#define CSR_UART_RXEMPTY_ADDR (CSR_BASE + 0x4008L)
#define CSR_UART_RXEMPTY_SIZE 1
static inline uint32_t uart_rxempty_read(void) {
return csr_read_simple((CSR_BASE + 0x4008L));
}
#define CSR_UART_EV_STATUS_ADDR (CSR_BASE + 0x400cL)
#define CSR_UART_EV_STATUS_SIZE 1
static inline uint32_t uart_ev_status_read(void) {
return csr_read_simple((CSR_BASE + 0x400cL));
}
#define CSR_UART_EV_STATUS_TX_OFFSET 0
#define CSR_UART_EV_STATUS_TX_SIZE 1
static inline uint32_t uart_ev_status_tx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_ev_status_tx_read(void) {
uint32_t word = uart_ev_status_read();
return uart_ev_status_tx_extract(word);
}
#define CSR_UART_EV_STATUS_RX_OFFSET 1
#define CSR_UART_EV_STATUS_RX_SIZE 1
static inline uint32_t uart_ev_status_rx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_ev_status_rx_read(void) {
uint32_t word = uart_ev_status_read();
return uart_ev_status_rx_extract(word);
}
#define CSR_UART_EV_PENDING_ADDR (CSR_BASE + 0x4010L)
#define CSR_UART_EV_PENDING_SIZE 1
static inline uint32_t uart_ev_pending_read(void) {
return csr_read_simple((CSR_BASE + 0x4010L));
}
static inline void uart_ev_pending_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x4010L));
}
#define CSR_UART_EV_PENDING_TX_OFFSET 0
#define CSR_UART_EV_PENDING_TX_SIZE 1
static inline uint32_t uart_ev_pending_tx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_ev_pending_tx_read(void) {
uint32_t word = uart_ev_pending_read();
return uart_ev_pending_tx_extract(word);
}
static inline uint32_t uart_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_ev_pending_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_ev_pending_read();
uint32_t newword = uart_ev_pending_tx_replace(oldword, plain_value);
uart_ev_pending_write(newword);
}
#define CSR_UART_EV_PENDING_RX_OFFSET 1
#define CSR_UART_EV_PENDING_RX_SIZE 1
static inline uint32_t uart_ev_pending_rx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_ev_pending_rx_read(void) {
uint32_t word = uart_ev_pending_read();
return uart_ev_pending_rx_extract(word);
}
static inline uint32_t uart_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_ev_pending_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_ev_pending_read();
uint32_t newword = uart_ev_pending_rx_replace(oldword, plain_value);
uart_ev_pending_write(newword);
}
#define CSR_UART_EV_ENABLE_ADDR (CSR_BASE + 0x4014L)
#define CSR_UART_EV_ENABLE_SIZE 1
static inline uint32_t uart_ev_enable_read(void) {
return csr_read_simple((CSR_BASE + 0x4014L));
}
static inline void uart_ev_enable_write(uint32_t v) {
csr_write_simple(v, (CSR_BASE + 0x4014L));
}
#define CSR_UART_EV_ENABLE_TX_OFFSET 0
#define CSR_UART_EV_ENABLE_TX_SIZE 1
static inline uint32_t uart_ev_enable_tx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_ev_enable_tx_read(void) {
uint32_t word = uart_ev_enable_read();
return uart_ev_enable_tx_extract(word);
}
static inline uint32_t uart_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_ev_enable_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_ev_enable_read();
uint32_t newword = uart_ev_enable_tx_replace(oldword, plain_value);
uart_ev_enable_write(newword);
}
#define CSR_UART_EV_ENABLE_RX_OFFSET 1
#define CSR_UART_EV_ENABLE_RX_SIZE 1
static inline uint32_t uart_ev_enable_rx_extract(uint32_t oldword) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_ev_enable_rx_read(void) {
uint32_t word = uart_ev_enable_read();
return uart_ev_enable_rx_extract(word);
}
static inline uint32_t uart_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((uint32_t)(1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_ev_enable_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_ev_enable_read();
uint32_t newword = uart_ev_enable_rx_replace(oldword, plain_value);
uart_ev_enable_write(newword);
}
#define CSR_UART_TXEMPTY_ADDR (CSR_BASE + 0x4018L)
#define CSR_UART_TXEMPTY_SIZE 1
static inline uint32_t uart_txempty_read(void) {
return csr_read_simple((CSR_BASE + 0x4018L));
}
#define CSR_UART_RXFULL_ADDR (CSR_BASE + 0x401cL)
#define CSR_UART_RXFULL_SIZE 1
static inline uint32_t uart_rxfull_read(void) {
return csr_read_simple((CSR_BASE + 0x401cL));
}

#endif

8
dev/build/litex/build/cmod7/software/include/generated/git.h

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41
//--------------------------------------------------------------------------------
#ifndef __GENERATED_GIT_H
#define __GENERATED_GIT_H

#define LITEX_GIT_SHA1 "6932fc51"
#endif

30
dev/build/litex/build/cmod7/software/include/generated/mem.h

@ -0,0 +1,30 @@ @@ -0,0 +1,30 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41
//--------------------------------------------------------------------------------
#ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H

#ifndef ROM_BASE
#define ROM_BASE 0x00000000L
#define ROM_SIZE 0x00010000
#endif

#ifndef SRAM_BASE
#define SRAM_BASE 0x00010000L
#define SRAM_SIZE 0x00010000
#endif

#ifndef MAIN_RAM_BASE
#define MAIN_RAM_BASE 0x00100000L
#define MAIN_RAM_SIZE 0x00000100
#endif

#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#define CSR_SIZE 0x00010000
#endif

#ifndef MEM_REGIONS
#define MEM_REGIONS "ROM 0x00000000 0x10000 \nSRAM 0x00010000 0x10000 \nMAIN_RAM 0x00100000 0x100 \nCSR 0xfff00000 0x10000 "
#endif
#endif

1