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@ -214,6 +214,8 @@ async def genClocks(dut, sim):
@@ -214,6 +214,8 @@ async def genClocks(dut, sim):
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await RisingEdge(dut.clk_1x) |
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dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.') |
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sim.ok = False |
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sim.fail = 'Max cycle reached.' |
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# ------------------------------------------------------------------------------------------------ |
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# Interfaces |
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@ -235,31 +237,33 @@ async def tb(dut):
@@ -235,31 +237,33 @@ async def tb(dut):
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sim = Sim(dut) |
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sim.mem = Memory(sim) |
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#sim.memFiles = ['../mem/boot_ieq1.bin.hex'] #wtf cmdline parm |
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sim.maxCycles = 2000 |
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''' |
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sim.memFiles = ['../mem/boot.bin.hex'] #wtf cmdline parm |
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for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc. |
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sim.mem.loadFile(sim.memFiles[i]) |
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''' |
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sim.memFiles = [ |
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{ |
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'addr': 0x00000000, |
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'file' : '../mem/test1/rom.init' |
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}, |
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{ |
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'addr': 0x10000000, |
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'file' : '../mem/test1/test.init' |
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} |
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] |
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for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc. |
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sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr']) |
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if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default: |
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sim.mem.write(sim.resetAddr, sim.resetOp) |
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sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.') |
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# dut.cocotb_icarus |
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# dut._log.info(sim.top.__dict__) |
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# {'_handle': <cocotb.simulator.gpi_sim_hdl at 0x55f8fa8a3aa0>, |
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# '_len': None, '_sub_handles': {}, '_invalid_sub_handles': set(), '_name': 'cocotb_icarus', |
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# '_type': 'GPI_MODULE', '_fullname': 'cocotb_icarus(GPI_MODULE)', '_path': 'cocotb_icarus.cocotb_icarus', |
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# '_log': <SimBaseLog cocotb.cocotb_icarus (INFO)>, '_def_name': 'cocotb_icarus', '_def_file': './cocotb_icarus.v', |
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# '_discovered': False |
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# } |
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# dut |
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# {'_handle': <cocotb.simulator.gpi_sim_hdl at 0x557757943540>, |
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# '_len': None, '_sub_handles': {'an_ac_pm_thread_stop': ModifiableObject(cocotb_icarus.an_ac_pm_thread_stop), |
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# 'cocotb_icarus': HierarchyObject(cocotb_icarus.cocotb_icarus with definition cocotb_icarus (at ./cocotb_icarus.v))}, |
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# '_invalid_sub_handles': set(), '_name': 'cocotb_icarus', '_type': 'GPI_MODULE', '_fullname': 'cocotb_icarus(GPI_MODULE)', |
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# '_path': 'cocotb_icarus', '_log': <SimBaseLog cocotb.cocotb_icarus (INFO)>, '_def_name': '', '_def_file': '', |
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# '_discovered': False |
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# init stuff |
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await init(dut, sim) |
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@ -294,8 +298,6 @@ async def tb(dut):
@@ -294,8 +298,6 @@ async def tb(dut):
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await RisingEdge(dut.clk_1x) |
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dut._log.info(f'[{sim.cycle:08d}] Threads enabled.') |
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# should await sim.done |
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await Timer((sim.maxCycles+100)*8, units='ns') |
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@ -303,5 +305,5 @@ async def tb(dut):
@@ -303,5 +305,5 @@ async def tb(dut):
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dut._log.info(f'[{sim.cycle:08d}] You has opulence.') |
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else: |
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dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!') |
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assert False, f'[{sim.cycle:08d}] {sim.fail}' |
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dut._log.info(f'[{sim.cycle:08d}] {sim.fail}') |
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assert False |
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